mirror of https://gitee.com/openkylin/linux.git
drm/msm/mdp5: Add plane blending operation support for MDP5 (v2)
This change is to add properties alpha/zpos/blend_mode to mdp5 plane for alpha blending operation to generate the blended output. v1: Initial change v2: Change "premultilied" property to enum (Rob's comment) Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> [Don't actually expose alpha/premultiplied props to userspace yet pending a chance for discussion and some userspace to exercise it] Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
jilai wang
Rob Clark
parent
4ff696eafa
commit
129877819c
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@ -160,7 +160,7 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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if (mdp5_crtc->ctl && !crtc->state->enable) {
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/* set STAGE_UNUSED for all layers */
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mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000);
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mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, NULL, 0, 0);
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mdp5_ctl_release(mdp5_crtc->ctl);
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mdp5_crtc->ctl = NULL;
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}
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@ -196,13 +196,9 @@ static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
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/*
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* blend_setup() - blend all the planes of a CRTC
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*
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* When border is enabled, the border color will ALWAYS be the base layer.
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* Therefore, the first plane (private RGB pipe) will start at STAGE0.
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* If disabled, the first plane starts at STAGE_BASE.
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*
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* Note:
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* Border is not enabled here because the private plane is exactly
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* the CRTC resolution.
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* If no base layer is available, border will be enabled as the base layer.
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* Otherwise all layers will be blended based on their stage calculated
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* in mdp5_crtc_atomic_check.
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*/
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static void blend_setup(struct drm_crtc *crtc)
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{
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@ -210,9 +206,14 @@ static void blend_setup(struct drm_crtc *crtc)
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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struct drm_plane *plane;
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const struct mdp5_cfg_hw *hw_cfg;
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uint32_t lm = mdp5_crtc->lm, blend_cfg = 0;
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struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
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const struct mdp_format *format;
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uint32_t lm = mdp5_crtc->lm;
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uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
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unsigned long flags;
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#define blender(stage) ((stage) - STAGE_BASE)
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uint8_t stage[STAGE_MAX + 1];
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int i, plane_cnt = 0;
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#define blender(stage) ((stage) - STAGE0)
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hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
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@ -222,33 +223,73 @@ static void blend_setup(struct drm_crtc *crtc)
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if (!mdp5_crtc->ctl)
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goto out;
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/* Collect all plane information */
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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enum mdp_mixer_stage_id stage =
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to_mdp5_plane_state(plane->state)->stage;
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/*
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* Note: This cannot happen with current implementation but
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* we need to check this condition once z property is added
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*/
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BUG_ON(stage > hw_cfg->lm.nb_stages);
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/* LM */
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mdp5_write(mdp5_kms,
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REG_MDP5_LM_BLEND_OP_MODE(lm, blender(stage)),
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MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
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MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST));
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
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blender(stage)), 0xff);
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
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blender(stage)), 0x00);
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/* CTL */
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blend_cfg |= mdp_ctl_blend_mask(mdp5_plane_pipe(plane), stage);
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DBG("%s: blending pipe %s on stage=%d", mdp5_crtc->name,
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pipe2name(mdp5_plane_pipe(plane)), stage);
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pstate = to_mdp5_plane_state(plane->state);
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pstates[pstate->stage] = pstate;
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stage[pstate->stage] = mdp5_plane_pipe(plane);
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plane_cnt++;
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}
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DBG("%s: lm%d: blend config = 0x%08x", mdp5_crtc->name, lm, blend_cfg);
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mdp5_ctl_blend(mdp5_crtc->ctl, lm, blend_cfg);
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/*
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* If there is no base layer, enable border color.
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* Although it's not possbile in current blend logic,
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* put it here as a reminder.
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*/
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if (!pstates[STAGE_BASE] && plane_cnt) {
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ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
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DBG("Border Color is enabled");
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}
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/* The reset for blending */
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for (i = STAGE0; i <= STAGE_MAX; i++) {
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if (!pstates[i])
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continue;
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format = to_mdp_format(
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msm_framebuffer_format(pstates[i]->base.fb));
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plane = pstates[i]->base.plane;
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blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
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MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
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fg_alpha = pstates[i]->alpha;
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bg_alpha = 0xFF - pstates[i]->alpha;
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DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
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if (format->alpha_enable && pstates[i]->premultiplied) {
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blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
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MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
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if (fg_alpha != 0xff) {
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bg_alpha = fg_alpha;
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blend_op |=
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MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
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MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
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} else {
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blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
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}
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} else if (format->alpha_enable) {
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blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
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MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
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if (fg_alpha != 0xff) {
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bg_alpha = fg_alpha;
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blend_op |=
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MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
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MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
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MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
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MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
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} else {
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blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
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}
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}
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
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blender(i)), blend_op);
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
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blender(i)), fg_alpha);
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mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
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blender(i)), bg_alpha);
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}
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mdp5_ctl_blend(mdp5_crtc->ctl, lm, stage, plane_cnt, ctl_blend_flags);
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out:
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spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
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@ -339,7 +380,8 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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struct drm_plane *plane;
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struct drm_device *dev = crtc->dev;
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struct plane_state pstates[STAGE3 + 1];
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struct plane_state pstates[STAGE_MAX + 1];
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const struct mdp5_cfg_hw *hw_cfg;
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int cnt = 0, i;
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DBG("%s: check", mdp5_crtc->name);
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@ -354,10 +396,10 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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/* verify that there are not too many planes attached to crtc
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* and that we don't have conflicting mixer stages:
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*/
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hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
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drm_atomic_crtc_state_for_each_plane(plane, state) {
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struct drm_plane_state *pstate;
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if (cnt >= ARRAY_SIZE(pstates)) {
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if (cnt >= (hw_cfg->lm.nb_stages)) {
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dev_err(dev->dev, "too many planes!\n");
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return -EINVAL;
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}
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@ -369,13 +411,13 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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*/
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if (!pstate)
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pstate = plane->state;
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pstates[cnt].plane = plane;
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pstates[cnt].state = to_mdp5_plane_state(pstate);
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cnt++;
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}
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/* assign a stage based on sorted zpos property */
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sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
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for (i = 0; i < cnt; i++) {
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@ -287,30 +287,86 @@ int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable)
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blend_cfg &= ~MDP5_CTL_LAYER_REG_CURSOR_OUT;
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ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, lm), blend_cfg);
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ctl->cursor_on = enable;
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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ctl->pending_ctl_trigger = mdp_ctl_flush_mask_cursor(cursor_id);
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ctl->cursor_on = enable;
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return 0;
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}
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg)
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static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
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enum mdp_mixer_stage_id stage)
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{
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switch (pipe) {
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case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
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case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
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case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
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case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
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case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
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case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
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case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
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case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
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case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
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case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
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default: return 0;
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}
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}
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static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
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enum mdp_mixer_stage_id stage)
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{
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if (stage < STAGE6)
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return 0;
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switch (pipe) {
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case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3;
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case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3;
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case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3;
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case SSPP_RGB0: return MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3;
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case SSPP_RGB1: return MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3;
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case SSPP_RGB2: return MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3;
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case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3;
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case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3;
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case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3;
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case SSPP_RGB3: return MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3;
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default: return 0;
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}
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}
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u8 *stage, u32 stage_cnt,
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u32 ctl_blend_op_flags)
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{
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unsigned long flags;
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u32 blend_cfg = 0, blend_ext_cfg = 0;
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int i, start_stage;
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if (ctl->cursor_on)
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blend_cfg |= MDP5_CTL_LAYER_REG_CURSOR_OUT;
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else
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blend_cfg &= ~MDP5_CTL_LAYER_REG_CURSOR_OUT;
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if (ctl_blend_op_flags & MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT) {
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start_stage = STAGE0;
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blend_cfg |= MDP5_CTL_LAYER_REG_BORDER_COLOR;
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} else {
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start_stage = STAGE_BASE;
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}
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for (i = start_stage; i < start_stage + stage_cnt; i++) {
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blend_cfg |= mdp_ctl_blend_mask(stage[i], i);
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blend_ext_cfg |= mdp_ctl_blend_ext_mask(stage[i], i);
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}
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spin_lock_irqsave(&ctl->hw_lock, flags);
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if (ctl->cursor_on)
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blend_cfg |= MDP5_CTL_LAYER_REG_CURSOR_OUT;
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ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, lm), blend_cfg);
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ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, lm), blend_ext_cfg);
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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ctl->pending_ctl_trigger = mdp_ctl_flush_mask_lm(lm);
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DBG("lm%d: blend config = 0x%08x. ext_cfg = 0x%08x", lm,
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blend_cfg, blend_ext_cfg);
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return 0;
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}
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@ -41,40 +41,20 @@ int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
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/*
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* blend_cfg (LM blender config):
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*
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* The function below allows the caller of mdp5_ctl_blend() to specify how pipes
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* are being blended according to their stage (z-order), through @blend_cfg arg.
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*/
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static inline u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
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enum mdp_mixer_stage_id stage)
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{
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switch (pipe) {
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case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
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case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
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case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
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case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
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case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
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case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
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case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
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case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
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case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
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case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
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default: return 0;
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}
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}
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/*
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* mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
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*
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* @blend_cfg: see LM blender config definition below
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* @stage: array to contain the pipe num for each stage
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* @stage_cnt: valid stage number in stage array
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* @ctl_blend_op_flags: blender operation mode flags
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*
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* Note:
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* CTL registers need to be flushed after calling this function
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* (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
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*/
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg);
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#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT BIT(0)
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u8 *stage, u32 stage_cnt,
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u32 ctl_blend_op_flags);
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/**
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* mdp_ctl_flush_mask...() - Register FLUSH masks
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@ -70,18 +70,12 @@ struct mdp5_kms {
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struct mdp5_plane_state {
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struct drm_plane_state base;
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/* "virtual" zpos.. we calculate actual mixer-stage at runtime
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* by sorting the attached planes by zpos and then assigning
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* mixer stage lowest to highest. Private planes get default
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* zpos of zero, and public planes a unique value that is
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* greater than zero. This way, things work out if a naive
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* userspace assigns planes to a crtc without setting zpos.
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*/
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int zpos;
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/* aligned with property */
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uint8_t premultiplied;
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uint8_t zpos;
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uint8_t alpha;
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/* the actual mixer stage, calculated in crtc->atomic_check()
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* NOTE: this should move to mdp5_crtc_state, when that exists
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*/
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/* assigned by crtc blender */
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enum mdp_mixer_stage_id stage;
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/* some additional transactional status to help us know in the
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@ -68,14 +68,103 @@ static void mdp5_plane_destroy(struct drm_plane *plane)
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static void mdp5_plane_install_properties(struct drm_plane *plane,
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struct drm_mode_object *obj)
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{
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// XXX
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struct drm_device *dev = plane->dev;
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struct msm_drm_private *dev_priv = dev->dev_private;
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struct drm_property *prop;
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#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
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prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
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if (!prop) { \
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prop = drm_property_##fnc(dev, 0, #name, \
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##__VA_ARGS__); \
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if (!prop) { \
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dev_warn(dev->dev, \
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"Create property %s failed\n", \
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#name); \
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return; \
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} \
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dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
|
||||
} \
|
||||
drm_object_attach_property(&plane->base, prop, init_val); \
|
||||
} while (0)
|
||||
|
||||
#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
|
||||
INSTALL_PROPERTY(name, NAME, init_val, \
|
||||
create_range, min, max)
|
||||
|
||||
#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
|
||||
INSTALL_PROPERTY(name, NAME, init_val, \
|
||||
create_enum, name##_prop_enum_list, \
|
||||
ARRAY_SIZE(name##_prop_enum_list))
|
||||
|
||||
INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
|
||||
|
||||
#undef INSTALL_RANGE_PROPERTY
|
||||
#undef INSTALL_ENUM_PROPERTY
|
||||
#undef INSTALL_PROPERTY
|
||||
}
|
||||
|
||||
int mdp5_plane_set_property(struct drm_plane *plane,
|
||||
static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
|
||||
struct drm_plane_state *state, struct drm_property *property,
|
||||
uint64_t val)
|
||||
{
|
||||
struct drm_device *dev = plane->dev;
|
||||
struct mdp5_plane_state *pstate;
|
||||
struct msm_drm_private *dev_priv = dev->dev_private;
|
||||
int ret = 0;
|
||||
|
||||
pstate = to_mdp5_plane_state(state);
|
||||
|
||||
#define SET_PROPERTY(name, NAME, type) do { \
|
||||
if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
|
||||
pstate->name = (type)val; \
|
||||
DBG("Set property %s %d", #name, (type)val); \
|
||||
goto done; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
SET_PROPERTY(zpos, ZPOS, uint8_t);
|
||||
|
||||
dev_err(dev->dev, "Invalid property\n");
|
||||
ret = -EINVAL;
|
||||
done:
|
||||
return ret;
|
||||
#undef SET_PROPERTY
|
||||
}
|
||||
|
||||
static int mdp5_plane_set_property(struct drm_plane *plane,
|
||||
struct drm_property *property, uint64_t val)
|
||||
{
|
||||
// XXX
|
||||
return -EINVAL;
|
||||
return mdp5_plane_atomic_set_property(plane, plane->state, property,
|
||||
val);
|
||||
}
|
||||
|
||||
static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
|
||||
const struct drm_plane_state *state,
|
||||
struct drm_property *property, uint64_t *val)
|
||||
{
|
||||
struct drm_device *dev = plane->dev;
|
||||
struct mdp5_plane_state *pstate;
|
||||
struct msm_drm_private *dev_priv = dev->dev_private;
|
||||
int ret = 0;
|
||||
|
||||
pstate = to_mdp5_plane_state(state);
|
||||
|
||||
#define GET_PROPERTY(name, NAME, type) do { \
|
||||
if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
|
||||
*val = pstate->name; \
|
||||
DBG("Get property %s %lld", #name, *val); \
|
||||
goto done; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
GET_PROPERTY(zpos, ZPOS, uint8_t);
|
||||
|
||||
dev_err(dev->dev, "Invalid property\n");
|
||||
ret = -EINVAL;
|
||||
done:
|
||||
return ret;
|
||||
#undef SET_PROPERTY
|
||||
}
|
||||
|
||||
static void mdp5_plane_reset(struct drm_plane *plane)
|
||||
|
|
@ -88,11 +177,15 @@ static void mdp5_plane_reset(struct drm_plane *plane)
|
|||
kfree(to_mdp5_plane_state(plane->state));
|
||||
mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
|
||||
|
||||
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
|
||||
mdp5_state->zpos = 0;
|
||||
} else {
|
||||
mdp5_state->zpos = 1 + drm_plane_index(plane);
|
||||
}
|
||||
/* assign default blend parameters */
|
||||
mdp5_state->alpha = 255;
|
||||
mdp5_state->premultiplied = 0;
|
||||
|
||||
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
|
||||
mdp5_state->zpos = STAGE_BASE;
|
||||
else
|
||||
mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
|
||||
|
||||
mdp5_state->base.plane = plane;
|
||||
|
||||
plane->state = &mdp5_state->base;
|
||||
|
|
@ -132,6 +225,8 @@ static const struct drm_plane_funcs mdp5_plane_funcs = {
|
|||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
.destroy = mdp5_plane_destroy,
|
||||
.set_property = mdp5_plane_set_property,
|
||||
.atomic_set_property = mdp5_plane_atomic_set_property,
|
||||
.atomic_get_property = mdp5_plane_atomic_get_property,
|
||||
.reset = mdp5_plane_reset,
|
||||
.atomic_duplicate_state = mdp5_plane_duplicate_state,
|
||||
.atomic_destroy_state = mdp5_plane_destroy_state,
|
||||
|
|
|
|||
|
|
@ -64,6 +64,13 @@ struct msm_file_private {
|
|||
int dummy;
|
||||
};
|
||||
|
||||
enum msm_mdp_plane_property {
|
||||
PLANE_PROP_ZPOS,
|
||||
PLANE_PROP_ALPHA,
|
||||
PLANE_PROP_PREMULTIPLIED,
|
||||
PLANE_PROP_MAX_NUM
|
||||
};
|
||||
|
||||
struct msm_drm_private {
|
||||
|
||||
struct msm_kms *kms;
|
||||
|
|
@ -128,6 +135,9 @@ struct msm_drm_private {
|
|||
unsigned int num_connectors;
|
||||
struct drm_connector *connectors[8];
|
||||
|
||||
/* Properties */
|
||||
struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
|
||||
|
||||
/* VRAM carveout, used when no IOMMU: */
|
||||
struct {
|
||||
unsigned long size;
|
||||
|
|
|
|||
Loading…
Reference in New Issue