mirror of https://gitee.com/openkylin/linux.git
i2c: i2c-sh_mobile register access code break out
Break out register access functions in the i2c-sh_mobile driver. This update should not change any driver logic. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
0fdf86754f
commit
12a55f2db7
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@ -132,12 +132,12 @@ struct sh_mobile_i2c_data {
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#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
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/* Register offsets */
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#define ICDR(pd) (pd->reg + 0x00)
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#define ICCR(pd) (pd->reg + 0x04)
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#define ICSR(pd) (pd->reg + 0x08)
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#define ICIC(pd) (pd->reg + 0x0c)
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#define ICCL(pd) (pd->reg + 0x10)
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#define ICCH(pd) (pd->reg + 0x14)
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#define ICDR 0x00
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#define ICCR 0x04
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#define ICSR 0x08
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#define ICIC 0x0c
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#define ICCL 0x10
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#define ICCH 0x14
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/* Register bits */
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#define ICCR_ICE 0x80
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@ -160,6 +160,22 @@ struct sh_mobile_i2c_data {
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#define ICIC_WAITE 0x02
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#define ICIC_DTEE 0x01
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static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
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{
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iowrite8(data, pd->reg + offs);
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}
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static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
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{
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return ioread8(pd->reg + offs);
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}
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static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
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unsigned char set, unsigned char clr)
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{
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iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
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}
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static void activate_ch(struct sh_mobile_i2c_data *pd)
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{
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unsigned long i2c_clk;
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@ -197,24 +213,24 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
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pd->icch = (u_int8_t)(num/denom);
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/* Enable channel and configure rx ack */
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iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
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iic_set_clr(pd, ICCR, ICCR_ICE, 0);
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/* Mask all interrupts */
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iowrite8(0, ICIC(pd));
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iic_wr(pd, ICIC, 0);
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/* Set the clock */
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iowrite8(pd->iccl, ICCL(pd));
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iowrite8(pd->icch, ICCH(pd));
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iic_wr(pd, ICCL, pd->iccl);
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iic_wr(pd, ICCH, pd->icch);
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}
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static void deactivate_ch(struct sh_mobile_i2c_data *pd)
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{
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/* Clear/disable interrupts */
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iowrite8(0, ICSR(pd));
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iowrite8(0, ICIC(pd));
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iic_wr(pd, ICSR, 0);
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iic_wr(pd, ICIC, 0);
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/* Disable channel */
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iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
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iic_set_clr(pd, ICCR, 0, ICCR_ICE);
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/* Disable clock and mark device as idle */
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clk_disable(pd->clk);
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@ -233,35 +249,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
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switch (op) {
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case OP_START: /* issue start and trigger DTE interrupt */
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iowrite8(0x94, ICCR(pd));
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iic_wr(pd, ICCR, 0x94);
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break;
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case OP_TX_FIRST: /* disable DTE interrupt and write data */
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iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
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iowrite8(data, ICDR(pd));
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iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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iic_wr(pd, ICDR, data);
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break;
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case OP_TX: /* write data */
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iowrite8(data, ICDR(pd));
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iic_wr(pd, ICDR, data);
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break;
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case OP_TX_STOP: /* write data and issue a stop afterwards */
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iowrite8(data, ICDR(pd));
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iowrite8(0x90, ICCR(pd));
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iic_wr(pd, ICDR, data);
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iic_wr(pd, ICCR, 0x90);
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break;
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case OP_TX_TO_RX: /* select read mode */
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iowrite8(0x81, ICCR(pd));
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iic_wr(pd, ICCR, 0x81);
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break;
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case OP_RX: /* just read data */
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ret = ioread8(ICDR(pd));
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ret = iic_rd(pd, ICDR);
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break;
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case OP_RX_STOP: /* enable DTE interrupt, issue stop */
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iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
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ICIC(pd));
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iowrite8(0xc0, ICCR(pd));
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iic_wr(pd, ICIC,
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ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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iic_wr(pd, ICCR, 0xc0);
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break;
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case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
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iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
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ICIC(pd));
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ret = ioread8(ICDR(pd));
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iowrite8(0xc0, ICCR(pd));
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iic_wr(pd, ICIC,
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ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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ret = iic_rd(pd, ICDR);
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iic_wr(pd, ICCR, 0xc0);
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break;
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}
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@ -367,7 +383,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
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unsigned char sr;
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int wakeup;
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sr = ioread8(ICSR(pd));
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sr = iic_rd(pd, ICSR);
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pd->sr |= sr; /* remember state */
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dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
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@ -376,7 +392,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
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if (sr & (ICSR_AL | ICSR_TACK)) {
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/* don't interrupt transaction - continue to issue stop */
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iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
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iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
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wakeup = 0;
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} else if (pd->msg->flags & I2C_M_RD)
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wakeup = sh_mobile_i2c_isr_rx(pd);
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@ -384,7 +400,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
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wakeup = sh_mobile_i2c_isr_tx(pd);
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if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
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iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
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iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
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if (wakeup) {
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pd->sr |= SW_DONE;
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@ -402,21 +418,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
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}
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/* Initialize channel registers */
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iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
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iic_set_clr(pd, ICCR, 0, ICCR_ICE);
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/* Enable channel and configure rx ack */
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iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
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iic_set_clr(pd, ICCR, ICCR_ICE, 0);
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/* Set the clock */
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iowrite8(pd->iccl, ICCL(pd));
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iowrite8(pd->icch, ICCH(pd));
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iic_wr(pd, ICCL, pd->iccl);
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iic_wr(pd, ICCH, pd->icch);
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pd->msg = usr_msg;
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pd->pos = -1;
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pd->sr = 0;
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/* Enable all interrupts to begin with */
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iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
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iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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return 0;
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}
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@ -451,7 +467,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
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retry_count = 1000;
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again:
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val = ioread8(ICSR(pd));
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val = iic_rd(pd, ICSR);
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dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
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