mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: move dcn1 dispclk programming to dccg
No functional change. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d578839ca0
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12c3130dd6
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@ -552,7 +552,85 @@ static void dce12_update_clocks(struct dccg *dccg,
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}
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}
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static void dcn_update_clocks(struct dccg *dccg,
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static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
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{
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bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
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bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz;
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int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
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bool cur_dpp_div = dccg->clks.dispclk_khz > dccg->clks.dppclk_khz;
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/* increase clock, looking for div is 0 for current, request div is 1*/
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if (dispclk_increase) {
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/* already divided by 2, no need to reach target clk with 2 steps*/
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if (cur_dpp_div)
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return new_clocks->dispclk_khz;
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/* request disp clk is lower than maximum supported dpp clk,
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* no need to reach target clk with two steps.
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*/
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if (new_clocks->dispclk_khz <= disp_clk_threshold)
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return new_clocks->dispclk_khz;
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/* target dpp clk not request divided by 2, still within threshold */
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if (!request_dpp_div)
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return new_clocks->dispclk_khz;
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} else {
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/* decrease clock, looking for current dppclk divided by 2,
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* request dppclk not divided by 2.
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*/
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/* current dpp clk not divided by 2, no need to ramp*/
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if (!cur_dpp_div)
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return new_clocks->dispclk_khz;
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/* current disp clk is lower than current maximum dpp clk,
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* no need to ramp
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*/
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if (dccg->clks.dispclk_khz <= disp_clk_threshold)
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return new_clocks->dispclk_khz;
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/* request dpp clk need to be divided by 2 */
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if (request_dpp_div)
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return new_clocks->dispclk_khz;
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}
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return disp_clk_threshold;
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}
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static void dcn1_ramp_up_dispclk_with_dpp(struct dccg *dccg, struct dc_clocks *new_clocks)
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{
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struct dc *dc = dccg->ctx->dc;
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int dispclk_to_dpp_threshold = dcn1_determine_dppclk_threshold(dccg, new_clocks);
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bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
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int i;
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/* set disp clk to dpp clk threshold */
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dccg->funcs->set_dispclk(dccg, dispclk_to_dpp_threshold);
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/* update request dpp clk division option */
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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if (!pipe_ctx->plane_state)
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continue;
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pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
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pipe_ctx->plane_res.dpp,
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request_dpp_div,
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true);
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}
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/* If target clk not same as dppclk threshold, set to target clock */
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if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz)
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dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
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dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
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dccg->clks.dppclk_khz = new_clocks->dppclk_khz;
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dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
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}
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static void dcn1_update_clocks(struct dccg *dccg,
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struct dc_clocks *new_clocks,
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bool safe_to_lower)
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{
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@ -572,6 +650,9 @@ static void dcn_update_clocks(struct dccg *dccg,
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send_request_to_increase = true;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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/* make sure dcf clk is before dpp clk to
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* make sure we have enough voltage to run dpp clk
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*/
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if (send_request_to_increase
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) {
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/*use dcfclk to request voltage*/
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@ -584,8 +665,8 @@ static void dcn_update_clocks(struct dccg *dccg,
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
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clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
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clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz;
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/* TODO: ramp up - dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
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dccg->clks.dispclk_khz = new_clocks->dispclk_khz;*/
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dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);
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dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
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dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
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send_request_to_lower = true;
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@ -666,10 +747,10 @@ static void dce_update_clocks(struct dccg *dccg,
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}
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}
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static const struct display_clock_funcs dcn_funcs = {
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static const struct display_clock_funcs dcn1_funcs = {
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.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround,
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.set_dispclk = dce112_set_clock,
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.update_clocks = dcn_update_clocks
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.update_clocks = dcn1_update_clocks
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};
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static const struct display_clock_funcs dce120_funcs = {
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@ -838,7 +919,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
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return &clk_dce->base;
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}
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struct dccg *dcn_dccg_create(struct dc_context *ctx)
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struct dccg *dcn1_dccg_create(struct dc_context *ctx)
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{
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struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
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@ -851,7 +932,7 @@ struct dccg *dcn_dccg_create(struct dc_context *ctx)
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dce_dccg_construct(
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clk_dce, ctx, NULL, NULL, NULL);
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clk_dce->base.funcs = &dcn_funcs;
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clk_dce->base.funcs = &dcn1_funcs;
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return &clk_dce->base;
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}
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@ -128,7 +128,7 @@ struct dccg *dce112_dccg_create(
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struct dccg *dce120_dccg_create(struct dc_context *ctx);
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struct dccg *dcn_dccg_create(struct dc_context *ctx);
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struct dccg *dcn1_dccg_create(struct dc_context *ctx);
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void dce_dccg_destroy(struct dccg **dccg);
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@ -2360,101 +2360,6 @@ static void dcn10_apply_ctx_for_surface(
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*/
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}
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static int determine_dppclk_threshold(struct dc *dc, struct dc_state *context)
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{
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bool request_dpp_div = context->bw.dcn.clk.dispclk_khz >
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context->bw.dcn.clk.dppclk_khz;
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bool dispclk_increase = context->bw.dcn.clk.dispclk_khz >
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dc->res_pool->dccg->clks.dispclk_khz;
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int disp_clk_threshold = context->bw.dcn.clk.max_supported_dppclk_khz;
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bool cur_dpp_div = dc->res_pool->dccg->clks.dispclk_khz >
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dc->res_pool->dccg->clks.dppclk_khz;
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/* increase clock, looking for div is 0 for current, request div is 1*/
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if (dispclk_increase) {
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/* already divided by 2, no need to reach target clk with 2 steps*/
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if (cur_dpp_div)
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return context->bw.dcn.clk.dispclk_khz;
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/* request disp clk is lower than maximum supported dpp clk,
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* no need to reach target clk with two steps.
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*/
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if (context->bw.dcn.clk.dispclk_khz <= disp_clk_threshold)
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return context->bw.dcn.clk.dispclk_khz;
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/* target dpp clk not request divided by 2, still within threshold */
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if (!request_dpp_div)
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return context->bw.dcn.clk.dispclk_khz;
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} else {
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/* decrease clock, looking for current dppclk divided by 2,
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* request dppclk not divided by 2.
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*/
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/* current dpp clk not divided by 2, no need to ramp*/
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if (!cur_dpp_div)
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return context->bw.dcn.clk.dispclk_khz;
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/* current disp clk is lower than current maximum dpp clk,
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* no need to ramp
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*/
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if (dc->res_pool->dccg->clks.dispclk_khz <= disp_clk_threshold)
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return context->bw.dcn.clk.dispclk_khz;
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/* request dpp clk need to be divided by 2 */
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if (request_dpp_div)
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return context->bw.dcn.clk.dispclk_khz;
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}
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return disp_clk_threshold;
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}
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static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
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{
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int i;
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bool request_dpp_div = context->bw.dcn.clk.dispclk_khz >
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context->bw.dcn.clk.dppclk_khz;
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int dispclk_to_dpp_threshold = determine_dppclk_threshold(dc, context);
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/* set disp clk to dpp clk threshold */
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dc->res_pool->dccg->funcs->set_dispclk(
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dc->res_pool->dccg,
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dispclk_to_dpp_threshold);
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/* update request dpp clk division option */
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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if (!pipe_ctx->plane_state)
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continue;
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pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
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pipe_ctx->plane_res.dpp,
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request_dpp_div,
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true);
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}
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/* If target clk not same as dppclk threshold, set to target clock */
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if (dispclk_to_dpp_threshold != context->bw.dcn.clk.dispclk_khz) {
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dc->res_pool->dccg->funcs->set_dispclk(
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dc->res_pool->dccg,
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context->bw.dcn.clk.dispclk_khz);
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}
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dc->res_pool->dccg->clks.dispclk_khz =
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context->bw.dcn.clk.dispclk_khz;
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dc->res_pool->dccg->clks.dppclk_khz =
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context->bw.dcn.clk.dppclk_khz;
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dc->res_pool->dccg->clks.max_supported_dppclk_khz =
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context->bw.dcn.clk.max_supported_dppclk_khz;
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}
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static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
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{
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return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
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}
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static void dcn10_set_bandwidth(
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struct dc *dc,
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struct dc_state *context,
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&context->bw.dcn.clk,
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decrease_allowed);
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/* make sure dcf clk is before dpp clk to
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* make sure we have enough voltage to run dpp clk
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*/
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if (should_set_clock(
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decrease_allowed,
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context->bw.dcn.clk.dispclk_khz,
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dc->res_pool->dccg->clks.dispclk_khz)) {
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ramp_up_dispclk_with_dpp(dc, context);
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}
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dcn10_pplib_apply_display_requirements(dc, context);
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if (dc->debug.sanity_checks) {
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@ -1072,7 +1072,7 @@ static bool construct(
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}
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}
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pool->base.dccg = dcn_dccg_create(ctx);
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pool->base.dccg = dcn1_dccg_create(ctx);
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if (pool->base.dccg == NULL) {
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dm_error("DC: failed to create display clock!\n");
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BREAK_TO_DEBUGGER();
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