mirror of https://gitee.com/openkylin/linux.git
arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie
Add required device node for QMP phy based 3-lane PCIe phy present on msm8996 chipset to enable support for the same. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -89,6 +89,10 @@ sdhci@74a4900 {
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status = "okay";
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};
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phy@34000 {
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status = "okay";
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};
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phy@7410000 {
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status = "okay";
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};
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@ -556,6 +556,68 @@ qusb2s_hstx_trim: hstx_trim@24f {
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};
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};
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phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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vdda-phy-supply = <&pm8994_l28>;
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vdda-pll-supply = <&pm8994_l12>;
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIE_PHY_COM_BCR>,
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<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
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reset-names = "phy", "common", "cfg";
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status = "disabled";
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pciephy_0: lane@35000 {
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reg = <0x035000 0x130>,
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<0x035200 0x200>,
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<0x035400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk_src";
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "lane0";
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};
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pciephy_1: lane@36000 {
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reg = <0x036000 0x130>,
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<0x036200 0x200>,
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<0x036400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk_src";
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "pipe1";
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "lane1";
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};
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pciephy_2: lane@37000 {
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reg = <0x037000 0x130>,
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<0x037200 0x200>,
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<0x037400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_2_pipe_clk_src";
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clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
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clock-names = "pipe2";
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resets = <&gcc GCC_PCIE_2_PHY_BCR>;
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reset-names = "lane2";
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};
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};
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phy@7410000 {
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compatible = "qcom,msm8996-qmp-usb3-phy";
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reg = <0x7410000 0x1c4>;
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