AT91: reset routine cleanup, remove not needed icache flush

Generalize assembler reset routine to allow use on several at91sam9 chips.
This patch replace double definitions of SDRAM controller registers and RSTC
registers with use of classical header files.

For this rework, we remove the not needed icache flush as it is already
done in the calling function: arm_machine_restart().

Rename at91sam9g20_reset.S to generalize to several chips.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

arch/arm/mach-at91/Makefile

@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261.o at91sam926x_time.o at91sam9261_d
 obj-$(CONFIG_ARCH_AT91SAM9G10)	+= at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)	+= at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o

arch/arm/mach-at91/at91sam9260.c

@@ -25,7 +25,7 @@
 #include "generic.h"
 #include "clock.h"
 
-extern void at91sam9g20_reset(void);
+extern void at91sam9_alt_reset(void);
 
 static struct map_desc at91sam9260_io_desc[] __initdata = {
 	{
@@ -330,7 +330,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
 		iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
 	if (cpu_is_at91sam9g20())
-		at91_arch_reset = at91sam9g20_reset;
+		at91_arch_reset = at91sam9_alt_reset;
 	else
 		at91_arch_reset = at91sam9260_reset;
 

arch/arm/mach-at91/at91sam9_alt_reset.S

@@ -0,0 +1,48 @@
+/*
+ * reset AT91SAM9G20 as per errata
+ *
+ * (C) BitBox Ltd 2010
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <mach/hardware.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_rstc.h>
+
+			.arm
+
+			.globl	at91sam9_alt_reset
+
+at91sam9_alt_reset:	mrc	p15, 0, r0, c1, c0, 0
+			orr	r0, r0, #CR_I
+			mcr	p15, 0, r0, c1, c0, 0		@ enable I-cache
+
+			ldr	r0, .at91_va_base_sdramc	@ preload constants
+			ldr	r1, .at91_va_base_rstc_cr
+
+			mov	r2, #1
+			mov	r3, #AT91_SDRAMC_LPCB_POWER_DOWN
+			ldr	r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
+
+			.balign	32				@ align to cache line
+
+			str	r2, [r0, #AT91_SDRAMC_TR]	@ disable SDRAM access
+			str	r3, [r0, #AT91_SDRAMC_LPR]	@ power down SDRAM
+			str	r4, [r1]			@ reset processor
+
+			b	.
+
+.at91_va_base_sdramc:
+	.word AT91_VA_BASE_SYS + AT91_SDRAMC0
+.at91_va_base_rstc_cr:
+	.word AT91_VA_BASE_SYS + AT91_RSTC_CR

arch/arm/mach-at91/at91sam9g20_reset.S

@@ -1,55 +0,0 @@
-/*
- * reset AT91SAM9G20 as per errata
- *
- * (C) BitBox Ltd 2010
- *
- * unless the SDRAM is cleanly shutdown before we hit the
- * reset register it can be left driving the data bus and
- * killing the chance of a subsequent boot from NAND
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#define CP15_CR_I			(1 << 12)
-
-#define SYS_VIRT_OFS			(-0x01000000)
-
-#define SDRAMC_BASE			(SYS_VIRT_OFS + 0xffffea00)
-#define  SDRAMC_TR			0x0004
-#define  SDRAMC_LPR			0x0010
-#define   SDRAMC_LPCB_POWER_DOWN	2
-
-#define RSTC_BASE			(SYS_VIRT_OFS + 0xfffffd00)
-#define  RSTC_CR			0x0000
-#define   RSTC_PROCRST			(1 << 0)
-#define   RSTC_PERRST			(1 << 2)
-#define   RSTC_KEY			(0xa5 << 24)
-
-			.arm
-
-			.globl	at91sam9g20_reset
-
-at91sam9g20_reset:	mov	r0, #0
-			mcr	p15, 0, r0, c7, c5, 0		@ flush I-cache
-
-			mrc	p15, 0, r0, c1, c0, 0
-			orr	r0, r0, #CP15_CR_I
-			mcr	p15, 0, r0, c1, c0, 0		@ enable I-cache
-
-			ldr	r0, =SDRAMC_BASE		@ preload constants
-			ldr	r1, =RSTC_BASE
-
-			mov	r2, #1
-			mov	r3, #SDRAMC_LPCB_POWER_DOWN
-			ldr	r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
-
-			.balign	32				@ align to cache line
-
-			str	r2, [r0, #SDRAMC_TR]		@ disable SDRAM access
-			str	r3, [r0, #SDRAMC_LPR]		@ power down SDRAM
-			str	r4, [r1, #RSTC_CR]		@ reset processor
-
-			b	.