openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

i.MX31: Add support for the CPLD on PDK Debug board. 

The i.MX31 PDK consists of several boards, one of them is a debug
board containing a CPLD which controls some debug leds, switch
buttons, an interrupt chip and an Ethernet controller.
This patch adds support for detecting if the PDK board is present
(during boot) and adds the interrupt chip to the kernel.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Magnus Lilja 2009-05-17 20:18:08 +02:00 committed by Sascha Hauer
parent 2eec8c318b
commit 135cad366b
3 changed files with 199 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

150
arch/arm/mach-mx3/mx31pdk.c
View File

@ -20,6 +20,7 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -46,13 +47,156 @@ static int mx31pdk_pins[] = {
MX31_PIN_CTS1__CTS1,
MX31_PIN_RTS1__RTS1,
MX31_PIN_TXD1__TXD1,
MX31_PIN_RXD1__RXD1
MX31_PIN_RXD1__RXD1,
IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
};
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
/*
* Routines for the CPLD on the debug board. It contains a CPLD handling
* LEDs, switches, interrupts for Ethernet.
*/
static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
{
uint32_t imr_val;
uint32_t int_valid;
uint32_t expio_irq;
imr_val = __raw_readw(CPLD_INT_MASK_REG);
int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
expio_irq = MXC_EXP_IO_BASE;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
if ((int_valid & 1) == 0)
continue;
generic_handle_irq(expio_irq);
}
}
/*
* Disable an expio pin's interrupt by setting the bit in the imr.
* @param irq an expio virtual irq number
*/
static void expio_mask_irq(uint32_t irq)
{
uint16_t reg;
uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
/* mask the interrupt */
reg = __raw_readw(CPLD_INT_MASK_REG);
reg |= 1 << expio;
__raw_writew(reg, CPLD_INT_MASK_REG);
}
/*
* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
* @param irq an expanded io virtual irq number
*/
static void expio_ack_irq(uint32_t irq)
{
uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
/* clear the interrupt status */
__raw_writew(1 << expio, CPLD_INT_RESET_REG);
__raw_writew(0, CPLD_INT_RESET_REG);
/* mask the interrupt */
expio_mask_irq(irq);
}
/*
* Enable a expio pin's interrupt by clearing the bit in the imr.
* @param irq a expio virtual irq number
*/
static void expio_unmask_irq(uint32_t irq)
{
uint16_t reg;
uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
/* unmask the interrupt */
reg = __raw_readw(CPLD_INT_MASK_REG);
reg &= ~(1 << expio);
__raw_writew(reg, CPLD_INT_MASK_REG);
}
static struct irq_chip expio_irq_chip = {
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
};
static int __init mx31pdk_init_expio(void)
{
int i;
int ret;
/* Check if there's a debug board connected */
if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
(__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
(__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
/* No Debug board found */
return -ENODEV;
}
pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n",
__raw_readw(CPLD_CODE_VER_REG));
/*
* Configure INT line as GPIO input
*/
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
if (ret)
pr_warning("could not get LAN irq gpio\n");
else
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
/* Disable the interrupts and clear the status */
__raw_writew(0, CPLD_INT_MASK_REG);
__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
__raw_writew(0, CPLD_INT_RESET_REG);
__raw_writew(0x1F, CPLD_INT_MASK_REG);
for (i = MXC_EXP_IO_BASE;
i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
i++) {
set_irq_chip(i, &expio_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler);
return 0;
}
/*
* This structure defines the MX31 memory map.
*/
static struct map_desc mx31pdk_io_desc[] __initdata = {
{
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE_NONSHARED,
}, {
.virtual = CS5_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS5_BASE_ADDR),
.length = CS5_SIZE,
.type = MT_DEVICE,
},
};
/*
* Set up static virtual mappings.
*/
static void __init mx31pdk_map_io(void)
{
mx31_map_io();
iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
}
/*!
* Board specific initialization.
*/
@ -62,6 +206,8 @@ static void __init mxc_board_init(void)
"mx31pdk");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mx31pdk_init_expio();
}
static void __init mx31pdk_timer_init(void)
@ -82,7 +228,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io,
.map_io = mx31pdk_map_io,
.init_irq = mxc_init_irq,
.init_machine = mxc_board_init,
.timer = &mx31pdk_timer,

45
arch/arm/plat-mxc/include/mach/board-mx31pdk.h
View File

@ -16,4 +16,49 @@
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
/* Definitions for components on the Debug board */
/* Base address of CPLD controller on the Debug board */
#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR)
/* LAN9217 ethernet base address */
#define LAN9217_BASE_ADDR CS5_BASE_ADDR
/* CPLD config and interrupt base address */
#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
/* LED switchs */
#define CPLD_LED_REG (CPLD_ADDR + 0x00)
/* buttons */
#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
/* status, interrupt */
#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
/* CPLD code version */
#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
/* module reset register */
#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60)
/* CPU ID and Personality ID */
#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68)
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1)
#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2)
#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3)
#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4)
#define MXC_MAX_EXP_IO_LINES 16
#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */

6
arch/arm/plat-mxc/include/mach/mx3x.h
View File

@ -48,6 +48,9 @@
#define CS4_SIZE SZ_32M
#define CS5_BASE_ADDR 0xB6000000
#define CS5_BASE_ADDR_VIRT 0xF6000000
#define CS5_SIZE SZ_32M
#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*
@ -191,6 +194,9 @@
#define CS4_IO_ADDRESS(x) \
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
#define CS5_IO_ADDRESS(x) \
(((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
#define X_MEMC_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)