arm64: dts: ls1028a: Update the clock providers for the Mali DP500

In order to maximise performance of the LCD Controller's 64-bit AXI
bus, for any give speed bin of the device, the AXI master interface
clock(ACLK) clock can be up to CPU_frequency/2, which is already
capable of optimal performance. In general, ACLK is always expected
to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
Main processing clock(PCLK) both are tied to the same clock as ACLK.

This change followed the LS1028A Architecture Specification Manual.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Wen He 2019-09-20 16:34:18 +08:00 committed by Shawn Guo
parent 62b4359c30
commit 1378259773
1 changed files with 2 additions and 15 deletions

View File

@ -86,20 +86,6 @@ dpclk: clock-controller@f1f0000 {
clocks = <&osc_27m>;
};
aclk: clock-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "aclk";
};
pclk: clock-apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <650000000>;
clock-output-names= "pclk";
};
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
@ -679,7 +665,8 @@ malidp0: display@f080000 {
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
<&clockgen 2 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;