mirror of https://gitee.com/openkylin/linux.git
arm64: dts: ls1028a: Update the clock providers for the Mali DP500
In order to maximise performance of the LCD Controller's 64-bit AXI bus, for any give speed bin of the device, the AXI master interface clock(ACLK) clock can be up to CPU_frequency/2, which is already capable of optimal performance. In general, ACLK is always expected to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and Main processing clock(PCLK) both are tied to the same clock as ACLK. This change followed the LS1028A Architecture Specification Manual. Signed-off-by: Wen He <wen.he_1@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -86,20 +86,6 @@ dpclk: clock-controller@f1f0000 {
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clocks = <&osc_27m>;
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};
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aclk: clock-axi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <650000000>;
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clock-output-names= "aclk";
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};
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pclk: clock-apb {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <650000000>;
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clock-output-names= "pclk";
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};
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reboot {
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compatible ="syscon-reboot";
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regmap = <&dcfg>;
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@ -679,7 +665,8 @@ malidp0: display@f080000 {
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interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
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<0 223 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "DE", "SE";
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clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
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clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
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<&clockgen 2 2>;
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clock-names = "pxlclk", "mclk", "aclk", "pclk";
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arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
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arm,malidp-arqos-value = <0xd000d000>;
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