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ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4
Add nodes for GPU (Mali 400) to Exynos4210 and Exynos4412. Describe the GPU as much as possible however still few elements are missing: 1. Exynos4210 bus clock is not described in hardware manual therefore the IP gate clock was provided, 2. Exynos4412: Not sure what to do with CLK_G3D clock responsible for gating entire IP block (it is now being disabled as unused), 3. Regulator supplies on Trats board. Limited testing on Odroid U3 (Exynos4412). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -51,6 +51,42 @@ aliases {
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serial3 = &serial_3;
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};
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gpu: gpu@13000000 {
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compatible = "samsung,exynos4210-mali", "arm,mali-400";
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reg = <0x13000000 0x10000>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3",
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"pmu";
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/*
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* CLK_G3D is not actually bus clock but a IP-level clock.
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* The bus clock is not described in hardware manual.
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*/
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clocks = <&clock CLK_G3D>,
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<&clock CLK_SCLK_G3D>;
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clock-names = "bus", "core";
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power-domains = <&pd_g3d>;
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status = "disabled";
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};
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pmu: pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&combiner>;
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@ -132,6 +132,11 @@ &fimd {
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status = "okay";
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};
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&gpu {
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mali-supply = <&buck3_reg>;
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status = "okay";
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};
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&hsotg {
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vusb_d-supply = <&ldo3_reg>;
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vusb_a-supply = <&ldo8_reg>;
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@ -239,6 +239,10 @@ &fimd {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&hsotg {
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vusb_d-supply = <&vusb_reg>;
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vusb_a-supply = <&vusbdac_reg>;
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@ -262,6 +262,11 @@ fimd_dpi_ep: endpoint {
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};
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};
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&gpu {
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mali-supply = <&buck2_reg>;
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status = "okay";
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};
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&hdmi {
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hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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@ -449,6 +449,23 @@ &fimc_3 {
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samsung,lcd-wb;
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};
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&gpu {
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operating-points-v2 = <&gpu_opp_table>;
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gpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <950000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <1050000>;
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};
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};
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};
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&mdma1 {
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power-domains = <&pd_lcd0>;
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};
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@ -115,6 +115,11 @@ &cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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&gpu {
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mali-supply = <&buck4_reg>;
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status = "okay";
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};
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&hsotg {
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vusb_d-supply = <&ldo15_reg>;
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vusb_a-supply = <&ldo12_reg>;
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@ -453,6 +453,11 @@ &fimd {
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status = "okay";
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};
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&gpu {
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mali-supply = <&buck4_reg>;
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status = "okay";
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};
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&hdmi {
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hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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@ -229,6 +229,11 @@ &fimc_3 {
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assigned-clock-rates = <0>, <176000000>;
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};
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&gpu {
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mali-supply = <&buck4_reg>;
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status = "okay";
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};
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&hdmi {
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hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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@ -38,3 +38,10 @@ &cooling_map1 {
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cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
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<&cpu2 15 15>, <&cpu3 15 15>;
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};
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&gpu_opp_table {
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opp-533000000 {
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opp-hz = /bits/ 64 <533000000>;
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opp-microvolt = <1075000>;
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};
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};
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@ -716,6 +716,31 @@ &gic {
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cpu-offset = <0x4000>;
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};
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&gpu {
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operating-points-v2 = <&gpu_opp_table>;
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gpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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opp-microvolt = <875000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <900000>;
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};
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opp-350000000 {
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opp-hz = /bits/ 64 <350000000>;
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opp-microvolt = <950000>;
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};
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opp-440000000 {
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opp-hz = /bits/ 64 <440000000>;
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opp-microvolt = <1025000>;
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};
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};
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};
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&hdmi {
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compatible = "samsung,exynos4212-hdmi";
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};
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