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drm/i915/gvt: Introduce intel_vgpu_submission 

Introduce intel_vgpu_submission to hold all members related to submission
in struct intel_vgpu before.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
This commit is contained in:
Zhi Wang 2017-09-10 21:15:18 +08:00 committed by Zhenyu Wang
parent 9a9829e9eb
commit 1406a14b0e
8 changed files with 75 additions and 56 deletions
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30
drivers/gpu/drm/i915/gvt/execlist.c
View File

@ -362,7 +362,7 @@ static void free_workload(struct intel_vgpu_workload *workload)
{ {
intel_vgpu_unpin_mm(workload->shadow_mm); intel_vgpu_unpin_mm(workload->shadow_mm);
intel_gvt_mm_unreference(workload->shadow_mm); intel_gvt_mm_unreference(workload->shadow_mm);
kmem_cache_free(workload->vgpu->workloads, workload); kmem_cache_free(workload->vgpu->submission.workloads, workload);
} }
#define get_desc_from_elsp_dwords(ed, i) \ #define get_desc_from_elsp_dwords(ed, i) \
@ -401,7 +401,8 @@ static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
struct intel_vgpu_workload, struct intel_vgpu_workload,
wa_ctx); wa_ctx);
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct intel_vgpu_submission *s = &workload->vgpu->submission;
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
struct drm_i915_gem_object *ctx_obj = struct drm_i915_gem_object *ctx_obj =
shadow_ctx->engine[ring_id].state->obj; shadow_ctx->engine[ring_id].state->obj;
struct execlist_ring_context *shadow_ring_context; struct execlist_ring_context *shadow_ring_context;
@ -474,6 +475,7 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
static int prepare_execlist_workload(struct intel_vgpu_workload *workload) static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
{ {
struct intel_vgpu *vgpu = workload->vgpu; struct intel_vgpu *vgpu = workload->vgpu;
struct intel_vgpu_submission *s = &vgpu->submission;
struct execlist_ctx_descriptor_format ctx[2]; struct execlist_ctx_descriptor_format ctx[2];
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
int ret; int ret;
@ -514,7 +516,7 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0); ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1); ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
ret = emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx); ret = emulate_execlist_schedule_in(&s->execlist[ring_id], ctx);
if (!ret) if (!ret)
goto out; goto out;
else else
@ -533,7 +535,8 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
{ {
struct intel_vgpu *vgpu = workload->vgpu; struct intel_vgpu *vgpu = workload->vgpu;
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id]; struct intel_vgpu_submission *s = &vgpu->submission;
struct intel_vgpu_execlist *execlist = &s->execlist[ring_id];
struct intel_vgpu_workload *next_workload; struct intel_vgpu_workload *next_workload;
struct list_head *next = workload_q_head(vgpu, ring_id)->next; struct list_head *next = workload_q_head(vgpu, ring_id)->next;
bool lite_restore = false; bool lite_restore = false;
@ -652,6 +655,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
struct execlist_ctx_descriptor_format *desc, struct execlist_ctx_descriptor_format *desc,
bool emulate_schedule_in) bool emulate_schedule_in)
{ {
struct intel_vgpu_submission *s = &vgpu->submission;
struct list_head *q = workload_q_head(vgpu, ring_id); struct list_head *q = workload_q_head(vgpu, ring_id);
struct intel_vgpu_workload *last_workload = get_last_workload(q); struct intel_vgpu_workload *last_workload = get_last_workload(q);
struct intel_vgpu_workload *workload = NULL; struct intel_vgpu_workload *workload = NULL;
@ -689,7 +693,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
gvt_dbg_el("ring id %d begin a new workload\n", ring_id); gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
workload = kmem_cache_zalloc(vgpu->workloads, GFP_KERNEL); workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
if (!workload) if (!workload)
return -ENOMEM; return -ENOMEM;
@ -738,7 +742,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
} }
if (emulate_schedule_in) if (emulate_schedule_in)
workload->elsp_dwords = vgpu->execlist[ring_id].elsp_dwords; workload->elsp_dwords = s->execlist[ring_id].elsp_dwords;
gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
workload, ring_id, head, tail, start, ctl); workload, ring_id, head, tail, start, ctl);
@ -748,7 +752,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
ret = prepare_mm(workload); ret = prepare_mm(workload);
if (ret) { if (ret) {
kmem_cache_free(vgpu->workloads, workload); kmem_cache_free(s->workloads, workload);
return ret; return ret;
} }
@ -769,7 +773,8 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id) int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id)
{ {
struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id]; struct intel_vgpu_submission *s = &vgpu->submission;
struct intel_vgpu_execlist *execlist = &s->execlist[ring_id];
struct execlist_ctx_descriptor_format *desc[2]; struct execlist_ctx_descriptor_format *desc[2];
int i, ret; int i, ret;
@ -811,7 +816,8 @@ int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id)
static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id)
{ {
struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id]; struct intel_vgpu_submission *s = &vgpu->submission;
struct intel_vgpu_execlist *execlist = &s->execlist[ring_id];
struct execlist_context_status_pointer_format ctx_status_ptr; struct execlist_context_status_pointer_format ctx_status_ptr;
u32 ctx_status_ptr_reg; u32 ctx_status_ptr_reg;
@ -833,6 +839,7 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id)
static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)
{ {
struct intel_vgpu_submission *s = &vgpu->submission;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine; struct intel_engine_cs *engine;
struct intel_vgpu_workload *pos, *n; struct intel_vgpu_workload *pos, *n;
@ -841,12 +848,11 @@ static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)
/* free the unsubmited workloads in the queues. */ /* free the unsubmited workloads in the queues. */
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
list_for_each_entry_safe(pos, n, list_for_each_entry_safe(pos, n,
&vgpu->workload_q_head[engine->id], list) { &s->workload_q_head[engine->id], list) {
list_del_init(&pos->list); list_del_init(&pos->list);
free_workload(pos); free_workload(pos);
} }
clear_bit(engine->id, s->shadow_ctx_desc_updated);
clear_bit(engine->id, vgpu->shadow_ctx_desc_updated);
} }
} }

17
drivers/gpu/drm/i915/gvt/gvt.h
View File

@ -142,6 +142,15 @@ struct vgpu_sched_ctl {
int weight; int weight;
}; };
struct intel_vgpu_submission {
struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
struct list_head workload_q_head[I915_NUM_ENGINES];
struct kmem_cache *workloads;
atomic_t running_workload_num;
struct i915_gem_context *shadow_ctx;
DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
};
struct intel_vgpu { struct intel_vgpu {
struct intel_gvt *gvt; struct intel_gvt *gvt;
int id; int id;
@ -161,16 +170,12 @@ struct intel_vgpu {
struct intel_vgpu_gtt gtt; struct intel_vgpu_gtt gtt;
struct intel_vgpu_opregion opregion; struct intel_vgpu_opregion opregion;
struct intel_vgpu_display display; struct intel_vgpu_display display;
struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; struct intel_vgpu_submission submission;
struct list_head workload_q_head[I915_NUM_ENGINES];
struct kmem_cache *workloads;
atomic_t running_workload_num;
/* 1/2K for each reserve ring buffer */ /* 1/2K for each reserve ring buffer */
void *reserve_ring_buffer_va[I915_NUM_ENGINES]; void *reserve_ring_buffer_va[I915_NUM_ENGINES];
int reserve_ring_buffer_size[I915_NUM_ENGINES]; int reserve_ring_buffer_size[I915_NUM_ENGINES];
DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
struct i915_gem_context *shadow_ctx;
DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
struct { struct {

2
drivers/gpu/drm/i915/gvt/handlers.c
View File

@ -1451,7 +1451,7 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
return -EINVAL; return -EINVAL;
execlist = &vgpu->execlist[ring_id]; execlist = &vgpu->submission.execlist[ring_id];
execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
if (execlist->elsp_dwords.index == 3) { if (execlist->elsp_dwords.index == 3) {

2
drivers/gpu/drm/i915/gvt/kvmgt.c
View File

@ -1188,7 +1188,7 @@ hw_id_show(struct device *dev, struct device_attribute *attr,
struct intel_vgpu *vgpu = (struct intel_vgpu *) struct intel_vgpu *vgpu = (struct intel_vgpu *)
mdev_get_drvdata(mdev); mdev_get_drvdata(mdev);
return sprintf(buf, "%u\n", return sprintf(buf, "%u\n",
vgpu->shadow_ctx->hw_id); vgpu->submission.shadow_ctx->hw_id);
} }
return sprintf(buf, "\n"); return sprintf(buf, "\n");
} }

9
drivers/gpu/drm/i915/gvt/render.c
View File

@ -261,14 +261,15 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
{ {
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct render_mmio *mmio; struct intel_vgpu_submission *s = &vgpu->submission;
u32 v; u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
int i, array_size;
u32 *reg_state = vgpu->shadow_ctx->engine[ring_id].lrc_reg_state;
u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
u32 inhibit_mask = u32 inhibit_mask =
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
i915_reg_t last_reg = _MMIO(0); i915_reg_t last_reg = _MMIO(0);
struct render_mmio *mmio;
u32 v;
int i, array_size;
if (IS_SKYLAKE(vgpu->gvt->dev_priv) if (IS_SKYLAKE(vgpu->gvt->dev_priv)
|| IS_KABYLAKE(vgpu->gvt->dev_priv)) { || IS_KABYLAKE(vgpu->gvt->dev_priv)) {

65
drivers/gpu/drm/i915/gvt/scheduler.c
View File

@ -57,7 +57,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
struct intel_vgpu *vgpu = workload->vgpu; struct intel_vgpu *vgpu = workload->vgpu;
struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt *gvt = vgpu->gvt;
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct i915_gem_context *shadow_ctx = vgpu->submission.shadow_ctx;
struct drm_i915_gem_object *ctx_obj = struct drm_i915_gem_object *ctx_obj =
shadow_ctx->engine[ring_id].state->obj; shadow_ctx->engine[ring_id].state->obj;
struct execlist_ring_context *shadow_ring_context; struct execlist_ring_context *shadow_ring_context;
@ -249,12 +249,13 @@ void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
*/ */
int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
{ {
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_vgpu_submission *s = &vgpu->submission;
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
struct intel_engine_cs *engine = dev_priv->engine[ring_id]; struct intel_engine_cs *engine = dev_priv->engine[ring_id];
struct drm_i915_gem_request *rq; struct drm_i915_gem_request *rq;
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_ring *ring; struct intel_ring *ring;
int ret; int ret;
@ -267,7 +268,7 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
GEN8_CTX_ADDRESSING_MODE_SHIFT; GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (!test_and_set_bit(ring_id, vgpu->shadow_ctx_desc_updated)) if (!test_and_set_bit(ring_id, s->shadow_ctx_desc_updated))
shadow_context_descriptor_update(shadow_ctx, shadow_context_descriptor_update(shadow_ctx,
dev_priv->engine[ring_id]); dev_priv->engine[ring_id]);
@ -326,9 +327,11 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
static int dispatch_workload(struct intel_vgpu_workload *workload) static int dispatch_workload(struct intel_vgpu_workload *workload)
{ {
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_vgpu_submission *s = &vgpu->submission;
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
struct intel_engine_cs *engine = dev_priv->engine[ring_id]; struct intel_engine_cs *engine = dev_priv->engine[ring_id];
int ret = 0; int ret = 0;
@ -414,7 +417,7 @@ static struct intel_vgpu_workload *pick_next_workload(
gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
atomic_inc(&workload->vgpu->running_workload_num); atomic_inc(&workload->vgpu->submission.running_workload_num);
out: out:
mutex_unlock(&gvt->lock); mutex_unlock(&gvt->lock);
return workload; return workload;
@ -424,8 +427,9 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
{ {
struct intel_vgpu *vgpu = workload->vgpu; struct intel_vgpu *vgpu = workload->vgpu;
struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt *gvt = vgpu->gvt;
struct intel_vgpu_submission *s = &vgpu->submission;
struct i915_gem_context *shadow_ctx = s->shadow_ctx;
int ring_id = workload->ring_id; int ring_id = workload->ring_id;
struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
struct drm_i915_gem_object *ctx_obj = struct drm_i915_gem_object *ctx_obj =
shadow_ctx->engine[ring_id].state->obj; shadow_ctx->engine[ring_id].state->obj;
struct execlist_ring_context *shadow_ring_context; struct execlist_ring_context *shadow_ring_context;
@ -491,15 +495,14 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
static void complete_current_workload(struct intel_gvt *gvt, int ring_id) static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
{ {
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
struct intel_vgpu_workload *workload; struct intel_vgpu_workload *workload =
struct intel_vgpu *vgpu; scheduler->current_workload[ring_id];
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_vgpu_submission *s = &vgpu->submission;
int event; int event;
mutex_lock(&gvt->lock); mutex_lock(&gvt->lock);
workload = scheduler->current_workload[ring_id];
vgpu = workload->vgpu;
/* For the workload w/ request, needs to wait for the context /* For the workload w/ request, needs to wait for the context
* switch to make sure request is completed. * switch to make sure request is completed.
* For the workload w/o request, directly complete the workload. * For the workload w/o request, directly complete the workload.
@ -536,7 +539,7 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
} }
mutex_lock(&dev_priv->drm.struct_mutex); mutex_lock(&dev_priv->drm.struct_mutex);
/* unpin shadow ctx as the shadow_ctx update is done */ /* unpin shadow ctx as the shadow_ctx update is done */
engine->context_unpin(engine, workload->vgpu->shadow_ctx); engine->context_unpin(engine, s->shadow_ctx);
mutex_unlock(&dev_priv->drm.struct_mutex); mutex_unlock(&dev_priv->drm.struct_mutex);
} }
@ -548,7 +551,7 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
list_del_init(&workload->list); list_del_init(&workload->list);
workload->complete(workload); workload->complete(workload);
atomic_dec(&vgpu->running_workload_num); atomic_dec(&s->running_workload_num);
wake_up(&scheduler->workload_complete_wq); wake_up(&scheduler->workload_complete_wq);
if (gvt->scheduler.need_reschedule) if (gvt->scheduler.need_reschedule)
@ -637,14 +640,15 @@ static int workload_thread(void *priv)
void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
{ {
struct intel_vgpu_submission *s = &vgpu->submission;
struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
if (atomic_read(&vgpu->running_workload_num)) { if (atomic_read(&s->running_workload_num)) {
gvt_dbg_sched("wait vgpu idle\n"); gvt_dbg_sched("wait vgpu idle\n");
wait_event(scheduler->workload_complete_wq, wait_event(scheduler->workload_complete_wq,
!atomic_read(&vgpu->running_workload_num)); !atomic_read(&s->running_workload_num));
} }
} }
@ -718,8 +722,10 @@ int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
*/ */
void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
{ {
i915_gem_context_put(vgpu->shadow_ctx); struct intel_vgpu_submission *s = &vgpu->submission;
kmem_cache_destroy(vgpu->workloads);
i915_gem_context_put(s->shadow_ctx);
kmem_cache_destroy(s->workloads);
} }
/** /**
@ -734,35 +740,36 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
*/ */
int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
{ {
struct intel_vgpu_submission *s = &vgpu->submission;
enum intel_engine_id i; enum intel_engine_id i;
struct intel_engine_cs *engine; struct intel_engine_cs *engine;
int ret; int ret;
vgpu->shadow_ctx = i915_gem_context_create_gvt( s->shadow_ctx = i915_gem_context_create_gvt(
&vgpu->gvt->dev_priv->drm); &vgpu->gvt->dev_priv->drm);
if (IS_ERR(vgpu->shadow_ctx)) if (IS_ERR(s->shadow_ctx))
return PTR_ERR(vgpu->shadow_ctx); return PTR_ERR(s->shadow_ctx);
bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES); bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
vgpu->workloads = kmem_cache_create("gvt-g_vgpu_workload", s->workloads = kmem_cache_create("gvt-g_vgpu_workload",
sizeof(struct intel_vgpu_workload), 0, sizeof(struct intel_vgpu_workload), 0,
SLAB_HWCACHE_ALIGN, SLAB_HWCACHE_ALIGN,
NULL); NULL);
if (!vgpu->workloads) { if (!s->workloads) {
ret = -ENOMEM; ret = -ENOMEM;
goto out_shadow_ctx; goto out_shadow_ctx;
} }
for_each_engine(engine, vgpu->gvt->dev_priv, i) for_each_engine(engine, vgpu->gvt->dev_priv, i)
INIT_LIST_HEAD(&vgpu->workload_q_head[i]); INIT_LIST_HEAD(&s->workload_q_head[i]);
atomic_set(&vgpu->running_workload_num, 0); atomic_set(&s->running_workload_num, 0);
return 0; return 0;
out_shadow_ctx: out_shadow_ctx:
i915_gem_context_put(vgpu->shadow_ctx); i915_gem_context_put(s->shadow_ctx);
return ret; return ret;
} }

2
drivers/gpu/drm/i915/gvt/scheduler.h
View File

@ -122,7 +122,7 @@ struct intel_shadow_bb_entry {
}; };
#define workload_q_head(vgpu, ring_id) \ #define workload_q_head(vgpu, ring_id) \
(&(vgpu->workload_q_head[ring_id])) (&(vgpu->submission.workload_q_head[ring_id]))
#define queue_workload(workload) do { \ #define queue_workload(workload) do { \
list_add_tail(&workload->list, \ list_add_tail(&workload->list, \

4
drivers/gpu/drm/i915/gvt/vgpu.c
View File

@ -226,7 +226,7 @@ void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
vgpu->active = false; vgpu->active = false;
if (atomic_read(&vgpu->running_workload_num)) { if (atomic_read(&vgpu->submission.running_workload_num)) {
mutex_unlock(&gvt->lock); mutex_unlock(&gvt->lock);
intel_gvt_wait_vgpu_idle(vgpu); intel_gvt_wait_vgpu_idle(vgpu);
mutex_lock(&gvt->lock); mutex_lock(&gvt->lock);
@ -293,7 +293,7 @@ struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
vgpu->gvt = gvt; vgpu->gvt = gvt;
for (i = 0; i < I915_NUM_ENGINES; i++) for (i = 0; i < I915_NUM_ENGINES; i++)
INIT_LIST_HEAD(&vgpu->workload_q_head[i]); INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
ret = intel_vgpu_init_sched_policy(vgpu); ret = intel_vgpu_init_sched_policy(vgpu);
if (ret) if (ret)