mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: create mmhub ras framework
enable mmhub ras feature and create sysfs/debugfs node for mmhub Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -177,7 +177,8 @@ struct amdgpu_gmc {
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struct amdgpu_xgmi xgmi;
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struct amdgpu_irq_src ecc_irq;
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struct ras_common_if *ras_if;
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struct ras_common_if *umc_ras_if;
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struct ras_common_if *mmhub_ras_if;
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};
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#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
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@ -266,7 +266,7 @@ static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct ras_common_if *ras_if = adev->gmc.ras_if;
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struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
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struct ras_dispatch_if ih_data = {
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.entry = entry,
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};
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@ -740,27 +740,25 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
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return 0;
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}
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static int gmc_v9_0_ecc_late_init(void *handle)
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static int gmc_v9_0_ecc_ras_block_late_init(void *handle,
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struct ras_fs_if *fs_info, struct ras_common_if *ras_block)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ras_common_if **ras_if = &adev->gmc.ras_if;
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struct ras_common_if **ras_if = NULL;
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struct ras_ih_if ih_info = {
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.cb = gmc_v9_0_process_ras_data_cb,
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "umc_err_count",
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.debugfs_name = "umc_err_inject",
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};
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struct ras_common_if ras_block = {
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.block = AMDGPU_RAS_BLOCK__UMC,
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.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
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.sub_block_index = 0,
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.name = "umc",
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};
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int r;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
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amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
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if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
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ras_if = &adev->gmc.umc_ras_if;
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else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB)
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ras_if = &adev->gmc.mmhub_ras_if;
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else
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BUG();
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if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
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amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
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return 0;
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}
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@ -775,7 +773,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
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if (r == -EAGAIN) {
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/* request a gpu reset. will run again. */
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amdgpu_ras_request_reset_on_boot(adev,
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AMDGPU_RAS_BLOCK__UMC);
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ras_block->block);
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return 0;
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}
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/* fail to enable ras, cleanup all. */
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@ -789,41 +787,46 @@ static int gmc_v9_0_ecc_late_init(void *handle)
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if (!*ras_if)
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return -ENOMEM;
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**ras_if = ras_block;
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**ras_if = *ras_block;
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r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
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if (r) {
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if (r == -EAGAIN) {
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amdgpu_ras_request_reset_on_boot(adev,
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AMDGPU_RAS_BLOCK__UMC);
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ras_block->block);
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r = 0;
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}
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goto feature;
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}
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ih_info.head = **ras_if;
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fs_info.head = **ras_if;
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fs_info->head = **ras_if;
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r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
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if (r)
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goto interrupt;
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if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
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r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
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if (r)
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goto interrupt;
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}
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amdgpu_ras_debugfs_create(adev, &fs_info);
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amdgpu_ras_debugfs_create(adev, fs_info);
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r = amdgpu_ras_sysfs_create(adev, &fs_info);
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r = amdgpu_ras_sysfs_create(adev, fs_info);
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if (r)
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goto sysfs;
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resume:
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r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
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if (r)
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goto irq;
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if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
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r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
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if (r)
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goto irq;
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}
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return 0;
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irq:
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amdgpu_ras_sysfs_remove(adev, *ras_if);
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sysfs:
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amdgpu_ras_debugfs_remove(adev, *ras_if);
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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interrupt:
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amdgpu_ras_feature_enable(adev, *ras_if, 0);
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feature:
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@ -832,6 +835,40 @@ static int gmc_v9_0_ecc_late_init(void *handle)
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return r;
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}
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static int gmc_v9_0_ecc_late_init(void *handle)
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{
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int r;
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struct ras_fs_if umc_fs_info = {
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.sysfs_name = "umc_err_count",
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.debugfs_name = "umc_err_inject",
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};
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struct ras_common_if umc_ras_block = {
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.block = AMDGPU_RAS_BLOCK__UMC,
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.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
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.sub_block_index = 0,
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.name = "umc",
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};
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struct ras_fs_if mmhub_fs_info = {
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.sysfs_name = "mmhub_err_count",
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.debugfs_name = "mmhub_err_inject",
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};
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struct ras_common_if mmhub_ras_block = {
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.block = AMDGPU_RAS_BLOCK__MMHUB,
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.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
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.sub_block_index = 0,
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.name = "mmhub",
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};
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r = gmc_v9_0_ecc_ras_block_late_init(handle,
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&umc_fs_info, &umc_ras_block);
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if (r)
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return r;
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r = gmc_v9_0_ecc_ras_block_late_init(handle,
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&mmhub_fs_info, &mmhub_ras_block);
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return r;
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}
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static int gmc_v9_0_late_init(void *handle)
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{
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@ -1192,21 +1229,32 @@ static int gmc_v9_0_sw_fini(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
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adev->gmc.ras_if) {
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struct ras_common_if *ras_if = adev->gmc.ras_if;
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adev->gmc.umc_ras_if) {
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struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
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struct ras_ih_if ih_info = {
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.head = *ras_if,
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};
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/*remove fs first*/
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/* remove fs first */
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amdgpu_ras_debugfs_remove(adev, ras_if);
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amdgpu_ras_sysfs_remove(adev, ras_if);
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/*remove the IH*/
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/* remove the IH */
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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amdgpu_ras_feature_enable(adev, ras_if, 0);
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kfree(ras_if);
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}
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
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adev->gmc.mmhub_ras_if) {
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struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if;
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/* remove fs and disable ras feature */
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amdgpu_ras_debugfs_remove(adev, ras_if);
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amdgpu_ras_sysfs_remove(adev, ras_if);
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amdgpu_ras_feature_enable(adev, ras_if, 0);
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kfree(ras_if);
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}
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amdgpu_gem_force_release(adev);
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amdgpu_vm_manager_fini(adev);
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