mirror of https://gitee.com/openkylin/linux.git
octeontx2-af: Add support for CGX link management
CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. - Support to send/receive commands/events to/form firmware. - events/commands implemented * link up * link down * reading firmware version Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Nithya Mani <nmani@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Linu Cherian
David S. Miller
parent
3a4fa841b0
commit
1463f382f5
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@ -24,16 +24,43 @@
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#define DRV_NAME "octeontx2-cgx"
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#define DRV_STRING "Marvell OcteonTX2 CGX/MAC Driver"
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/**
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* struct lmac
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* @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion
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* @cmd_lock: Lock to serialize the command interface
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* @resp: command response
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* @event_cb: callback for linkchange events
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* @cmd_pend: flag set before new command is started
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* flag cleared after command response is received
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* @cgx: parent cgx port
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* @lmac_id: lmac port id
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* @name: lmac port name
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*/
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struct lmac {
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wait_queue_head_t wq_cmd_cmplt;
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struct mutex cmd_lock;
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u64 resp;
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struct cgx_event_cb event_cb;
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bool cmd_pend;
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struct cgx *cgx;
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u8 lmac_id;
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char *name;
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};
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struct cgx {
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void __iomem *reg_base;
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struct pci_dev *pdev;
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u8 cgx_id;
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u8 lmac_count;
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struct lmac *lmac_idmap[MAX_LMAC_PER_CGX];
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struct list_head cgx_list;
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};
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static LIST_HEAD(cgx_list);
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/* CGX PHY management internal APIs */
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static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
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/* Supported devices */
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static const struct pci_device_id cgx_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
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@ -42,11 +69,24 @@ static const struct pci_device_id cgx_id_table[] = {
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MODULE_DEVICE_TABLE(pci, cgx_id_table);
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static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
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{
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writeq(val, cgx->reg_base + (lmac << 18) + offset);
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}
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static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
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{
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return readq(cgx->reg_base + (lmac << 18) + offset);
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}
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static inline struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
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{
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if (!cgx || lmac_id >= MAX_LMAC_PER_CGX)
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return NULL;
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return cgx->lmac_idmap[lmac_id];
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}
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int cgx_get_cgx_cnt(void)
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{
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struct cgx *cgx_dev;
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@ -82,18 +122,312 @@ void *cgx_get_pdata(int cgx_id)
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}
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EXPORT_SYMBOL(cgx_get_pdata);
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static void cgx_lmac_init(struct cgx *cgx)
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/* CGX Firmware interface low level support */
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static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
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{
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struct cgx *cgx = lmac->cgx;
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struct device *dev;
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int err = 0;
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u64 cmd;
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/* Ensure no other command is in progress */
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err = mutex_lock_interruptible(&lmac->cmd_lock);
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if (err)
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return err;
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/* Ensure command register is free */
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cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
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if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
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err = -EBUSY;
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goto unlock;
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}
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/* Update ownership in command request */
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req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
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/* Mark this lmac as pending, before we start */
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lmac->cmd_pend = true;
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/* Start command in hardware */
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cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
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/* Ensure command is completed without errors */
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if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
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msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
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dev = &cgx->pdev->dev;
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dev_err(dev, "cgx port %d:%d cmd timeout\n",
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cgx->cgx_id, lmac->lmac_id);
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err = -EIO;
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goto unlock;
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}
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/* we have a valid command response */
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smp_rmb(); /* Ensure the latest updates are visible */
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*resp = lmac->resp;
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unlock:
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mutex_unlock(&lmac->cmd_lock);
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return err;
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}
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static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp,
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struct cgx *cgx, int lmac_id)
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{
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struct lmac *lmac;
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int err;
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lmac = lmac_pdata(lmac_id, cgx);
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if (!lmac)
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return -ENODEV;
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err = cgx_fwi_cmd_send(req, resp, lmac);
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/* Check for valid response */
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if (!err) {
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if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
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return -EIO;
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else
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return 0;
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}
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return err;
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}
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/* Hardware event handlers */
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static inline void cgx_link_change_handler(u64 lstat,
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struct lmac *lmac)
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{
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struct cgx *cgx = lmac->cgx;
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struct cgx_link_event event;
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struct device *dev;
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dev = &cgx->pdev->dev;
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event.lstat.link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
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event.lstat.full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
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event.lstat.speed = FIELD_GET(RESP_LINKSTAT_SPEED, lstat);
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event.lstat.err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
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event.cgx_id = cgx->cgx_id;
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event.lmac_id = lmac->lmac_id;
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if (!lmac->event_cb.notify_link_chg) {
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dev_dbg(dev, "cgx port %d:%d Link change handler null",
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cgx->cgx_id, lmac->lmac_id);
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if (event.lstat.err_type != CGX_ERR_NONE) {
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dev_err(dev, "cgx port %d:%d Link error %d\n",
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cgx->cgx_id, lmac->lmac_id,
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event.lstat.err_type);
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}
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dev_info(dev, "cgx port %d:%d Link status %s, speed %x\n",
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cgx->cgx_id, lmac->lmac_id,
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event.lstat.link_up ? "UP" : "DOWN",
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event.lstat.speed);
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return;
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}
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if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
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dev_err(dev, "event notification failure\n");
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}
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static inline bool cgx_cmdresp_is_linkevent(u64 event)
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{
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u8 id;
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id = FIELD_GET(EVTREG_ID, event);
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if (id == CGX_CMD_LINK_BRING_UP ||
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id == CGX_CMD_LINK_BRING_DOWN)
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return true;
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else
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return false;
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}
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static inline bool cgx_event_is_linkevent(u64 event)
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{
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if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
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return true;
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else
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return false;
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}
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static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
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{
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struct lmac *lmac = data;
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struct device *dev;
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struct cgx *cgx;
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u64 event;
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cgx = lmac->cgx;
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event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
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if (!FIELD_GET(EVTREG_ACK, event))
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return IRQ_NONE;
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dev = &cgx->pdev->dev;
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switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
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case CGX_EVT_CMD_RESP:
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/* Copy the response. Since only one command is active at a
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* time, there is no way a response can get overwritten
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*/
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lmac->resp = event;
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/* Ensure response is updated before thread context starts */
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smp_wmb();
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/* There wont be separate events for link change initiated from
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* software; Hence report the command responses as events
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*/
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if (cgx_cmdresp_is_linkevent(event))
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cgx_link_change_handler(event, lmac);
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/* Release thread waiting for completion */
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lmac->cmd_pend = false;
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wake_up_interruptible(&lmac->wq_cmd_cmplt);
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break;
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case CGX_EVT_ASYNC:
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if (cgx_event_is_linkevent(event))
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cgx_link_change_handler(event, lmac);
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break;
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}
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/* Any new event or command response will be posted by firmware
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* only after the current status is acked.
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* Ack the interrupt register as well.
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*/
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cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
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cgx_write(lmac->cgx, lmac->lmac_id, CGXX_CMRX_INT, FW_CGX_INT);
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return IRQ_HANDLED;
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}
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/* APIs for PHY management using CGX firmware interface */
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/* callback registration for hardware events like link change */
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int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
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{
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struct cgx *cgx = cgxd;
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struct lmac *lmac;
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lmac = lmac_pdata(lmac_id, cgx);
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if (!lmac)
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return -ENODEV;
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lmac->event_cb = *cb;
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return 0;
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}
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EXPORT_SYMBOL(cgx_lmac_evh_register);
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static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
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{
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u64 req = 0;
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u64 resp;
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if (enable)
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req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
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else
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req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
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return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
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}
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EXPORT_SYMBOL(cgx_fwi_link_change);
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static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
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{
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u64 req = 0;
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req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
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return cgx_fwi_cmd_generic(req, resp, cgx, 0);
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}
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static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
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{
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struct device *dev = &cgx->pdev->dev;
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int major_ver, minor_ver;
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u64 resp;
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int err;
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if (!cgx->lmac_count)
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return 0;
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err = cgx_fwi_read_version(&resp, cgx);
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if (err)
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return err;
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major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
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minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
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dev_dbg(dev, "Firmware command interface version = %d.%d\n",
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major_ver, minor_ver);
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if (major_ver != CGX_FIRMWARE_MAJOR_VER ||
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minor_ver != CGX_FIRMWARE_MINOR_VER)
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return -EIO;
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else
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return 0;
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}
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static int cgx_lmac_init(struct cgx *cgx)
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{
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struct lmac *lmac;
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int i, err;
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cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7;
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if (cgx->lmac_count > MAX_LMAC_PER_CGX)
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cgx->lmac_count = MAX_LMAC_PER_CGX;
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for (i = 0; i < cgx->lmac_count; i++) {
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lmac = kcalloc(1, sizeof(struct lmac), GFP_KERNEL);
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if (!lmac)
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return -ENOMEM;
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lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
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if (!lmac->name)
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return -ENOMEM;
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sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
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lmac->lmac_id = i;
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lmac->cgx = cgx;
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init_waitqueue_head(&lmac->wq_cmd_cmplt);
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mutex_init(&lmac->cmd_lock);
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err = request_irq(pci_irq_vector(cgx->pdev,
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CGX_LMAC_FWI + i * 9),
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cgx_fwi_event_handler, 0, lmac->name, lmac);
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if (err)
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return err;
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/* Enable interrupt */
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cgx_write(cgx, lmac->lmac_id, CGXX_CMRX_INT_ENA_W1S,
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FW_CGX_INT);
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/* Add reference */
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cgx->lmac_idmap[i] = lmac;
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}
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return cgx_lmac_verify_fwi_version(cgx);
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}
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static int cgx_lmac_exit(struct cgx *cgx)
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{
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struct lmac *lmac;
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int i;
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/* Free all lmac related resources */
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for (i = 0; i < cgx->lmac_count; i++) {
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lmac = cgx->lmac_idmap[i];
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if (!lmac)
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continue;
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free_irq(pci_irq_vector(cgx->pdev, CGX_LMAC_FWI + i * 9), lmac);
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kfree(lmac->name);
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kfree(lmac);
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}
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return 0;
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}
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static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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struct cgx *cgx;
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int err;
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int err, nvec;
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cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
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if (!cgx)
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@ -123,14 +457,27 @@ static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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goto err_release_regions;
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}
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nvec = CGX_NVEC;
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err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
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if (err < 0 || err != nvec) {
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dev_err(dev, "Request for %d msix vectors failed, err %d\n",
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nvec, err);
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goto err_release_regions;
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}
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list_add(&cgx->cgx_list, &cgx_list);
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cgx->cgx_id = cgx_get_cgx_cnt() - 1;
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cgx_lmac_init(cgx);
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err = cgx_lmac_init(cgx);
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if (err)
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goto err_release_lmac;
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return 0;
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err_release_regions:
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err_release_lmac:
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cgx_lmac_exit(cgx);
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list_del(&cgx->cgx_list);
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err_release_regions:
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pci_release_regions(pdev);
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err_disable_device:
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pci_disable_device(pdev);
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@ -142,7 +489,9 @@ static void cgx_remove(struct pci_dev *pdev)
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{
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struct cgx *cgx = pci_get_drvdata(pdev);
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cgx_lmac_exit(cgx);
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list_del(&cgx->cgx_list);
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pci_free_irq_vectors(pdev);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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pci_set_drvdata(pdev, NULL);
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@ -11,6 +11,8 @@
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#ifndef CGX_H
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#define CGX_H
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#include "cgx_fw_if.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_CGX 0xA059
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@ -22,12 +24,42 @@
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#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
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/* Registers */
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#define CGXX_CMRX_INT 0x040
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#define FW_CGX_INT BIT_ULL(1)
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#define CGXX_CMRX_INT_ENA_W1S 0x058
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#define CGXX_CMRX_RX_ID_MAP 0x060
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#define CGXX_CMRX_RX_LMACS 0x128
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#define CGXX_SCRATCH0_REG 0x1050
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#define CGXX_SCRATCH1_REG 0x1058
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#define CGX_CONST 0x2000
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|
||||
#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
|
||||
#define CGX_EVENT_REG CGXX_SCRATCH0_REG
|
||||
#define CGX_CMD_TIMEOUT 2200 /* msecs */
|
||||
|
||||
#define CGX_NVEC 37
|
||||
#define CGX_LMAC_FWI 0
|
||||
|
||||
struct cgx_link_event {
|
||||
struct cgx_lnk_sts lstat;
|
||||
u8 cgx_id;
|
||||
u8 lmac_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cgx_event_cb
|
||||
* @notify_link_chg: callback for link change notification
|
||||
* @data: data passed to callback function
|
||||
*/
|
||||
struct cgx_event_cb {
|
||||
int (*notify_link_chg)(struct cgx_link_event *event, void *data);
|
||||
void *data;
|
||||
};
|
||||
|
||||
extern struct pci_driver cgx_driver;
|
||||
|
||||
int cgx_get_cgx_cnt(void);
|
||||
int cgx_get_lmac_cnt(void *cgxd);
|
||||
void *cgx_get_pdata(int cgx_id);
|
||||
int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
|
||||
#endif /* CGX_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,186 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* Marvell OcteonTx2 CGX driver
|
||||
*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CGX_FW_INTF_H__
|
||||
#define __CGX_FW_INTF_H__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define CGX_FIRMWARE_MAJOR_VER 1
|
||||
#define CGX_FIRMWARE_MINOR_VER 0
|
||||
|
||||
#define CGX_EVENT_ACK 1UL
|
||||
|
||||
/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
|
||||
enum cgx_error_type {
|
||||
CGX_ERR_NONE,
|
||||
CGX_ERR_LMAC_NOT_ENABLED,
|
||||
CGX_ERR_LMAC_MODE_INVALID,
|
||||
CGX_ERR_REQUEST_ID_INVALID,
|
||||
CGX_ERR_PREV_ACK_NOT_CLEAR,
|
||||
CGX_ERR_PHY_LINK_DOWN,
|
||||
CGX_ERR_PCS_RESET_FAIL,
|
||||
CGX_ERR_AN_CPT_FAIL,
|
||||
CGX_ERR_TX_NOT_IDLE,
|
||||
CGX_ERR_RX_NOT_IDLE,
|
||||
CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
|
||||
CGX_ERR_SPUX_RX_ALIGN_FAIL,
|
||||
CGX_ERR_SPUX_TX_FAULT,
|
||||
CGX_ERR_SPUX_RX_FAULT,
|
||||
CGX_ERR_SPUX_RESET_FAIL,
|
||||
CGX_ERR_SPUX_AN_RESET_FAIL,
|
||||
CGX_ERR_SPUX_USX_AN_RESET_FAIL,
|
||||
CGX_ERR_SMUX_RX_LINK_NOT_OK,
|
||||
CGX_ERR_PCS_RECV_LINK_FAIL,
|
||||
CGX_ERR_TRAINING_FAIL,
|
||||
CGX_ERR_RX_EQU_FAIL,
|
||||
CGX_ERR_SPUX_BER_FAIL,
|
||||
CGX_ERR_SPUX_RSFEC_ALGN_FAIL, /* = 22 */
|
||||
};
|
||||
|
||||
/* LINK speed types */
|
||||
enum cgx_link_speed {
|
||||
CGX_LINK_NONE,
|
||||
CGX_LINK_10M,
|
||||
CGX_LINK_100M,
|
||||
CGX_LINK_1G,
|
||||
CGX_LINK_2HG,
|
||||
CGX_LINK_5G,
|
||||
CGX_LINK_10G,
|
||||
CGX_LINK_20G,
|
||||
CGX_LINK_25G,
|
||||
CGX_LINK_40G,
|
||||
CGX_LINK_50G,
|
||||
CGX_LINK_100G,
|
||||
CGX_LINK_SPEED_MAX,
|
||||
};
|
||||
|
||||
/* REQUEST ID types. Input to firmware */
|
||||
enum cgx_cmd_id {
|
||||
CGX_CMD_NONE,
|
||||
CGX_CMD_GET_FW_VER,
|
||||
CGX_CMD_GET_MAC_ADDR,
|
||||
CGX_CMD_SET_MTU,
|
||||
CGX_CMD_GET_LINK_STS, /* optional to user */
|
||||
CGX_CMD_LINK_BRING_UP,
|
||||
CGX_CMD_LINK_BRING_DOWN,
|
||||
CGX_CMD_INTERNAL_LBK,
|
||||
CGX_CMD_EXTERNAL_LBK,
|
||||
CGX_CMD_HIGIG,
|
||||
CGX_CMD_LINK_STATE_CHANGE,
|
||||
CGX_CMD_MODE_CHANGE, /* hot plug support */
|
||||
CGX_CMD_INTF_SHUTDOWN,
|
||||
CGX_CMD_IRQ_ENABLE,
|
||||
CGX_CMD_IRQ_DISABLE,
|
||||
};
|
||||
|
||||
/* async event ids */
|
||||
enum cgx_evt_id {
|
||||
CGX_EVT_NONE,
|
||||
CGX_EVT_LINK_CHANGE,
|
||||
};
|
||||
|
||||
/* event types - cause of interrupt */
|
||||
enum cgx_evt_type {
|
||||
CGX_EVT_ASYNC,
|
||||
CGX_EVT_CMD_RESP
|
||||
};
|
||||
|
||||
enum cgx_stat {
|
||||
CGX_STAT_SUCCESS,
|
||||
CGX_STAT_FAIL
|
||||
};
|
||||
|
||||
enum cgx_cmd_own {
|
||||
CGX_CMD_OWN_NS,
|
||||
CGX_CMD_OWN_FIRMWARE,
|
||||
};
|
||||
|
||||
/* m - bit mask
|
||||
* y - value to be written in the bitrange
|
||||
* x - input value whose bitrange to be modified
|
||||
*/
|
||||
#define FIELD_SET(m, y, x) \
|
||||
(((x) & ~(m)) | \
|
||||
FIELD_PREP((m), (y)))
|
||||
|
||||
/* scratchx(0) CSR used for ATF->non-secure SW communication.
|
||||
* This acts as the status register
|
||||
* Provides details on command ack/status, command response, error details
|
||||
*/
|
||||
#define EVTREG_ACK BIT_ULL(0)
|
||||
#define EVTREG_EVT_TYPE BIT_ULL(1)
|
||||
#define EVTREG_STAT BIT_ULL(2)
|
||||
#define EVTREG_ID GENMASK_ULL(8, 3)
|
||||
|
||||
/* Response to command IDs with command status as CGX_STAT_FAIL
|
||||
*
|
||||
* Not applicable for commands :
|
||||
* CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
|
||||
*/
|
||||
#define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
|
||||
|
||||
/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
|
||||
* CGX_STAT_SUCCESS
|
||||
*/
|
||||
#define RESP_MAJOR_VER GENMASK_ULL(12, 9)
|
||||
#define RESP_MINOR_VER GENMASK_ULL(16, 13)
|
||||
|
||||
/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
|
||||
* CGX_STAT_SUCCESS
|
||||
*/
|
||||
#define RESP_MAC_ADDR GENMASK_ULL(56, 9)
|
||||
|
||||
/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
|
||||
* status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
|
||||
*
|
||||
* In case of CGX_STAT_FAIL, it indicates CGX configuration failed
|
||||
* when processing link up/down/change command.
|
||||
* Both err_type and current link status will be updated
|
||||
*
|
||||
* In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
|
||||
* link status will be updated
|
||||
*/
|
||||
struct cgx_lnk_sts {
|
||||
uint64_t reserved1:9;
|
||||
uint64_t link_up:1;
|
||||
uint64_t full_duplex:1;
|
||||
uint64_t speed:4; /* cgx_link_speed */
|
||||
uint64_t err_type:10;
|
||||
uint64_t reserved2:39;
|
||||
};
|
||||
|
||||
#define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
|
||||
#define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)
|
||||
#define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)
|
||||
#define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)
|
||||
|
||||
/* scratchx(1) CSR used for non-secure SW->ATF communication
|
||||
* This CSR acts as a command register
|
||||
*/
|
||||
#define CMDREG_OWN BIT_ULL(0)
|
||||
#define CMDREG_ID GENMASK_ULL(7, 2)
|
||||
|
||||
/* Any command using enable/disable as an argument need
|
||||
* to set this bitfield.
|
||||
* Ex: Loopback, HiGig...
|
||||
*/
|
||||
#define CMDREG_ENABLE BIT_ULL(8)
|
||||
|
||||
/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
|
||||
#define CMDMTU_SIZE GENMASK_ULL(23, 8)
|
||||
|
||||
/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
|
||||
#define CMDLINKCHANGE_LINKUP BIT_ULL(8)
|
||||
#define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
|
||||
#define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)
|
||||
|
||||
#endif /* __CGX_FW_INTF_H__ */
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Marvell OcteonTx2 RVU Admin Function driver
|
||||
*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include "rvu.h"
|
||||
#include "cgx.h"
|
||||
|
||||
static inline u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
|
||||
{
|
||||
return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
|
||||
}
|
||||
|
||||
static void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
|
||||
{
|
||||
if (cgx_id >= rvu->cgx_cnt)
|
||||
return NULL;
|
||||
|
||||
return rvu->cgx_idmap[cgx_id];
|
||||
}
|
||||
|
||||
static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
|
||||
{
|
||||
int cgx_cnt = rvu->cgx_cnt;
|
||||
int cgx, lmac_cnt, lmac;
|
||||
int pf = PF_CGXMAP_BASE;
|
||||
int size;
|
||||
|
||||
if (!cgx_cnt)
|
||||
return 0;
|
||||
|
||||
if (cgx_cnt > 0xF || MAX_LMAC_PER_CGX > 0xF)
|
||||
return -EINVAL;
|
||||
|
||||
/* Alloc map table
|
||||
* An additional entry is required since PF id starts from 1 and
|
||||
* hence entry at offset 0 is invalid.
|
||||
*/
|
||||
size = (cgx_cnt * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
|
||||
rvu->pf2cgxlmac_map = devm_kzalloc(rvu->dev, size, GFP_KERNEL);
|
||||
if (!rvu->pf2cgxlmac_map)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Initialize offset 0 with an invalid cgx and lmac id */
|
||||
rvu->pf2cgxlmac_map[0] = 0xFF;
|
||||
|
||||
/* Reverse map table */
|
||||
rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
|
||||
cgx_cnt * MAX_LMAC_PER_CGX * sizeof(u16),
|
||||
GFP_KERNEL);
|
||||
if (!rvu->cgxlmac2pf_map)
|
||||
return -ENOMEM;
|
||||
|
||||
rvu->cgx_mapped_pfs = 0;
|
||||
for (cgx = 0; cgx < cgx_cnt; cgx++) {
|
||||
lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu));
|
||||
for (lmac = 0; lmac < lmac_cnt; lmac++, pf++) {
|
||||
rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
|
||||
rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
|
||||
rvu->cgx_mapped_pfs++;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rvu_cgx_probe(struct rvu *rvu)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* find available cgx ports */
|
||||
rvu->cgx_cnt = cgx_get_cgx_cnt();
|
||||
if (!rvu->cgx_cnt) {
|
||||
dev_info(rvu->dev, "No CGX devices found!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt * sizeof(void *),
|
||||
GFP_KERNEL);
|
||||
if (!rvu->cgx_idmap)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Initialize the cgxdata table */
|
||||
for (i = 0; i < rvu->cgx_cnt; i++)
|
||||
rvu->cgx_idmap[i] = cgx_get_pdata(i);
|
||||
|
||||
/* Map CGX LMAC interfaces to RVU PFs */
|
||||
return rvu_map_cgx_lmac_pf(rvu);
|
||||
}
|
||||
Loading…
Reference in New Issue