mirror of https://gitee.com/openkylin/linux.git
drm: meson: viu: use proper macros instead of magic constants
This patch add new macros which are used to set the following registers: - VIU_SW_RESET - VIU_OSD1_CTRL_STAT - VIU_OSD2_CTRL_STAT - VIU_OSD1_FIFO_CTRL_STAT - VIU_OSD2_FIFO_CTRL_STAT - VIU_MISC_CTRL0 - VIU_OSD_BLEND_CTRL - OSD1_BLEND_SRC_CTRL - OSD2_BLEND_SRC_CTRL - DOLBY_PATH_CTRL Signed-off-by: Julien Masson <jmasson@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: fix OSD1_BLEND_SRC_CTRL register init value for G12A] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/86sgrz82em.fsf@baylibre.com
This commit is contained in:
Julien Masson
Neil Armstrong
parent
0ce266d018
commit
147ae1cbaa
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@ -328,7 +328,7 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
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/* Disable OSD1 */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
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writel_bits_relaxed(3 << 8, 0,
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writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
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priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
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else
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
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@ -138,11 +138,19 @@
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#define VIU_ADDR_START 0x1a00
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#define VIU_ADDR_END 0x1aff
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#define VIU_SW_RESET 0x1a01
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#define VIU_SW_RESET_OSD1 BIT(0)
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#define VIU_MISC_CTRL0 0x1a06
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#define VIU_CTRL0_VD1_AFBC_MASK 0x170000
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#define VIU_MISC_CTRL1 0x1a07
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#define D2D3_INTF_LENGTH 0x1a08
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#define D2D3_INTF_CTRL0 0x1a09
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#define VIU_OSD1_CTRL_STAT 0x1a10
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#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
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#define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8)
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#define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8)
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#define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8)
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#define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8)
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#define VIU_OSD1_OSD_ENABLE BIT(21)
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#define VIU_OSD1_CTRL_STAT2 0x1a2d
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#define VIU_OSD1_COLOR_ADDR 0x1a11
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#define VIU_OSD1_COLOR 0x1a12
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@ -232,6 +240,12 @@
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#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f
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#define VIU_OSD3_DIMM_CTRL 0x3da0
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#define VIU_OSD_DDR_PRIORITY_URGENT BIT(0)
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#define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5)
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#define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12)
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#define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22)
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#define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24)
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#define VD1_IF0_GEN_REG 0x1a50
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#define VD1_IF0_CANVAS0 0x1a51
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#define VD1_IF0_CANVAS1 0x1a52
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@ -1612,10 +1626,18 @@
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#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c
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#define DOLBY_PATH_CTRL 0x1a0c
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#define DOLBY_BYPASS_EN(val) (val & 0xf)
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#define OSD_PATH_MISC_CTRL 0x1a0e
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#define MALI_AFBCD_TOP_CTRL 0x1a0f
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#define VIU_OSD_BLEND_CTRL 0x39b0
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#define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
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#define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20)
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#define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24)
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#define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25)
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#define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26)
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#define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)
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#define VIU_OSD_BLEND_HOLD_LINES(lines) ((lines & 0x7) << 29)
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#define VIU_OSD_BLEND_CTRL1 0x39c0
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#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
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#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
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@ -1657,6 +1679,11 @@
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#define VD_BLEND_POSTBLD_PREMULT_EN BIT(16)
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#define OSD1_BLEND_SRC_CTRL 0x1dfd
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#define OSD2_BLEND_SRC_CTRL 0x1dfe
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#define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8)
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#define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8)
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#define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8)
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#define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8)
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#define OSD_BLEND_PATH_SEL_ENABLE BIT(20)
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#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968
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#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
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@ -320,9 +320,9 @@ void meson_viu_osd1_reset(struct meson_drm *priv)
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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/* Reset OSD1 */
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writel_bits_relaxed(BIT(0), BIT(0),
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writel_bits_relaxed(VIU_SW_RESET_OSD1, VIU_SW_RESET_OSD1,
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priv->io_base + _REG(VIU_SW_RESET));
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writel_bits_relaxed(BIT(0), 0,
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writel_bits_relaxed(VIU_SW_RESET_OSD1, 0,
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priv->io_base + _REG(VIU_SW_RESET));
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/* Rewrite these registers state lost in the reset */
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@ -335,15 +335,22 @@ void meson_viu_osd1_reset(struct meson_drm *priv)
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meson_viu_load_matrix(priv);
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}
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static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length)
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{
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uint32_t val = (((length & 0x80) % 24) / 12);
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return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31));
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}
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void meson_viu_init(struct meson_drm *priv)
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{
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uint32_t reg;
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/* Disable OSDs */
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writel_bits_relaxed(BIT(0) | BIT(21), 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_bits_relaxed(BIT(0) | BIT(21), 0,
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priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
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writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
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priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
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/* On GXL/GXM, Use the 10bit HDR conversion matrix */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
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@ -354,19 +361,17 @@ void meson_viu_init(struct meson_drm *priv)
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true);
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/* Initialize OSD1 fifo control register */
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reg = BIT(0) | /* Urgent DDR request priority */
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(4 << 5); /* hold_fifo_lines */
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reg = VIU_OSD_DDR_PRIORITY_URGENT |
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VIU_OSD_HOLD_FIFO_LINES(4) |
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VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
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VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
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VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
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reg |= (1 << 10) | /* burst length 32 */
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(32 << 12) | /* fifo_depth_val: 32*8=256 */
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(2 << 22) | /* 4 words in 1 burst */
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(2 << 24) |
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(1 << 31);
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reg |= meson_viu_osd_burst_length_reg(32);
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else
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reg |= (3 << 10) | /* burst length 64 */
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(32 << 12) | /* fifo_depth_val: 32*8=256 */
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(2 << 22) | /* 4 words in 1 burst */
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(2 << 24);
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reg |= meson_viu_osd_burst_length_reg(64);
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
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@ -379,12 +384,9 @@ void meson_viu_init(struct meson_drm *priv)
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priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
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/* Disable VD1 AFBC */
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/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 */
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writel_bits_relaxed(0x7 << 16, 0,
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priv->io_base + _REG(VIU_MISC_CTRL0));
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/* afbc vd1 set=0 */
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writel_bits_relaxed(BIT(20), 0,
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priv->io_base + _REG(VIU_MISC_CTRL0));
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/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
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writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0,
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priv->io_base + _REG(VIU_MISC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
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writel_relaxed(0x00FF00C0,
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@ -393,27 +395,31 @@ void meson_viu_init(struct meson_drm *priv)
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priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
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if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
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writel_relaxed(4 << 29 |
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1 << 27 |
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1 << 26 | /* blend_din0 input to blend0 */
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1 << 25 | /* blend1_dout to blend2 */
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1 << 24 | /* blend1_din3 input to blend1 */
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1 << 20 |
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0 << 16 |
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1,
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priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
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writel_relaxed(1 << 20,
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priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
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writel_relaxed(1 << 20,
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priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
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writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
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VIU_OSD_BLEND_REORDER(1, 0) |
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VIU_OSD_BLEND_REORDER(2, 0) |
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VIU_OSD_BLEND_REORDER(3, 0) |
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VIU_OSD_BLEND_DIN_EN(1) |
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VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
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VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
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VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
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VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
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VIU_OSD_BLEND_HOLD_LINES(4),
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priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
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writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
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priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
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writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
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priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
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writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
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writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
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writel_relaxed(0,
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priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0));
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writel_relaxed(0,
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priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA));
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writel_bits_relaxed(0x3 << 2, 0x3 << 2,
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priv->io_base + _REG(DOLBY_PATH_CTRL));
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writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc),
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priv->io_base + _REG(DOLBY_PATH_CTRL));
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}
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priv->viu.osd1_enabled = false;
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