mirror of https://gitee.com/openkylin/linux.git
sh: More I/O routine overhauling.
This tidies up a lot of the PIO/MMIO split. No in-tree platforms were making use of the MMIO overloading through the machvec (nor have any of them been in some time), so we just kill all of that off. The ISA I/O routine wrapping remains unaffected, which remains the only special casing outside of the iomap API that boards need to think about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
bc0f424faa
commit
14866543ad
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@ -1,27 +1,26 @@
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#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l}/write{b,w,l} are for PCI,
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* read{b,w,l,q}/write{b,w,l,q} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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* These may (will) be platform specific function.
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*
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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* For read{b,w,l} and write{b,w,l} there are also __raw versions, which
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* do not have a memory barrier after them.
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*
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* In addition, we have
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* ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
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* which are processor specific.
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*/
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/*
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* We follow the Alpha convention here:
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* __inb expands to an inline function call (which calls via the mv)
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* _inb is a real function call (note ___raw fns are _ version of __raw)
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* inb by default expands to _inb, but the machine specific code may
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* define it to __inb if it chooses.
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* While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
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* automatically, there are also __raw versions, which do not.
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*
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* Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
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* SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
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* these have the same semantics as the __raw variants, and as such, all
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* new code should be using the __raw versions.
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*
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* All ISA I/O routines are wrapped through the machine vector. If a
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* board does not provide overrides, a generic set that are copied in
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* from the default machine vector are used instead. These are largely
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* for old compat code for I/O offseting to SuperIOs, all of which are
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* better handled through the machvec ioport mapping routines these days.
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*/
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#include <asm/cache.h>
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#include <asm/system.h>
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@ -31,7 +30,6 @@
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#include <asm-generic/iomap.h>
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#ifdef __KERNEL__
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/*
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* Depending on which platform we are running on, we need different
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* I/O functions.
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@ -40,90 +38,64 @@
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#include <asm/io_generic.h>
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#include <asm/io_trapped.h>
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#define maybebadio(port) \
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printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
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__FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
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#define inb(p) sh_mv.mv_inb((p))
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#define inw(p) sh_mv.mv_inw((p))
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#define inl(p) sh_mv.mv_inl((p))
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#define outb(x,p) sh_mv.mv_outb((x),(p))
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#define outw(x,p) sh_mv.mv_outw((x),(p))
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#define outl(x,p) sh_mv.mv_outl((x),(p))
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/*
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* Since boards are able to define their own set of I/O routines through
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* their respective machine vector, we always wrap through the mv.
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*
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* Also, in the event that a board hasn't provided its own definition for
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* a given routine, it will be wrapped to generic code at run-time.
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*/
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#define inb_p(p) sh_mv.mv_inb_p((p))
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#define inw_p(p) sh_mv.mv_inw_p((p))
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#define inl_p(p) sh_mv.mv_inl_p((p))
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#define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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#define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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#define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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#define __inb(p) sh_mv.mv_inb((p))
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#define __inw(p) sh_mv.mv_inw((p))
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#define __inl(p) sh_mv.mv_inl((p))
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#define __outb(x,p) sh_mv.mv_outb((x),(p))
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#define __outw(x,p) sh_mv.mv_outw((x),(p))
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#define __outl(x,p) sh_mv.mv_outl((x),(p))
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#define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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#define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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#define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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#define __inb_p(p) sh_mv.mv_inb_p((p))
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#define __inw_p(p) sh_mv.mv_inw_p((p))
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#define __inl_p(p) sh_mv.mv_inl_p((p))
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#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
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#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
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#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
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#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
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#define __readb(a) sh_mv.mv_readb((a))
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#define __readw(a) sh_mv.mv_readw((a))
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#define __readl(a) sh_mv.mv_readl((a))
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#define __writeb(v,a) sh_mv.mv_writeb((v),(a))
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#define __writew(v,a) sh_mv.mv_writew((v),(a))
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#define __writel(v,a) sh_mv.mv_writel((v),(a))
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#define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; })
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#define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; })
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#define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; })
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#define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; })
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#define inb __inb
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#define inw __inw
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#define inl __inl
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#define outb __outb
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#define outw __outw
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#define outl __outl
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#define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
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#define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
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#define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
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#define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); })
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#define inb_p __inb_p
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#define inw_p __inw_p
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#define inl_p __inl_p
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#define outb_p __outb_p
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#define outw_p __outw_p
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#define outl_p __outl_p
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/* SuperH on-chip I/O functions */
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#define ctrl_inb __raw_readb
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#define ctrl_inw __raw_readw
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#define ctrl_inl __raw_readl
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#define ctrl_inq __raw_readq
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#define insb __insb
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#define insw __insw
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#define insl __insl
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#define outsb __outsb
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#define outsw __outsw
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#define outsl __outsl
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#define ctrl_outb __raw_writeb
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#define ctrl_outw __raw_writew
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#define ctrl_outl __raw_writel
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#define ctrl_outq __raw_writeq
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
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void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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/*
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* The platform header files may define some of these macros to use
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* the inlined versions where appropriate. These macros may also be
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* redefined by userlevel programs.
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*/
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#define readb(a) ({ unsigned int r_ = __readb(a); mb(); r_; })
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#define readw(a) ({ unsigned int r_ = __readw(a); mb(); r_; })
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#define readl(a) ({ unsigned int r_ = __readl(a); mb(); r_; })
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#define writeb(v,a) ({ __writeb((v),(a)); mb(); })
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#define writew(v,a) ({ __writew((v),(a)); mb(); })
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#define writel(v,a) ({ __writel((v),(a)); mb(); })
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static inline void ctrl_delay(void)
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{
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#ifdef P2SEG
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__raw_readw(P2SEG);
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#endif
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}
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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@ -151,18 +123,23 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
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__BUILD_MEMORY_STRING(b, u8)
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__BUILD_MEMORY_STRING(w, u16)
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__BUILD_MEMORY_STRING(q, u64)
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#define writesb __raw_writesb
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#define writesw __raw_writesw
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#define writesl __raw_writesl
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void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#define readsb __raw_readsb
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#define readsw __raw_readsw
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#define readsl __raw_readsl
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#define writesb __raw_writesb
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#define writesw __raw_writesw
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#define writesl __raw_writesl
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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#define readsb __raw_readsb
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#define readsw __raw_readsw
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#define readsl __raw_readsl
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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#define readq_relaxed(a) readq(a)
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/* Simple MMIO */
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#define ioread8(a) __raw_readb(a)
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@ -185,15 +162,17 @@ __BUILD_MEMORY_STRING(w, u16)
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#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
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#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
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#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
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/* synco on SH-4A, otherwise a nop */
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#define mmiowb() wmb()
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#define IO_SPACE_LIMIT 0xffffffff
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extern unsigned long generic_io_base;
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/*
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* This function provides a method for the generic case where a board-specific
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* ioport_map simply needs to return the port + some arbitrary port base.
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* This function provides a method for the generic case where a
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* board-specific ioport_map simply needs to return the port + some
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* arbitrary port base.
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*
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* We use this at board setup time to implicitly set the port base, and
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* as a result, we can use the generic ioport_map.
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@ -206,57 +185,9 @@ static inline void __set_io_port_base(unsigned long pbase)
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#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
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/* We really want to try and get these to memcpy etc */
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extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
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extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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extern void memset_io(volatile void __iomem *, int, unsigned long);
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/* SuperH on-chip I/O functions */
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static inline unsigned char ctrl_inb(unsigned long addr)
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{
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return *(volatile unsigned char*)addr;
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}
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static inline unsigned short ctrl_inw(unsigned long addr)
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{
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return *(volatile unsigned short*)addr;
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}
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static inline unsigned int ctrl_inl(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline unsigned long long ctrl_inq(unsigned long addr)
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{
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return *(volatile unsigned long long*)addr;
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}
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static inline void ctrl_outb(unsigned char b, unsigned long addr)
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{
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*(volatile unsigned char*)addr = b;
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}
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static inline void ctrl_outw(unsigned short b, unsigned long addr)
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{
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*(volatile unsigned short*)addr = b;
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}
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static inline void ctrl_outl(unsigned int b, unsigned long addr)
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{
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*(volatile unsigned long*)addr = b;
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}
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static inline void ctrl_outq(unsigned long long b, unsigned long addr)
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{
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*(volatile unsigned long long*)addr = b;
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}
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static inline void ctrl_delay(void)
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{
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#ifdef P2SEG
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ctrl_inw(P2SEG);
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#endif
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}
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void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
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void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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void memset_io(volatile void __iomem *, int, unsigned long);
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/* Quad-word real-mode I/O, don't ask.. */
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unsigned long long peek_real_address_q(unsigned long long addr);
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@ -347,6 +278,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
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#define iounmap(addr) \
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__iounmap((addr))
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#define maybebadio(port) \
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printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
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__func__, __LINE__, (port), (u32)__builtin_return_address(0))
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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@ -33,13 +33,6 @@ void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long
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void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
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void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
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u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
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u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
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u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
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void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
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void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
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void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
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void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
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void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
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@ -42,13 +42,6 @@ struct sh_machine_vector {
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void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
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void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
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u8 (*mv_readb)(void __iomem *);
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u16 (*mv_readw)(void __iomem *);
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u32 (*mv_readl)(void __iomem *);
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void (*mv_writeb)(u8, void __iomem *);
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void (*mv_writew)(u16, void __iomem *);
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void (*mv_writel)(u32, void __iomem *);
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int (*mv_irq_demux)(int irq);
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void (*mv_init_irq)(void);
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@ -19,12 +19,12 @@
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* Copy data from IO memory space to "real" memory space.
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* This needs to be optimized.
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*/
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void memcpy_fromio(void *to, volatile void __iomem *from, unsigned long count)
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void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count)
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{
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char *p = to;
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unsigned char *p = to;
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while (count) {
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count--;
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*p = readb((void __iomem *)from);
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*p = readb(from);
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p++;
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from++;
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}
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@ -37,10 +37,10 @@ EXPORT_SYMBOL(memcpy_fromio);
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*/
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void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count)
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{
|
||||
const char *p = from;
|
||||
const unsigned char *p = from;
|
||||
while (count) {
|
||||
count--;
|
||||
writeb(*p, (void __iomem *)to);
|
||||
writeb(*p, to);
|
||||
p++;
|
||||
to++;
|
||||
}
|
||||
|
|
@ -55,7 +55,7 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
|
|||
{
|
||||
while (count) {
|
||||
count--;
|
||||
writeb(c, (void __iomem *)dst);
|
||||
writeb(c, dst);
|
||||
dst++;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,38 +19,33 @@
|
|||
/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
|
||||
* workaround. */
|
||||
/* I'm not sure SH7709 has this kind of bug */
|
||||
#define dummy_read() ctrl_inb(0xba000000)
|
||||
#define dummy_read() __raw_readb(0xba000000)
|
||||
#else
|
||||
#define dummy_read()
|
||||
#endif
|
||||
|
||||
unsigned long generic_io_base;
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
ctrl_inw(0xa0000000);
|
||||
}
|
||||
|
||||
u8 generic_inb(unsigned long port)
|
||||
{
|
||||
return ctrl_inb((unsigned long __force)__ioport_map(port, 1));
|
||||
return __raw_readb(__ioport_map(port, 1));
|
||||
}
|
||||
|
||||
u16 generic_inw(unsigned long port)
|
||||
{
|
||||
return ctrl_inw((unsigned long __force)__ioport_map(port, 2));
|
||||
return __raw_readw(__ioport_map(port, 2));
|
||||
}
|
||||
|
||||
u32 generic_inl(unsigned long port)
|
||||
{
|
||||
return ctrl_inl((unsigned long __force)__ioport_map(port, 4));
|
||||
return __raw_readl(__ioport_map(port, 4));
|
||||
}
|
||||
|
||||
u8 generic_inb_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = generic_inb(port);
|
||||
|
||||
delay();
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
|
|
@ -58,7 +53,7 @@ u16 generic_inw_p(unsigned long port)
|
|||
{
|
||||
unsigned long v = generic_inw(port);
|
||||
|
||||
delay();
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
|
|
@ -66,7 +61,7 @@ u32 generic_inl_p(unsigned long port)
|
|||
{
|
||||
unsigned long v = generic_inl(port);
|
||||
|
||||
delay();
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
|
|
@ -112,35 +107,35 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
|
|||
|
||||
void generic_outb(u8 b, unsigned long port)
|
||||
{
|
||||
ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1));
|
||||
__raw_writeb(b, __ioport_map(port, 1));
|
||||
}
|
||||
|
||||
void generic_outw(u16 b, unsigned long port)
|
||||
{
|
||||
ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2));
|
||||
__raw_writew(b, __ioport_map(port, 2));
|
||||
}
|
||||
|
||||
void generic_outl(u32 b, unsigned long port)
|
||||
{
|
||||
ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4));
|
||||
__raw_writel(b, __ioport_map(port, 4));
|
||||
}
|
||||
|
||||
void generic_outb_p(u8 b, unsigned long port)
|
||||
{
|
||||
generic_outb(b, port);
|
||||
delay();
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
void generic_outw_p(u16 b, unsigned long port)
|
||||
{
|
||||
generic_outw(b, port);
|
||||
delay();
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
void generic_outl_p(u32 b, unsigned long port)
|
||||
{
|
||||
generic_outl(b, port);
|
||||
delay();
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -184,36 +179,6 @@ void generic_outsl(unsigned long port, const void *src, unsigned long count)
|
|||
dummy_read();
|
||||
}
|
||||
|
||||
u8 generic_readb(void __iomem *addr)
|
||||
{
|
||||
return ctrl_inb((unsigned long __force)addr);
|
||||
}
|
||||
|
||||
u16 generic_readw(void __iomem *addr)
|
||||
{
|
||||
return ctrl_inw((unsigned long __force)addr);
|
||||
}
|
||||
|
||||
u32 generic_readl(void __iomem *addr)
|
||||
{
|
||||
return ctrl_inl((unsigned long __force)addr);
|
||||
}
|
||||
|
||||
void generic_writeb(u8 b, void __iomem *addr)
|
||||
{
|
||||
ctrl_outb(b, (unsigned long __force)addr);
|
||||
}
|
||||
|
||||
void generic_writew(u16 b, void __iomem *addr)
|
||||
{
|
||||
ctrl_outw(b, (unsigned long __force)addr);
|
||||
}
|
||||
|
||||
void generic_writel(u32 b, void __iomem *addr)
|
||||
{
|
||||
ctrl_outl(b, (unsigned long __force)addr);
|
||||
}
|
||||
|
||||
void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
|
||||
{
|
||||
return (void __iomem *)(addr + generic_io_base);
|
||||
|
|
|
|||
|
|
@ -126,9 +126,6 @@ void __init sh_mv_setup(void)
|
|||
mv_set(insb); mv_set(insw); mv_set(insl);
|
||||
mv_set(outsb); mv_set(outsw); mv_set(outsl);
|
||||
|
||||
mv_set(readb); mv_set(readw); mv_set(readl);
|
||||
mv_set(writeb); mv_set(writew); mv_set(writel);
|
||||
|
||||
mv_set(ioport_map);
|
||||
mv_set(ioport_unmap);
|
||||
mv_set(irq_demux);
|
||||
|
|
|
|||
Loading…
Reference in New Issue