mirror of https://gitee.com/openkylin/linux.git
dt-bindings: tegra: Changes for v5.1-rc1
This contains device tree binding updates for CPU frequency scaling on Tegra210, BPMP support on Tegra210 and support for NVIDIA Shield TV. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmAITHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoRH5D/9mL1momHpLBgEVPpMS5L6UWlgzLHUj Ji69q4U2d2KYIclxVD2J8aCc9pmWI+tR0MIUmf1d60NgJfXwC41T9aVndw1yDwQ2 LFOLW05hcISTghPvP2kFAPh/bkYFcDOlKHAk2mc8ITWgOpJWXhP3iLwKmDsLKkg9 +nZjoJjZD6DP618Nqu2SzeFClHWjcS+x1PxuZ6e6iQyMgCyp6JDEGArclVx6mAi6 CnBJjsyHNFUvQ+PkgVW5y+pMVfrs1Q5iUvLGD5Nqi1RniqI9m1j5PZDb6vDUeoX5 l3O5SxwTf+x3FhqBf//AoQlUdzVVRILR23ncgc9G9513lSQX6ruodB0C0tvuRKoC l5Wc3+S3obVNMyF2SZVYkdaqCzids8K8TbK576c8brQ5/Gn7JSAhYm0Cxc5Yw5qd SBj3Ubw337BEsfpI8gntMwgOaXPpD6OqQ+2Tybz5cnYtPcLxJicN1qJMm6zxOx0y 9MknaynXdOMEy3Od5KaHQHPcwOYx3+883thM5VB+2pzD2OapTL36AwxcT/5qwy/X TjcHNOj+mIpxZ40W5yJf0u0kq2JuQNh2MsvW93cXA6XB+GDu3qps6PqD4gk/nVhY elsC+XGFxV+7J5eMSVeJrCsd9eSxkDlFdmvh/AJ/1+jxOsiLYutamjG0JpmML0Rl +RZcMO5ZZNJXIQ== =CP31 -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: tegra: Changes for v5.1-rc1 This contains device tree binding updates for CPU frequency scaling on Tegra210, BPMP support on Tegra210 and support for NVIDIA Shield TV. * tag 'tegra-for-5.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties dt-bindings: clock: tegra124-dfll: add Tegra210 support dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator dt-bindings: firmware: tegra186-bpmp: Remove name property dt-bindings: firmware: Add bindings for Tegra210 BPMP dt-bindings: tegra: Add Shield TV device tree binding documentation Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
14ab4f4330
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@ -87,9 +87,11 @@ properties:
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- const: nvidia,tegra124
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- items:
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- enum:
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- nvidia,darcy
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- nvidia,p2371-0000
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- nvidia,p2371-2180
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- nvidia,p2571
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- nvidia,p2894-0050-a08
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- const: nvidia,tegra210
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- items:
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- enum:
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@ -8,10 +8,11 @@ the fast CPU cluster. It consists of a free-running voltage controlled
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oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
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control module that will automatically adjust the VDD_CPU voltage by
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communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
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Currently only the I2C mode is supported by these bindings.
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Required properties:
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- compatible : should be "nvidia,tegra124-dfll"
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- compatible : should be one of:
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- "nvidia,tegra124-dfll": for Tegra124
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- "nvidia,tegra210-dfll": for Tegra210
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- reg : Defines the following set of registers, in the order listed:
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- registers for the DFLL control logic.
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- registers for the I2C output logic.
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@ -45,10 +46,31 @@ Required properties for the control loop parameters:
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Optional properties for the control loop parameters:
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- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
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Optional properties for mode selection:
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- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
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Required properties for I2C mode:
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- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
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Example:
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Required properties for PWM mode:
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- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
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- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
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control is disabled and the PWM output is tristated. Note that this voltage is
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configured in hardware, typically via a resistor divider.
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- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
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is enabled and PWM output is low. Hence, this is the minimum output voltage
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that the regulator supports when PWM control is enabled.
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- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
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corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
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duty cycle would be: nvidia,pwm-min-microvolts +
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nvidia,pwm-voltage-step-microvolts * 2.
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- pinctrl-0: I/O pad configuration when PWM control is enabled.
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- pinctrl-1: I/O pad configuration when PWM control is disabled.
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- pinctrl-names: must include the following entries:
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- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
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- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
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Example for I2C:
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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@ -76,3 +98,58 @@ clock@70110000 {
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nvidia,i2c-fs-rate = <400000>;
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};
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Example for PWM:
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
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<&tegra_car TEGRA210_CLK_DFLL_REF>,
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<&tegra_car TEGRA124_CLK_I2C5>;;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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nvidia,sample-rate = <25000>;
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
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nvidia,cf = <6>;
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nvidia,ci = <0>;
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nvidia,cg = <2>;
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nvidia,pwm-min-microvolts = <708000>; /* 708mV */
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nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
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nvidia,pwm-to-pmic;
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nvidia,pwm-tristate-microvolts = <1000000>;
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nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
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pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
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pinctrl-0 = <&dvfs_pwm_active_state>;
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pinctrl-1 = <&dvfs_pwm_inactive_state>;
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};
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/* pinmux nodes added for completeness. Binding doc can be found in:
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* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
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*/
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pinmux: pinmux@700008d4 {
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dvfs_pwm_active_state: dvfs_pwm_active {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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};
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dvfs_pwm_inactive_state: dvfs_pwm_inactive {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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@ -9,11 +9,9 @@ Required properties:
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- cpu_g: Clock mux for the fast CPU cluster.
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- cpu_lp: Clock mux for the low-power CPU cluster.
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- pll_x: Fast PLL clocksource.
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- pll_p: Auxiliary PLL used during fast PLL rate changes.
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- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
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- vdd-cpu-supply: Regulator for CPU voltage
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Optional properties:
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- clock-latency: Specify the possible maximum transition latency for clock,
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@ -31,13 +29,11 @@ cpus {
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reg = <0>;
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clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
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<&tegra_car TEGRA124_CLK_CCLK_LP>,
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<&tegra_car TEGRA124_CLK_PLL_X>,
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<&tegra_car TEGRA124_CLK_PLL_P>,
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<&dfll>;
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clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
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clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
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clock-latency = <300000>;
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vdd-cpu-supply: <&vdd_cpu>;
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};
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<...>
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@ -8,7 +8,6 @@ which can create the interprocessor communication (IPC) between the CPU
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and BPMP.
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Required properties:
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- name : Should be bpmp
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- compatible
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Array of strings
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One of:
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@ -0,0 +1,35 @@
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NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
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The Boot and Power Management Processor (BPMP) is a co-processor found
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in Tegra210 SoC. It is designed to handle the early stages of the boot
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process as well as to assisting in entering deep low power state
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(suspend to ram), and also offloading DRAM memory clock scaling on
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some platforms. The binding document defines the resources that would
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be used by the BPMP T210 firmware driver, which can create the
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interprocessor communication (IPC) between the CPU and BPMP.
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Required properties:
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- compatible
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Array of strings
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One of:
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- "nvidia,tegra210-bpmp"
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- reg: physical base address and length for HW synchornization primitives
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1) base address and length to Tegra 'atomics' hardware
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2) base address and length to Tegra 'semaphore' hardware
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- interrupts: specifies the interrupt number for receiving messages ("rx")
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and for triggering messages ("tx")
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Optional properties:
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- #clock-cells : Should be 1 for platforms where DRAM clock control is
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offloaded to bpmp.
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Example:
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bpmp@70016000 {
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compatible = "nvidia,tegra210-bpmp";
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reg = <0x0 0x70016000 0x0 0x2000
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0x0 0x60001000 0x0 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "tx", "rx";
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};
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