mirror of https://gitee.com/openkylin/linux.git
phy: qcom-qmp: Add support for SM6115 UFS phy
Add the tables and constants for init sequences for UFS QMP phy found in SM4250/6115 SoC. The phy is a variation of the v2 phy, but is mistakenly labeled as v3-660 in downstream sources. QSERDES COM, RX, TX registers match fully existing v2 registers, with a few additions. PCS registers don't have much in common, but there are no clashes with existing ones so new registers were added to existing v2 PCS pack. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210821155657.893165-3-iskren.chernev@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Iskren Chernev
Vinod Koul
parent
80f652c266
commit
152a810eae
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@ -234,6 +234,11 @@ static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_PCS_READY_STATUS] = 0x160,
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};
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static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = 0x00,
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[QPHY_PCS_READY_STATUS] = 0x168,
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};
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static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x44,
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@ -1329,6 +1334,97 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
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};
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static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
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/* Rate B */
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
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};
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static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
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QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
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};
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static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
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};
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static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
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QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
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QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
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QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
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QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
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QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
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QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
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};
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static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
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@ -3396,6 +3492,31 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
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.no_pcs_sw_reset = true,
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};
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static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
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.type = PHY_TYPE_UFS,
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.nlanes = 1,
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.serdes_tbl = sm6115_ufsphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
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.tx_tbl = sm6115_ufsphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
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.rx_tbl = sm6115_ufsphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
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.pcs_tbl = sm6115_ufsphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm6115_ufsphy_regs_layout,
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.start_ctrl = SERDES_START,
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.pwrdn_ctrl = SW_PWRDN,
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.is_dual_lane_phy = false,
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.no_pcs_sw_reset = true,
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};
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static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
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.type = PHY_TYPE_PCIE,
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.nlanes = 1,
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@ -5444,6 +5565,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,msm8998-qmp-usb3-phy",
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.data = &msm8998_usb3phy_cfg,
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}, {
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.compatible = "qcom,sm6115-qmp-ufs-phy",
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.data = &sm6115_ufsphy_cfg,
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}, {
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.compatible = "qcom,sm8150-qmp-ufs-phy",
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.data = &sm8150_ufsphy_cfg,
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@ -191,6 +191,8 @@
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#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
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#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
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#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
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#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
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#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
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#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
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#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
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#define QSERDES_COM_BG_CTRL 0x170
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@ -220,6 +222,10 @@
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/* Only for QMP V2 PHY - RX registers */
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#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
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#define QSERDES_RX_UCDR_SO_GAIN 0x01c
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#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
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#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
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#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
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#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
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#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
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#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
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#define QSERDES_RX_RX_TERM_BW 0x090
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@ -243,6 +249,10 @@
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#define QPHY_POWER_DOWN_CONTROL 0x04
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#define QPHY_TXDEEMPH_M6DB_V0 0x24
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#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
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#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34
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#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38
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#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c
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#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40
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#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
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#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
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#define QPHY_POWER_STATE_CONFIG1 0x60
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@ -253,6 +263,11 @@
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#define QPHY_LOCK_DETECT_CONFIG3 0x88
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#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
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#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
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#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
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#define QPHY_RX_SYM_RESYNC_CTRL 0x13c
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#define QPHY_RX_MIN_HIBERN8_TIME 0x140
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#define QPHY_RX_SIGDET_CTRL2 0x148
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#define QPHY_RX_PWM_GEAR_BAND 0x154
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#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
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#define QPHY_OSC_DTCT_ACTIONS 0x1AC
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#define QPHY_RX_SIGDET_LVL 0x1D8
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@ -280,6 +295,8 @@
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#define QSERDES_V3_COM_SSC_PER2 0x020
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#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
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#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
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#define QSERDES_V3_COM_POST_DIV 0x02c
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#define QSERDES_V3_COM_POST_DIV_MUX 0x030
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#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
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# define QSERDES_V3_COM_BIAS_EN 0x0001
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# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
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@ -291,6 +308,7 @@
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#define QSERDES_V3_COM_CLK_ENABLE1 0x038
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#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
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#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
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#define QSERDES_V3_COM_PLL_EN 0x044
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#define QSERDES_V3_COM_PLL_IVCO 0x048
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#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
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#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
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