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drm/amd/powerplay: revise caching the soft pptable and add it's size 

This fixes a bug in the pptable access interface that could lead to
a crash.  Check the pointer before using it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang 2016-04-15 15:02:54 -04:00 committed by Alex Deucher
parent 5632708f44
commit 1551019523
2 changed files with 9 additions and 5 deletions
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9
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
View File

@ -138,12 +138,15 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
u16 size;
u8 frev, crev;
void *table_address;
void *table_address = (void *)hwmgr->soft_pp_table;
if (!table_address) {
table_address = (ATOM_Tonga_POWERPLAYTABLE *)
cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev);
cgs_atom_get_data_table(hwmgr->device,
index, &size, &frev, &crev);
hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
hwmgr->soft_pp_table_size = size;
}
return table_address;
}

1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View File

@ -577,6 +577,7 @@ struct pp_hwmgr {
void *device;
struct pp_smumgr *smumgr;
const void *soft_pp_table;
uint32_t soft_pp_table_size;
bool need_pp_table_upload;
enum amd_dpm_forced_level dpm_level;
bool block_hw_access;