mirror of https://gitee.com/openkylin/linux.git
clk: exynos4: Add missing CMU_TOP and ISP clocks
The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Andrzej Hajda
Kukjin Kim
parent
8e1ce8393e
commit
1554701528
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@ -98,6 +98,10 @@ Exynos4 SoC and this is specified where applicable.
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sclk_mfc 170
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sclk_pcm0 171
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sclk_g3d 172
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sclk_pwm_isp 173 Exynos4x12
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sclk_spi0_isp 174 Exynos4x12
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sclk_spi1_isp 175 Exynos4x12
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sclk_uart_isp 176 Exynos4x12
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[Peripheral Clock Gates]
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@ -205,6 +209,32 @@ Exynos4 SoC and this is specified where applicable.
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fimc_lite1 354 Exynos4x12
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ppmuispx 355 Exynos4x12
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ppmuispmx 356 Exynos4x12
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fimc_isp 357 Exynos4x12
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fimc_drc 358 Exynos4x12
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fimc_fd 359 Exynos4x12
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mcuisp 360 Exynos4x12
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gicisp 361 Exynos4x12
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smmu_isp 362 Exynos4x12
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smmu_drc 363 Exynos4x12
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smmu_fd 364 Exynos4x12
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smmu_lite0 365 Exynos4x12
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smmu_lite1 366 Exynos4x12
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mcuctl_isp 367 Exynos4x12
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mpwm_isp 368 Exynos4x12
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i2c0_isp 369 Exynos4x12
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i2c1_isp 370 Exynos4x12
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mtcadc_isp 371 Exynos4x12
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pwm_isp 372 Exynos4x12
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wdt_isp 373 Exynos4x12
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uart_isp 374 Exynos4x12
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asyncaxim 375 Exynos4x12
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smmu_ispcx 376 Exynos4x12
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spi0_isp 377 Exynos4x12
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spi1_isp 378 Exynos4x12
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pwm_isp_sclk 379 Exynos4x12
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spi0_isp_sclk 380 Exynos4x12
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spi1_isp_sclk 381 Exynos4x12
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uart_isp_sclk 382 Exynos4x12
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[Mux Clocks]
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@ -34,6 +34,7 @@
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#define E4210_SRC_IMAGE 0xc230
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#define SRC_LCD0 0xc234
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#define SRC_LCD1 0xc238
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#define E4X12_SRC_ISP 0xc238
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#define SRC_MAUDIO 0xc23c
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#define SRC_FSYS 0xc240
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#define SRC_PERIL0 0xc250
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@ -43,6 +44,7 @@
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#define SRC_MASK_TV 0xc324
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#define SRC_MASK_LCD0 0xc334
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#define SRC_MASK_LCD1 0xc338
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#define E4X12_SRC_MASK_ISP 0xc338
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#define SRC_MASK_MAUDIO 0xc33c
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#define SRC_MASK_FSYS 0xc340
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#define SRC_MASK_PERIL0 0xc350
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@ -76,6 +78,7 @@
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#define E4210_GATE_IP_IMAGE 0xc930
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#define GATE_IP_LCD0 0xc934
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#define GATE_IP_LCD1 0xc938
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#define E4X12_GATE_IP_ISP 0xc938
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#define E4X12_GATE_IP_MAUDIO 0xc93c
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#define GATE_IP_FSYS 0xc940
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#define GATE_IP_GPS 0xc94c
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@ -87,7 +90,10 @@
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#define E4210_MPLL_CON0 0x14108
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#define SRC_CPU 0x14200
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#define DIV_CPU0 0x14500
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#define E4X12_DIV_ISP0 0x18300
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#define E4X12_DIV_ISP1 0x18304
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#define E4X12_GATE_ISP0 0x18800
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#define E4X12_GATE_ISP1 0x18804
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/* the exynos4 soc type */
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enum exynos4_soc {
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@ -124,7 +130,8 @@ enum exynos4_clks {
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sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
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sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
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sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
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sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
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sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
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sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
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/* gate clocks */
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fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
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@ -138,7 +145,11 @@ enum exynos4_clks {
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spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
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spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
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audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
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fimc_lite1, ppmuispx, ppmuispmx,
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fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
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gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
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mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
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asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
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spi1_isp_sclk, uart_isp_sclk,
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/* mux clocks */
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mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
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@ -234,6 +245,8 @@ PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
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PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
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PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
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"spdif_extclk", };
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PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
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PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
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/* Exynos 4210-specific parent groups */
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PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
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@ -271,6 +284,9 @@ PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
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"sclk_usbphy0", "xxti", "xusbxti",
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"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
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PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
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PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
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PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
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PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
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/* fixed rate clocks generated outside the soc */
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struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
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@ -301,7 +317,9 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
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MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
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CLK_SET_RATE_PARENT, 0),
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MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
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MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
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MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
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MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
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};
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/* list of mux clocks supported in exynos4210 soc */
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@ -358,8 +376,15 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
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struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
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MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
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SRC_CPU, 24, 1),
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MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
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MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
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MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
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SRC_TOP1, 12, 1),
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MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
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SRC_TOP1, 16, 1),
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MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
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MUX(none, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
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SRC_TOP1, 24, 1),
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MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
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MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
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MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
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@ -405,6 +430,10 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
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MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
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MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
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MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
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MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
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MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
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MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
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MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
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};
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/* list of divider clocks supported in all exynos4 soc's */
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@ -431,10 +460,10 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
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DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
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DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
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DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
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DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
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DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
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DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
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DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
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DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
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DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
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DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
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DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
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@ -472,6 +501,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
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/* list of divider clocks supported in exynos4210 soc */
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struct samsung_div_clock exynos4210_div_clks[] __initdata = {
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DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
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DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
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DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
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DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
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@ -487,6 +517,20 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
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DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
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DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
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DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
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DIV(none, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
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DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
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DIV(none, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", DIV_TOP, 24, 3),
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DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
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DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
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DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
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DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
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DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
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DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
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DIV(none, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
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DIV(none, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
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DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
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DIV(none, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
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DIV(none, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
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};
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/* list of gate clocks supported in all exynos4 soc's */
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@ -730,20 +774,80 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
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GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
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GATE_A(keyif, "keyif", "aclk100",
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E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
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GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
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E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
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GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
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E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
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GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
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E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
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GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
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E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
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GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
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E4X12_GATE_IP_ISP, 0, 0, 0),
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GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
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E4X12_GATE_IP_ISP, 1, 0, 0),
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GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
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E4X12_GATE_IP_ISP, 2, 0, 0),
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GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
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E4X12_GATE_IP_ISP, 3, 0, 0),
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GATE_A(wdt, "watchdog", "aclk100",
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E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
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GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
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E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
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GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
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E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
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GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
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CLK_IGNORE_UNUSED, 0),
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GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
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CLK_IGNORE_UNUSED, 0),
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GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
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CLK_IGNORE_UNUSED, 0),
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GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
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CLK_IGNORE_UNUSED, 0),
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GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
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CLK_IGNORE_UNUSED, 0),
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GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
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CLK_IGNORE_UNUSED, 0),
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GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
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CLK_IGNORE_UNUSED, 0),
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GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
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CLK_IGNORE_UNUSED, 0),
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GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
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CLK_IGNORE_UNUSED, 0),
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GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
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CLK_IGNORE_UNUSED, 0),
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GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
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CLK_IGNORE_UNUSED, 0),
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GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
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CLK_IGNORE_UNUSED, 0),
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GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
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CLK_IGNORE_UNUSED, 0),
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GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
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CLK_IGNORE_UNUSED, 0),
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GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
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CLK_IGNORE_UNUSED, 0),
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GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
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CLK_IGNORE_UNUSED, 0),
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GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
|
|
|||
Loading…
Reference in New Issue