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net: phy: Add Cortina CS4340 driver
Add basic support for Cortina PHY drivers. Support only CS4340 for now. The phys are not compatible with IEEE 802.3 clause 22/45 registers. Implement proper read_status support. The generic 10G phy driver causes bus register access errors. The driver should be described using the "ethernet-phy-id" device tree compatible. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -234,6 +234,11 @@ config CICADA_PHY
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---help---
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Currently supports the cis8204
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config CORTINA_PHY
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tristate "Cortina EDC CDR 10G Ethernet PHY"
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---help---
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Currently supports the CS4340 phy.
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config DAVICOM_PHY
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tristate "Davicom PHYs"
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---help---
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@ -46,6 +46,7 @@ obj-$(CONFIG_BCM_CYGNUS_PHY) += bcm-cygnus.o
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obj-$(CONFIG_BCM_NET_PHYLIB) += bcm-phy-lib.o
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obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
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obj-$(CONFIG_CICADA_PHY) += cicada.o
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obj-$(CONFIG_CORTINA_PHY) += cortina.o
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obj-$(CONFIG_DAVICOM_PHY) += davicom.o
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obj-$(CONFIG_DP83640_PHY) += dp83640.o
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obj-$(CONFIG_DP83848_PHY) += dp83848.o
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@ -0,0 +1,118 @@
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/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* CORTINA is a registered trademark of Cortina Systems, Inc.
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*
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#define PHY_ID_CS4340 0x13e51002
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#define VILLA_GLOBAL_CHIP_ID_LSB 0x0
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#define VILLA_GLOBAL_CHIP_ID_MSB 0x1
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#define VILLA_GLOBAL_GPIO_1_INTS 0x017
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static int cortina_read_reg(struct phy_device *phydev, u16 regnum)
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{
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return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
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MII_ADDR_C45 | regnum);
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}
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static int cortina_config_aneg(struct phy_device *phydev)
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{
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phydev->supported = SUPPORTED_10000baseT_Full;
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phydev->advertising = SUPPORTED_10000baseT_Full;
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return 0;
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}
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static int cortina_read_status(struct phy_device *phydev)
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{
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int gpio_int_status, ret = 0;
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gpio_int_status = cortina_read_reg(phydev, VILLA_GLOBAL_GPIO_1_INTS);
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if (gpio_int_status < 0) {
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ret = gpio_int_status;
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goto err;
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}
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if (gpio_int_status & 0x8) {
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/* up when edc_convergedS set */
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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phydev->link = 1;
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} else {
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phydev->link = 0;
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}
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err:
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return ret;
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}
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static int cortina_soft_reset(struct phy_device *phydev)
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{
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return 0;
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}
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static int cortina_probe(struct phy_device *phydev)
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{
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u32 phy_id = 0;
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int id_lsb = 0, id_msb = 0;
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/* Read device id from phy registers. */
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id_lsb = cortina_read_reg(phydev, VILLA_GLOBAL_CHIP_ID_LSB);
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if (id_lsb < 0)
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return -ENXIO;
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phy_id = id_lsb << 16;
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id_msb = cortina_read_reg(phydev, VILLA_GLOBAL_CHIP_ID_MSB);
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if (id_msb < 0)
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return -ENXIO;
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phy_id |= id_msb;
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/* Make sure the device tree binding matched the driver with the
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* right device.
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*/
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if (phy_id != phydev->drv->phy_id) {
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phydev_err(phydev, "Error matching phy with %s driver\n",
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phydev->drv->name);
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return -ENODEV;
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}
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return 0;
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}
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static struct phy_driver cortina_driver[] = {
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{
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.phy_id = PHY_ID_CS4340,
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.phy_id_mask = 0xffffffff,
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.name = "Cortina CS4340",
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.config_aneg = cortina_config_aneg,
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.read_status = cortina_read_status,
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.soft_reset = cortina_soft_reset,
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.probe = cortina_probe,
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},
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};
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module_phy_driver(cortina_driver);
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static struct mdio_device_id __maybe_unused cortina_tbl[] = {
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{ PHY_ID_CS4340, 0xffffffff},
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{},
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};
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MODULE_DEVICE_TABLE(mdio, cortina_tbl);
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