mirror of https://gitee.com/openkylin/linux.git
KVM: Portability: Move kvm_get/set_msr[_common] to x86.c
This patch moves the implementation of the functions of kvm_get/set_msr, kvm_get/set_msr_common, and set_efer from kvm_main.c to x86.c. The definition of EFER_RESERVED_BITS is moved too. Signed-off-by: Carsten Otte <cotte@de.ibm.com> Acked-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
This commit is contained in:
Carsten Otte
Avi Kivity
parent
aab61cc0d2
commit
15c4a6406f
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@ -90,8 +90,6 @@ static struct kvm_stats_debugfs_item {
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static struct dentry *debugfs_dir;
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#define EFER_RESERVED_BITS 0xfffffffffffff2fe
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static long kvm_vcpu_ioctl(struct file *file, unsigned int ioctl,
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unsigned long arg);
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@ -1356,137 +1354,6 @@ void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
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}
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}
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int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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{
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u64 data;
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switch (msr) {
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case 0xc0010010: /* SYSCFG */
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case 0xc0010015: /* HWCR */
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case MSR_IA32_PLATFORM_ID:
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case MSR_IA32_P5_MC_ADDR:
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case MSR_IA32_P5_MC_TYPE:
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case MSR_IA32_MC0_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MCG_CAP:
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case MSR_IA32_MC0_MISC:
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case MSR_IA32_MC0_MISC+4:
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case MSR_IA32_MC0_MISC+8:
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case MSR_IA32_MC0_MISC+12:
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case MSR_IA32_MC0_MISC+16:
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case MSR_IA32_UCODE_REV:
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case MSR_IA32_PERF_STATUS:
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case MSR_IA32_EBL_CR_POWERON:
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/* MTRR registers */
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case 0xfe:
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case 0x200 ... 0x2ff:
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data = 0;
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break;
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case 0xcd: /* fsb frequency */
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data = 3;
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break;
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case MSR_IA32_APICBASE:
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data = kvm_get_apic_base(vcpu);
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break;
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case MSR_IA32_MISC_ENABLE:
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data = vcpu->ia32_misc_enable_msr;
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break;
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#ifdef CONFIG_X86_64
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case MSR_EFER:
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data = vcpu->shadow_efer;
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break;
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#endif
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default:
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pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
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return 1;
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}
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*pdata = data;
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_get_msr_common);
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/*
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* Reads an msr value (of 'msr_index') into 'pdata'.
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* Returns 0 on success, non-0 otherwise.
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* Assumes vcpu_load() was already called.
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*/
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int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
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{
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return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
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}
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#ifdef CONFIG_X86_64
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static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
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{
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if (efer & EFER_RESERVED_BITS) {
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printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
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efer);
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inject_gp(vcpu);
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return;
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}
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if (is_paging(vcpu)
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&& (vcpu->shadow_efer & EFER_LME) != (efer & EFER_LME)) {
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printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
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inject_gp(vcpu);
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return;
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}
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kvm_x86_ops->set_efer(vcpu, efer);
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efer &= ~EFER_LMA;
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efer |= vcpu->shadow_efer & EFER_LMA;
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vcpu->shadow_efer = efer;
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}
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#endif
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int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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switch (msr) {
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#ifdef CONFIG_X86_64
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case MSR_EFER:
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set_efer(vcpu, data);
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break;
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#endif
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case MSR_IA32_MC0_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
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__FUNCTION__, data);
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break;
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case MSR_IA32_MCG_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
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__FUNCTION__, data);
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break;
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case MSR_IA32_UCODE_REV:
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case MSR_IA32_UCODE_WRITE:
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case 0x200 ... 0x2ff: /* MTRRs */
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break;
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case MSR_IA32_APICBASE:
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kvm_set_apic_base(vcpu, data);
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break;
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case MSR_IA32_MISC_ENABLE:
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vcpu->ia32_misc_enable_msr = data;
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break;
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default:
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pr_unimpl(vcpu, "unhandled wrmsr: 0x%x\n", msr);
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_set_msr_common);
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/*
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* Writes msr value into into the appropriate "register".
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* Returns 0 on success, non-0 otherwise.
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* Assumes vcpu_load() was already called.
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*/
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int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
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{
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return kvm_x86_ops->set_msr(vcpu, msr_index, data);
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}
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void kvm_resched(struct kvm_vcpu *vcpu)
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{
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if (!need_resched())
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@ -38,6 +38,7 @@
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| X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
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#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
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#define EFER_RESERVED_BITS 0xfffffffffffff2fe
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unsigned long segment_base(u16 selector)
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{
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@ -324,6 +325,44 @@ static u32 emulated_msrs[] = {
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MSR_IA32_MISC_ENABLE,
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};
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#ifdef CONFIG_X86_64
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static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
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{
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if (efer & EFER_RESERVED_BITS) {
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printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
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efer);
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inject_gp(vcpu);
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return;
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}
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if (is_paging(vcpu)
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&& (vcpu->shadow_efer & EFER_LME) != (efer & EFER_LME)) {
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printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
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inject_gp(vcpu);
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return;
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}
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kvm_x86_ops->set_efer(vcpu, efer);
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efer &= ~EFER_LMA;
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efer |= vcpu->shadow_efer & EFER_LMA;
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vcpu->shadow_efer = efer;
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}
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#endif
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/*
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* Writes msr value into into the appropriate "register".
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* Returns 0 on success, non-0 otherwise.
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* Assumes vcpu_load() was already called.
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*/
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int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
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{
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return kvm_x86_ops->set_msr(vcpu, msr_index, data);
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}
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/*
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* Adapt set_msr() to msr_io()'s calling convention
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*/
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@ -332,6 +371,101 @@ static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
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return kvm_set_msr(vcpu, index, *data);
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}
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int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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switch (msr) {
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#ifdef CONFIG_X86_64
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case MSR_EFER:
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set_efer(vcpu, data);
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break;
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#endif
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case MSR_IA32_MC0_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
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__FUNCTION__, data);
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break;
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case MSR_IA32_MCG_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
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__FUNCTION__, data);
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break;
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case MSR_IA32_UCODE_REV:
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case MSR_IA32_UCODE_WRITE:
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case 0x200 ... 0x2ff: /* MTRRs */
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break;
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case MSR_IA32_APICBASE:
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kvm_set_apic_base(vcpu, data);
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break;
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case MSR_IA32_MISC_ENABLE:
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vcpu->ia32_misc_enable_msr = data;
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break;
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default:
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pr_unimpl(vcpu, "unhandled wrmsr: 0x%x\n", msr);
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_set_msr_common);
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/*
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* Reads an msr value (of 'msr_index') into 'pdata'.
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* Returns 0 on success, non-0 otherwise.
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* Assumes vcpu_load() was already called.
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*/
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int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
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{
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return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
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}
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int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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{
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u64 data;
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switch (msr) {
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case 0xc0010010: /* SYSCFG */
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case 0xc0010015: /* HWCR */
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case MSR_IA32_PLATFORM_ID:
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case MSR_IA32_P5_MC_ADDR:
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case MSR_IA32_P5_MC_TYPE:
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case MSR_IA32_MC0_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MCG_CAP:
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case MSR_IA32_MC0_MISC:
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case MSR_IA32_MC0_MISC+4:
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case MSR_IA32_MC0_MISC+8:
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case MSR_IA32_MC0_MISC+12:
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case MSR_IA32_MC0_MISC+16:
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case MSR_IA32_UCODE_REV:
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case MSR_IA32_PERF_STATUS:
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case MSR_IA32_EBL_CR_POWERON:
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/* MTRR registers */
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case 0xfe:
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case 0x200 ... 0x2ff:
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data = 0;
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break;
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case 0xcd: /* fsb frequency */
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data = 3;
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break;
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case MSR_IA32_APICBASE:
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data = kvm_get_apic_base(vcpu);
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break;
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case MSR_IA32_MISC_ENABLE:
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data = vcpu->ia32_misc_enable_msr;
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break;
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#ifdef CONFIG_X86_64
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case MSR_EFER:
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data = vcpu->shadow_efer;
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break;
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#endif
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default:
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pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
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return 1;
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}
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*pdata = data;
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_get_msr_common);
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/*
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* Read or write a bunch of msrs. All parameters are kernel addresses.
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*
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