mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: Update initvals for AR9462
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith Manoharan
John W. Linville
parent
15d2b58577
commit
16329ff029
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@ -37,28 +37,28 @@ static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18253ede},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0003580c},
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{0x00018c08, 0x0003780c},
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};
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static const u32 ar9462_2p0_baseband_postamble[][5] = {
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/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
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{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
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{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae},
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{0x00009824, 0x5ac640de, 0x5ac640d0, 0x5ac640d0, 0x63c640da},
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{0x00009824, 0x63c640de, 0x5ac640d0, 0x5ac640d0, 0x63c640da},
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{0x00009828, 0x0796be89, 0x0696b081, 0x0696b881, 0x09143e81},
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{0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
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{0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
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{0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
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{0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
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{0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a2},
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{0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
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{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8},
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{0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e},
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{0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3376605e, 0x32395d5e},
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{0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
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{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
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{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
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{0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
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{0x00009e3c, 0xcf946222, 0xcf946222, 0xcfd5c782, 0xcfd5c282},
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{0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
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{0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
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{0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
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{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
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@ -82,9 +82,9 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
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{0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
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{0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
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{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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{0x0000a3a4, 0x00000010, 0x00000010, 0x00000000, 0x00000000},
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{0x0000a3a4, 0x00000050, 0x00000050, 0x00000000, 0x00000000},
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{0x0000a3a8, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa},
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{0x0000a3ac, 0xaaaaaa00, 0xaaaaaa30, 0xaaaaaa00, 0xaaaaaa00},
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{0x0000a3ac, 0xaaaaaa00, 0xaa30aa30, 0xaaaaaa00, 0xaaaaaa00},
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{0x0000a41c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
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{0x0000a420, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce},
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{0x0000a424, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
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@ -363,14 +363,14 @@ static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18213ede},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0003580c},
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{0x00018c08, 0x0003780c},
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};
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static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18212ede},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0003580c},
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{0x00018c08, 0x0003780c},
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};
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static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
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@ -775,7 +775,7 @@ static const u32 ar9462_2p0_baseband_core[][2] = {
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{0x00009fc0, 0x803e4788},
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{0x00009fc4, 0x0001efb5},
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{0x00009fcc, 0x40000014},
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{0x00009fd0, 0x01193b93},
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{0x00009fd0, 0x0a193b93},
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{0x0000a20c, 0x00000000},
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{0x0000a220, 0x00000000},
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{0x0000a224, 0x00000000},
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@ -850,7 +850,7 @@ static const u32 ar9462_2p0_baseband_core[][2] = {
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{0x0000a7cc, 0x00000000},
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{0x0000a7d0, 0x00000000},
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{0x0000a7d4, 0x00000004},
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{0x0000a7dc, 0x00000001},
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{0x0000a7dc, 0x00000000},
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{0x0000a7f0, 0x80000000},
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{0x0000a8d0, 0x004b6a8e},
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{0x0000a8d4, 0x00000820},
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@ -886,7 +886,7 @@ static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
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{0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
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{0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
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{0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
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{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
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{0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
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{0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
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{0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
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@ -906,20 +906,20 @@ static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
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{0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
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{0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
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{0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
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{0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
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{0x0000a54c, 0x59025eb6, 0x59025eb6, 0x42001a83, 0x42001a83},
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{0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001c84, 0x44001c84},
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{0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
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{0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
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{0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
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{0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
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{0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
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{0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
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{0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
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{0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
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{0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
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{0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
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{0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
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{0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
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{0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
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{0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
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{0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
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{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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@ -1053,7 +1053,6 @@ static const u32 ar9462_2p0_mac_core[][2] = {
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{0x00008044, 0x00000000},
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{0x00008048, 0x00000000},
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{0x0000804c, 0xffffffff},
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{0x00008050, 0xffffffff},
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{0x00008054, 0x00000000},
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{0x00008058, 0x00000000},
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{0x0000805c, 0x000fc78f},
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@ -1117,9 +1116,9 @@ static const u32 ar9462_2p0_mac_core[][2] = {
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{0x000081f8, 0x00000000},
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{0x000081fc, 0x00000000},
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{0x00008240, 0x00100000},
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{0x00008244, 0x0010f424},
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{0x00008244, 0x0010f400},
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{0x00008248, 0x00000800},
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{0x0000824c, 0x0001e848},
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{0x0000824c, 0x0001e800},
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{0x00008250, 0x00000000},
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{0x00008254, 0x00000000},
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{0x00008258, 0x00000000},
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