openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/amdkfd: Delete alloc_format field from map_queue struct 

Alloc format was never really supported by MEC FW. FW always
does one per pipe allocation.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Oak Zeng 2019-02-14 10:25:42 -06:00 committed by Alex Deucher
parent 14568cf658
commit 16631afff2
4 changed files with 2 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
View File

@ -153,8 +153,6 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES, packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
sizeof(struct pm4_mes_map_queues)); sizeof(struct pm4_mes_map_queues));
packet->bitfields2.alloc_format =
alloc_format__mes_map_queues__one_per_pipe_vi;
packet->bitfields2.num_queues = 1; packet->bitfields2.num_queues = 1;
packet->bitfields2.queue_sel = packet->bitfields2.queue_sel =
queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi; queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;

2
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
View File

@ -190,8 +190,6 @@ static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer,
packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES, packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
sizeof(struct pm4_mes_map_queues)); sizeof(struct pm4_mes_map_queues));
packet->bitfields2.alloc_format =
alloc_format__mes_map_queues__one_per_pipe_vi;
packet->bitfields2.num_queues = 1; packet->bitfields2.num_queues = 1;
packet->bitfields2.queue_sel = packet->bitfields2.queue_sel =
queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi; queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;

7
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
View File

@ -255,11 +255,6 @@ enum mes_map_queues_queue_type_enum {
queue_type__mes_map_queues__low_latency_static_queue_vi = 3 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
}; };
enum mes_map_queues_alloc_format_enum {
alloc_format__mes_map_queues__one_per_pipe_vi = 0,
alloc_format__mes_map_queues__all_on_one_pipe_vi = 1
};
enum mes_map_queues_engine_sel_enum { enum mes_map_queues_engine_sel_enum {
engine_sel__mes_map_queues__compute_vi = 0, engine_sel__mes_map_queues__compute_vi = 0,
engine_sel__mes_map_queues__sdma0_vi = 2, engine_sel__mes_map_queues__sdma0_vi = 2,
@ -279,7 +274,7 @@ struct pm4_mes_map_queues {
enum mes_map_queues_queue_sel_enum queue_sel:2; enum mes_map_queues_queue_sel_enum queue_sel:2;
uint32_t reserved2:15; uint32_t reserved2:15;
enum mes_map_queues_queue_type_enum queue_type:3; enum mes_map_queues_queue_type_enum queue_type:3;
enum mes_map_queues_alloc_format_enum alloc_format:2; uint32_t reserved3:2;
enum mes_map_queues_engine_sel_enum engine_sel:3; enum mes_map_queues_engine_sel_enum engine_sel:3;
uint32_t num_queues:3; uint32_t num_queues:3;
} bitfields2; } bitfields2;

7
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h
View File

@ -216,11 +216,6 @@ enum mes_map_queues_queue_type_vi_enum {
queue_type__mes_map_queues__low_latency_static_queue_vi = 3 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
}; };
enum mes_map_queues_alloc_format_vi_enum {
alloc_format__mes_map_queues__one_per_pipe_vi = 0,
alloc_format__mes_map_queues__all_on_one_pipe_vi = 1
};
enum mes_map_queues_engine_sel_vi_enum { enum mes_map_queues_engine_sel_vi_enum {
engine_sel__mes_map_queues__compute_vi = 0, engine_sel__mes_map_queues__compute_vi = 0,
engine_sel__mes_map_queues__sdma0_vi = 2, engine_sel__mes_map_queues__sdma0_vi = 2,
@ -240,7 +235,7 @@ struct pm4_mes_map_queues {
enum mes_map_queues_queue_sel_vi_enum queue_sel:2; enum mes_map_queues_queue_sel_vi_enum queue_sel:2;
uint32_t reserved2:15; uint32_t reserved2:15;
enum mes_map_queues_queue_type_vi_enum queue_type:3; enum mes_map_queues_queue_type_vi_enum queue_type:3;
enum mes_map_queues_alloc_format_vi_enum alloc_format:2; uint32_t reserved3:2;
enum mes_map_queues_engine_sel_vi_enum engine_sel:3; enum mes_map_queues_engine_sel_vi_enum engine_sel:3;
uint32_t num_queues:3; uint32_t num_queues:3;
} bitfields2; } bitfields2;