From 2ffc224f3ab047f16d2dc73b90a6fe148c03f946 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 16 Mar 2016 10:03:09 +0900 Subject: [PATCH 01/26] ARM: dts: lager: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the lager device tree to use the generic rather than renesas-specific properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- arch/arm/boot/dts/r8a7790-lager.dts | 92 ++++++++++++++--------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index aa6ca92a9485..a5828721ab7c 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -314,119 +314,119 @@ &pfc { pinctrl-names = "default"; du_pins: du { - renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data"; - renesas,function = "scif0"; + groups = "scif0_data"; + function = "scif0"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; scifa1_pins: serial1 { - renesas,groups = "scifa1_data"; - renesas,function = "scifa1"; + groups = "scifa1_data"; + function = "scifa1"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; mmc1_pins: mmc1 { - renesas,groups = "mmc1_data8", "mmc1_ctrl"; - renesas,function = "mmc1"; + groups = "mmc1_data8", "mmc1_ctrl"; + function = "mmc1"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; msiof1_pins: spi2 { - renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", + groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", "msiof1_tx"; - renesas,function = "msiof1"; + function = "msiof1"; }; i2c0_pins: i2c0 { - renesas,groups = "i2c0"; - renesas,function = "i2c0"; + groups = "i2c0"; + function = "i2c0"; }; iic0_pins: iic0 { - renesas,groups = "iic0"; - renesas,function = "iic0"; + groups = "iic0"; + function = "iic0"; }; iic1_pins: iic1 { - renesas,groups = "iic1"; - renesas,function = "iic1"; + groups = "iic1"; + function = "iic1"; }; iic2_pins: iic2 { - renesas,groups = "iic2"; - renesas,function = "iic2"; + groups = "iic2"; + function = "iic2"; }; iic3_pins: iic3 { - renesas,groups = "iic3"; - renesas,function = "iic3"; + groups = "iic3"; + function = "iic3"; }; hsusb_pins: hsusb { - renesas,groups = "usb0_ovc_vbus"; - renesas,function = "usb0"; + groups = "usb0_ovc_vbus"; + function = "usb0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; usb2_pins: usb2 { - renesas,groups = "usb2"; - renesas,function = "usb2"; + groups = "usb2"; + function = "usb2"; }; vin1_pins: vin { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; From a32f5cff122b41f01a4ed18a9007871344b651c3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:52:11 +0900 Subject: [PATCH 02/26] ARM: dts: ape6evm: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the ape6evm device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 590257095700..93ace33e3e36 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -189,28 +189,28 @@ &cmt1 { &pfc { scifa0_pins: serial0 { - renesas,groups = "scifa0_data"; - renesas,function = "scifa0"; + groups = "scifa0_data"; + function = "scifa0"; }; mmc0_pins: mmc { - renesas,groups = "mmc0_data8", "mmc0_ctrl"; - renesas,function = "mmc0"; + groups = "mmc0_data8", "mmc0_ctrl"; + function = "mmc0"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; keyboard_pins: keyboard { - renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327", - "PORT328", "PORT329"; + pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", + "PORT329"; bias-pull-up; }; }; From 1ba1e26ededf070da2b1af117f912d2d9f05accf Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:53:17 +0900 Subject: [PATCH 03/26] ARM: dts: armadillo800eva: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the armadillo800eva device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index c548cabb102f..2c82dab2b6f4 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -228,44 +228,44 @@ &pfc { pinctrl-names = "default"; ether_pins: ether { - renesas,groups = "gether_mii", "gether_int"; - renesas,function = "gether"; + groups = "gether_mii", "gether_int"; + function = "gether"; }; scifa1_pins: serial1 { - renesas,groups = "scifa1_data"; - renesas,function = "scifa1"; + groups = "scifa1_data"; + function = "scifa1"; }; st1232_pins: touchscreen { - renesas,groups = "intc_irq10"; - renesas,function = "intc"; + groups = "intc_irq10"; + function = "intc"; }; backlight_pins: backlight { - renesas,groups = "tpu0_to2_1"; - renesas,function = "tpu0"; + groups = "tpu0_to2_1"; + function = "tpu0"; }; mmc0_pins: mmc0 { - renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; - renesas,function = "mmc0"; + groups = "mmc0_data8_1", "mmc0_ctrl_1"; + function = "mmc0"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; + function = "sdhi0"; }; fsia_pins: sounda { - renesas,groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - renesas,function = "fsia"; + groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + function = "fsia"; }; lcd0_pins: lcd0 { - renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; - renesas,function = "lcd0"; + groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; + function = "lcd0"; /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; From ddf72563890a3361f7da82510ef8baca37a13830 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:53:54 +0900 Subject: [PATCH 04/26] ARM: dts: bockw: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the bockw device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7778-bockw.dts | 40 ++++++++++++++--------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 21e3b9dda2da..e0dab1464648 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -130,53 +130,53 @@ &pfc { pinctrl-names = "default"; scif0_pins: serial0 { - renesas,groups = "scif0_data_a", "scif0_ctrl"; - renesas,function = "scif0"; + groups = "scif0_data_a", "scif0_ctrl"; + function = "scif0"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; mmc_pins: mmc { - renesas,groups = "mmc_data8", "mmc_ctrl"; - renesas,function = "mmc"; + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi0_pup_pins: sd0_pup { - renesas,groups = "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; bias-pull-up; }; hspi0_pins: hspi0 { - renesas,groups = "hspi0_a"; - renesas,function = "hspi0"; + groups = "hspi0_a"; + function = "hspi0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; vin1_pins: vin1 { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; }; From 8870d1393e0685d0bb1ae879fb1db3ffcf9a1020 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:54:24 +0900 Subject: [PATCH 05/26] ARM: dts: marzen: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the marzen device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7779-marzen.dts | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index e111d35d02ae..b795da6f5503 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -170,49 +170,49 @@ &pfc { du_pins: du { du0 { - renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; - renesas,function = "du0"; + groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + function = "du0"; }; du1 { - renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; - renesas,function = "du1"; + groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; + function = "du1"; }; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk_b"; - renesas,function = "scif_clk"; + groups = "scif_clk_b"; + function = "scif_clk"; }; ethernet_pins: ethernet { intc { - renesas,groups = "intc_irq1_b"; - renesas,function = "intc"; + groups = "intc_irq1_b"; + function = "intc"; }; lbsc { - renesas,groups = "lbsc_ex_cs0"; - renesas,function = "lbsc"; + groups = "lbsc_ex_cs0"; + function = "lbsc"; }; }; scif2_pins: serial2 { - renesas,groups = "scif2_data_c"; - renesas,function = "scif2"; + groups = "scif2_data_c"; + function = "scif2"; }; scif4_pins: serial4 { - renesas,groups = "scif4_data"; - renesas,function = "scif4"; + groups = "scif4_data"; + function = "scif4"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; }; hspi0_pins: hspi0 { - renesas,groups = "hspi0"; - renesas,function = "hspi0"; + groups = "hspi0"; + function = "hspi0"; }; }; From fec7b9f8952f396d88228677f44d52c7e20a6be8 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:55:10 +0900 Subject: [PATCH 06/26] ARM: dts: koelsch: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the koelsch device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791-koelsch.dts | 68 +++++++++++++-------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 0ad71b81d3a2..c6b43c85a0b1 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -324,89 +324,89 @@ &pfc { pinctrl-names = "default"; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; + groups = "scif1_data_d"; + function = "scif1"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; msiof0_pins: spi1 { - renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", "msiof0_tx"; - renesas,function = "msiof0"; + function = "msiof0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin1_pins: vin1 { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; From b2abb296ad8cb576ea90e813842fa204bc21aebb Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:55:31 +0900 Subject: [PATCH 07/26] ARM: dts: porter: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the porter device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791-porter.dts | 60 ++++++++++++++-------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 6c08314427d6..af3751ff519a 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -147,78 +147,78 @@ &pfc { pinctrl-names = "default"; scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; can0_pins: can0 { - renesas,groups = "can0_data"; - renesas,function = "can0"; + groups = "can0_data"; + function = "can0"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; ssi_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; audio_clk_pins: audio_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; From 2e207c1cd0f883a7d89b5241295c167e45f994b2 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:55:47 +0900 Subject: [PATCH 08/26] ARM: dts: gose: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the gose device tree to use the generic Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793-gose.dts | 40 +++++++++++++++--------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 87e89ec9dd47..c61df8b316ee 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -240,53 +240,53 @@ &pfc { pinctrl-names = "default"; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; + groups = "scif1_data_d"; + function = "scif1"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; From be7359dd9813e44bad827607048dd16298076bb8 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:56:21 +0900 Subject: [PATCH 09/26] ARM: dts: alt: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the alt device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794-alt.dts | 32 +++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index ca9bc4fff287..383ad791f1db 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -107,38 +107,38 @@ &pfc { pinctrl-names = "default"; du_pins: du { - renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; - renesas,function = "du"; + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; + function = "du"; }; scif2_pins: serial2 { - renesas,groups = "scif2_data"; - renesas,function = "scif2"; + groups = "scif2_data"; + function = "scif2"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq8"; - renesas,function = "intc"; + groups = "intc_irq8"; + function = "intc"; }; i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; + groups = "i2c1"; + function = "i2c1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; }; @@ -148,8 +148,8 @@ &cmt0 { &pfc { qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; }; From 4386ed21e5c1944f9b666f405796499526c5e59b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:57:28 +0900 Subject: [PATCH 10/26] ARM: dts: silk: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the silk device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794-silk.dts | 44 +++++++++++++++--------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 66f077a3ca41..56d98d5b2185 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -130,58 +130,58 @@ &pfc { pinctrl-names = "default"; scif2_pins: serial2 { - renesas,groups = "scif2_data"; - renesas,function = "scif2"; + groups = "scif2_data"; + function = "scif2"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq8"; - renesas,function = "intc"; + groups = "intc_irq8"; + function = "intc"; }; i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; + groups = "i2c1"; + function = "i2c1"; }; mmcif0_pins: mmcif0 { - renesas,groups = "mmc_data8", "mmc_ctrl"; - renesas,function = "mmc"; + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; }; From ffff86d16ed25655643f75fdb83eb70f0a8496af Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:57:10 +0900 Subject: [PATCH 11/26] ARM: dts: kzm9g: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the kzm9g device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/sh73a0-kzm9g.dts | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index aa8bae3b8fcf..e40a2f23b6cd 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -329,41 +329,41 @@ &mmcif { &pfc { i2c3_pins: i2c3 { - renesas,groups = "i2c3_1"; - renesas,function = "i2c3"; + groups = "i2c3_1"; + function = "i2c3"; }; mmcif_pins: mmc { mux { - renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; - renesas,function = "mmc0"; + groups = "mmc0_data8_0", "mmc0_ctrl_0"; + function = "mmc0"; }; cfg { - renesas,groups = "mmc0_data8_0"; - renesas,pins = "PORT279"; + groups = "mmc0_data8_0"; + pins = "PORT279"; bias-pull-up; }; }; scifa4_pins: serial4 { - renesas,groups = "scifa4_data", "scifa4_ctrl"; - renesas,function = "scifa4"; + groups = "scifa4_data", "scifa4_ctrl"; + function = "scifa4"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; fsia_pins: sounda { - renesas,groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - renesas,function = "fsia"; + groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + function = "fsia"; }; }; From 20ccdd90ab22808e582d81cdfac09e3b804e7b20 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 07:57:10 +0900 Subject: [PATCH 12/26] ARM: dts: kzm9d: use generic pinctrl properties Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties. This patch updates the kzm9d device tree to use the generic properties. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/emev2-kzm9d.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 8c24975e8f9d..a35b851e1cd7 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -105,8 +105,8 @@ &iic1 { &pfc { uart1_pins: serial@e1030000 { - renesas,groups = "uart1_ctrl", "uart1_data"; - renesas,function = "uart1"; + groups = "uart1_ctrl", "uart1_data"; + function = "uart1"; }; }; From b19dd47b27d2bd719d304f27c0a4fcd3f51632dd Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 16 Mar 2016 09:21:13 +0900 Subject: [PATCH 13/26] ARM: dts: r8a7790: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary the nodes. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 88 +++++++++++----------------------- 1 file changed, 28 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 38b706399a6b..283698fc0fea 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1003,20 +1003,18 @@ clocks { ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus_clk { + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; - clock-output-names = "pcie_bus"; status = "disabled"; }; @@ -1028,19 +1026,16 @@ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; }; /* External SCIF clock */ @@ -1053,11 +1048,10 @@ scif_clk: scif { }; /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal_clk { + usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "usb_extal"; }; /* External CAN clock */ @@ -1066,7 +1060,6 @@ can_clk: can_clk { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "can_clk"; status = "disabled"; }; @@ -1084,201 +1077,176 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - mmc1_clk: mmc1_clk@e6150244 { + mmc1_clk: mmc1@e6150244 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc1"; }; - ssp_clk: ssp_clk@e6150248 { + ssp_clk: ssp@e6150248 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150248 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssp"; }; - ssprs_clk: ssprs_clk@e615024c { + ssprs_clk: ssprs@e615024c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615024c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssprs"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - z2_clk: z2_clk { + z2_clk: z2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "z2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - imp_clk: imp_clk { + imp_clk: imp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "imp"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ From 21f189705929b9d27a44f0ae3d2ddd390c545670 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:10:44 +0900 Subject: [PATCH 14/26] ARM: dts: r7s72100: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r7s72100.dtsi | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 89e46ebef1bc..e8e2a5d71976 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -37,46 +37,41 @@ clocks { #size-cells = <1>; /* External clocks */ - extal_clk: extal_clk { + extal_clk: extal { #clock-cells = <0>; compatible = "fixed-clock"; /* If clk present, value must be set by board */ clock-frequency = <0>; - clock-output-names = "extal"; }; - usb_x1_clk: usb_x1_clk { + usb_x1_clk: usb_x1 { #clock-cells = <0>; compatible = "fixed-clock"; /* If clk present, value must be set by board */ clock-frequency = <0>; - clock-output-names = "usb_x1"; }; /* Fixed factor clocks */ - b_clk: b_clk { + b_clk: b { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <3>; - clock-output-names = "b"; }; - p1_clk: p1_clk { + p1_clk: p1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <6>; - clock-output-names = "p1"; }; - p0_clk: p0_clk { + p0_clk: p0 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <12>; - clock-output-names = "p0"; }; /* Special CPG clocks */ From 2dca78980372f154a2181e6044db71be9da626e9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:14:31 +0900 Subject: [PATCH 15/26] ARM: dts: r8a7740: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7740.dtsi | 57 ++++++++++++---------------------- 1 file changed, 19 insertions(+), 38 deletions(-) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 995fbda74b7a..39b2f88ad151 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -422,53 +422,45 @@ clocks { ranges; /* External root clock */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal2"; }; - dv_clk: dv_clk { + dv_clk: dv { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; - clock-output-names = "dv"; }; - fmsick_clk: fmsick_clk { + fmsick_clk: fmsick { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fmsick"; }; - fmsock_clk: fmsock_clk { + fmsock_clk: fmsock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fmsock"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -486,7 +478,7 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, @@ -494,9 +486,8 @@ vclk1_clk: vclk1_clk@e6150008 { <&extal1_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, @@ -504,77 +495,67 @@ vclk2_clk: vclk2_clk@e615000c { <&extal1_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - fmsi_clk: fmsi_clk@e6150010 { + fmsi_clk: fmsi@e6150010 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150010 4>; clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fmsi"; }; - fmso_clk: fmso_clk@e6150014 { + fmso_clk: fmso@e6150014 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fmso"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - sub_clk: sub_clk@e6150080 { + sub_clk: sub@e6150080 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; clocks = <&pllc1_div2_clk>, <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "sub"; }; - spu_clk: spu_clk@e6150084 { + spu_clk: spu@e6150084 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; clocks = <&pllc1_div2_clk>, <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "spu"; }; - vou_clk: vou_clk@e6150088 { + vou_clk: vou@e6150088 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, <0>; #clock-cells = <0>; - clock-output-names = "vou"; }; - stpro_clk: stpro_clk@e615009c { + stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; #clock-cells = <0>; - clock-output-names = "stpro"; }; /* Fixed factor clocks */ - pllc1_div2_clk: pllc1_div2_clk { + pllc1_div2_clk: pllc1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pllc1_div2"; }; - extal1_div2_clk: extal1_div2_clk { + extal1_div2_clk: extal1_div2 { compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "extal1_div2"; }; /* Gate clocks */ From 452fc89994c2a81ade92096088b94ecbfef436a8 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:15:11 +0900 Subject: [PATCH 16/26] ARM: dts: r8a7778: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7778.dtsi | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index f83a348fc07a..99c10ebbaca2 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -443,11 +443,10 @@ clocks { ranges; /* External input clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal"; }; /* External SCIF clock */ @@ -474,59 +473,51 @@ cpg_clocks: cpg_clocks@ffc80000 { audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_c"; }; /* Fixed ratio clocks */ - g_clk: g_clk { + g_clk: g { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "g"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; - clock-output-names = "i"; }; - s3_clk: s3_clk { + s3_clk: s3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "s3"; }; - s4_clk: s4_clk { + s4_clk: s4 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "s4"; }; - z_clk: z_clk { + z_clk: z { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLB>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; - clock-output-names = "z"; }; /* Gate clocks */ From 3f6dba702c57908c5f66601ced6ef9f131759611 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:15:34 +0900 Subject: [PATCH 17/26] ARM: dts: r8a7779: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7779.dtsi | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index a0cc08e6295b..60bc1e66bba9 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -445,12 +445,11 @@ clocks { ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* External SCIF clock */ @@ -474,37 +473,33 @@ cpg_clocks: clocks@ffc80000 { }; /* Fixed factor clocks */ - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - s3_clk: s3_clk { + s3_clk: s3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "s3"; }; - s4_clk: s4_clk { + s4_clk: s4 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; - clock-output-names = "s4"; }; - g_clk: g_clk { + g_clk: g { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "g"; }; /* Gate clocks */ From f617604fe5d74b9c8d3333bad2e4959abe4594a4 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:16:23 +0900 Subject: [PATCH 18/26] ARM: dts: r8a7791: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 79 +++++++++++----------------------- 1 file changed, 25 insertions(+), 54 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6439f0569fe2..8010d935300f 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1048,12 +1048,11 @@ clocks { ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* @@ -1064,27 +1063,23 @@ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; }; /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus_clk { + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; - clock-output-names = "pcie_bus"; status = "disabled"; }; @@ -1098,11 +1093,10 @@ scif_clk: scif { }; /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal_clk { + usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "usb_extal"; }; /* External CAN clock */ @@ -1111,7 +1105,6 @@ can_clk: can_clk { #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "can_clk"; status = "disabled"; }; @@ -1129,178 +1122,156 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - ssp_clk: ssp_clk@e6150248 { + ssp_clk: ssp@e6150248 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150248 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssp"; }; - ssprs_clk: ssprs_clk@e615024c { + ssprs_clk: ssprs@e615024c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615024c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssprs"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ From 3b81c0ce13c53445b1e38fa1ff86025e5b8a9199 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:09 +0900 Subject: [PATCH 19/26] ARM: dts: r8a7793: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 45 +++++++++++----------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index b48215945241..95bbed95b0c1 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -812,12 +812,11 @@ clocks { ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* @@ -828,19 +827,16 @@ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; }; /* External SCIF clock */ @@ -866,111 +862,98 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <5>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ From 337f6bef6dd8dd9d2621980e2d34150d2014909c Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:57 +0900 Subject: [PATCH 20/26] ARM: dts: r8a7794: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 66 ++++++++++++---------------------- 1 file changed, 22 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index eacb2b291361..7d7d18766540 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -836,12 +836,11 @@ clocks { ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* External SCIF clock */ @@ -865,173 +864,152 @@ cpg_clocks: cpg_clocks@e6150000 { #power-domain-cells = <0>; }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cp"; }; - acp_clk: acp_clk { + acp_clk: acp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "acp"; }; /* Gate clocks */ From 45e4f51311f3d4551326bfa43547f86b00af0a94 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:57 +0900 Subject: [PATCH 21/26] ARM: dts: gose: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793-gose.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index c61df8b316ee..3cd1c804621f 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -158,11 +158,10 @@ led8 { }; }; - audio_clock: clock { + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { From 62c7e9da598611827f09984386fa1438ccc46f87 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:57 +0900 Subject: [PATCH 22/26] ARM: dts: koelsch: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791-koelsch.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index c6b43c85a0b1..1adf8770db7e 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -242,11 +242,10 @@ vccq_sdhi2: regulator@5 { 1800000 0>; }; - audio_clock: clock { + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { From 203f0ef865303412a9d03a88a2f845db682ac628 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:57 +0900 Subject: [PATCH 23/26] ARM: dts: porter: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791-porter.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index af3751ff519a..9554d13362f6 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -113,11 +113,10 @@ x16_clk: x16-clock { clock-frequency = <74250000>; }; - x14_clk: x14-clock { + x14_clk: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; sound { From a5bad2c7c9ee0f5e188b97baeb383753fad53c86 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Mar 2016 08:17:57 +0900 Subject: [PATCH 24/26] ARM: dts: lager: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790-lager.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index a5828721ab7c..823a119cb1b4 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -176,11 +176,10 @@ vccq_sdhi2: regulator@4 { 1800000 0>; }; - audio_clock: clock { + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { From 57c75d1ed6890b8c57fce5d0c557a6b486c4d898 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Mar 2016 10:06:42 +0900 Subject: [PATCH 25/26] ARM: dts: r8a73a4: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. The clock-output-names property is left in place for the zb_clk which is thus treated as a special case as the MSTP clock driver (clk-mstp.c) explicitly looks for a clock with node name zb_clk for the r8a73a4 and sh73a0 SoCs. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a73a4.dtsi | 75 ++++++++++++---------------------- 1 file changed, 25 insertions(+), 50 deletions(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6583a1dfca1f..6954912a3753 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -486,37 +486,32 @@ clocks { ranges; /* External root clocks */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "extal2"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -540,171 +535,151 @@ zb_clk: zb_clk@e6150010 { #clock-cells = <0>; clock-output-names = "zb"; }; - sdhi0_clk: sdhi0_clk@e6150074 { + sdhi0_clk: sdhi0ck@e6150074 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150074 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi0ck"; }; - sdhi1_clk: sdhi1_clk@e6150078 { + sdhi1_clk: sdhi1ck@e6150078 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi1ck"; }; - sdhi2_clk: sdhi2_clk@e615007c { + sdhi2_clk: sdhi2ck@e615007c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615007c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi2ck"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - mmc1_clk: mmc1_clk@e6150244 { + mmc1_clk: mmc1@e6150244 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mmc1"; }; - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150008 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615000c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - vclk3_clk: vclk3_clk@e615001c { + vclk3_clk: vclk3@e615001c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615001c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk3"; }; - vclk4_clk: vclk4_clk@e6150014 { + vclk4_clk: vclk4@e6150014 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150014 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk4"; }; - vclk5_clk: vclk5_clk@e6150034 { + vclk5_clk: vclk5@e6150034 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150034 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk5"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150018 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsiack_clk>, <0>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - fsib_clk: fsib_clk@e6150090 { + fsib_clk: fsib@e6150090 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150090 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsibck_clk>, <0>; #clock-cells = <0>; - clock-output-names = "fsib"; }; - mp_clk: mp_clk@e6150080 { + mp_clk: mp@e6150080 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150080 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mp"; }; - m4_clk: m4_clk@e6150098 { + m4_clk: m4@e6150098 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150098 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; #clock-cells = <0>; - clock-output-names = "m4"; }; - hsi_clk: hsi_clk@e615026c { + hsi_clk: hsi@e615026c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; #clock-cells = <0>; - clock-output-names = "hsi"; }; - spuv_clk: spuv_clk@e6150094 { + spuv_clk: spuv@e6150094 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150094 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spuv"; }; /* Fixed factor clocks */ - main_div2_clk: main_div2_clk { + main_div2_clk: main_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "main_div2"; }; - pll0_div2_clk: pll0_div2_clk { + pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll0_div2"; }; - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - extal1_div2_clk: extal1_div2_clk { + extal1_div2_clk: extal1_div2 { compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "extal1_div2"; }; /* Gate clocks */ From 000025cfbb9e8bafd0a1fa84d8d83526d24bde42 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Mar 2016 10:06:43 +0900 Subject: [PATCH 26/26] ARM: dts: sh73a0: Remove unnecessary clock-output-names properties * Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. The clock-output-names property is left in place for the zb_clk which is thus treated as a special case as the MSTP clock driver (clk-mstp.c) explicitly looks for a clock with node name zb_clk for the r8a73a4 and sh73a0 SoCs. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/boot/dts/sh73a0.dtsi | 87 ++++++++++++----------------------- 1 file changed, 29 insertions(+), 58 deletions(-) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index bf825ca4f6f7..639ea2d76970 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -602,39 +602,33 @@ clocks { ranges; /* External root clocks */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extal2"; }; - extcki_clk: extcki_clk { + extcki_clk: extcki { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extcki"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -650,7 +644,7 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -658,9 +652,8 @@ vclk1_clk: vclk1_clk@e6150008 { <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -668,9 +661,8 @@ vclk2_clk: vclk2_clk@e615000c { <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - vclk3_clk: vclk3_clk@e615001c { + vclk3_clk: vclk3@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -678,7 +670,6 @@ vclk3_clk: vclk3_clk@e615001c { <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk3"; }; zb_clk: zb_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; @@ -688,168 +679,148 @@ zb_clk: zb_clk@e6150010 { #clock-cells = <0>; clock-output-names = "zb"; }; - flctl_clk: flctl_clk@e6150014 { + flctl_clk: flctlck@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "flctlck"; }; - sdhi0_clk: sdhi0_clk@e6150074 { + sdhi0_clk: sdhi0ck@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi0ck"; }; - sdhi1_clk: sdhi1_clk@e6150078 { + sdhi1_clk: sdhi1ck@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi1ck"; }; - sdhi2_clk: sdhi2_clk@e615007c { + sdhi2_clk: sdhi2ck@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi2ck"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsiack_clk>, <&fsiack_clk>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - fsib_clk: fsib_clk@e6150090 { + fsib_clk: fsib@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsibck_clk>, <&fsibck_clk>; #clock-cells = <0>; - clock-output-names = "fsib"; }; - sub_clk: sub_clk@e6150080 { + sub_clk: sub@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sub"; }; - spua_clk: spua_clk@e6150084 { + spua_clk: spua@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spua"; }; - spuv_clk: spuv_clk@e6150094 { + spuv_clk: spuv@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spuv"; }; - msu_clk: msu_clk@e6150088 { + msu_clk: msu@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "msu"; }; - hsi_clk: hsi_clk@e615008c { + hsi_clk: hsi@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div7_clk>, <0>; #clock-cells = <0>; - clock-output-names = "hsi"; }; - mfg1_clk: mfg1_clk@e6150098 { + mfg1_clk: mfg1@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg1"; }; - mfg2_clk: mfg2_clk@e615009c { + mfg2_clk: mfg2@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg2"; }; - dsit_clk: dsit_clk@e6150060 { + dsit_clk: dsit@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "dsit"; }; - dsi0p_clk: dsi0p_clk@e6150064 { + dsi0p_clk: dsi0pck@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, <&extcki_clk>, <0>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "dsi0pck"; }; /* Fixed factor clocks */ - main_div2_clk: main_div2_clk { + main_div2_clk: main_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "main_div2"; }; - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - pll1_div7_clk: pll1_div7_clk { + pll1_div7_clk: pll1_div7 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <7>; clock-mult = <1>; - clock-output-names = "pll1_div7"; }; - pll1_div13_clk: pll1_div13_clk { + pll1_div13_clk: pll1_div13 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <13>; clock-mult = <1>; - clock-output-names = "pll1_div13"; }; - twd_clk: twd_clk { + twd_clk: twd { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_Z>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "twd"; }; /* Gate clocks */