mirror of https://gitee.com/openkylin/linux.git
powerpc/85xx: Updates to P4080DS device tree
* Added BSD dual-license * Moved mpic-parent to root so we dont need to duplicate everywhere * Added next level cache from L2 to CPC * Moved to 4-cell MPIC interrupt properties * Added 3 MSI banks * Added numerous missing nodes: soc-sram-error, guts, pins, clockgen, rcpm, sfp, serdes, etc. * Reworked PCIe interrupts to be at virtual bridge level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
e181877d86
commit
169296b38f
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@ -3,10 +3,33 @@
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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@ -16,6 +39,7 @@ / {
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compatible = "fsl,P4080DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ccsr = &soc;
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@ -32,6 +56,9 @@ aliases {
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dma0 = &dma0;
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dma1 = &dma1;
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sdhc = &sdhc;
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msi0 = &msi0;
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msi1 = &msi1;
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msi2 = &msi2;
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crypto = &crypto;
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sec_jr0 = &sec_jr0;
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@ -56,6 +83,7 @@ cpu0: PowerPC,4080@0 {
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reg = <0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu1: PowerPC,4080@1 {
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@ -63,6 +91,7 @@ cpu1: PowerPC,4080@1 {
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reg = <1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu2: PowerPC,4080@2 {
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@ -70,6 +99,7 @@ cpu2: PowerPC,4080@2 {
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reg = <2>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu3: PowerPC,4080@3 {
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@ -77,6 +107,7 @@ cpu3: PowerPC,4080@3 {
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reg = <3>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu4: PowerPC,4080@4 {
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@ -84,6 +115,7 @@ cpu4: PowerPC,4080@4 {
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reg = <4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu5: PowerPC,4080@5 {
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@ -91,6 +123,7 @@ cpu5: PowerPC,4080@5 {
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reg = <5>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu6: PowerPC,4080@6 {
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@ -98,6 +131,7 @@ cpu6: PowerPC,4080@6 {
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reg = <6>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu7: PowerPC,4080@7 {
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@ -105,6 +139,7 @@ cpu7: PowerPC,4080@7 {
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reg = <7>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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};
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@ -121,6 +156,11 @@ soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 29>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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@ -128,42 +168,132 @@ corenet-law@0 {
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};
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memory-controller@8000 {
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compatible = "fsl,p4080-memory-controller";
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compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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interrupts = <16 2 1 23>;
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};
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memory-controller@9000 {
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compatible = "fsl,p4080-memory-controller";
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compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
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reg = <0x9000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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interrupts = <16 2 1 22>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,p4080-l3-cache-controller", "cache";
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reg = <0x10000 0x1000
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0x11000 0x1000>;
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interrupts = <16 2 1 27
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16 2 1 26>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,p4080-pamu";
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reg = <0x20000 0x10000>;
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interrupts = <24 2>;
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interrupt-parent = <&mpic>;
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x5000>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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compatible = "fsl,mpic", "chrp,open-pic";
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device_type = "open-pic";
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};
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msi0: msi@41600 {
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compatible = "fsl,mpic-msi";
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reg = <0x41600 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0 0 0
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0xe1 0 0 0
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0xe2 0 0 0
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0xe3 0 0 0
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0xe4 0 0 0
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0xe5 0 0 0
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0xe6 0 0 0
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0xe7 0 0 0>;
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};
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msi1: msi@41800 {
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compatible = "fsl,mpic-msi";
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reg = <0x41800 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe8 0 0 0
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0xe9 0 0 0
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0xea 0 0 0
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0xeb 0 0 0
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0xec 0 0 0
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0xed 0 0 0
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0xee 0 0 0
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0xef 0 0 0>;
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};
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msi2: msi@41a00 {
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compatible = "fsl,mpic-msi";
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reg = <0x41a00 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xf0 0 0 0
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0xf1 0 0 0
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0xf2 0 0 0
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0xf3 0 0 0
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0xf4 0 0 0
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0xf5 0 0 0
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0xf6 0 0 0
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0xf7 0 0 0>;
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};
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guts: global-utilities@e0000 {
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compatible = "fsl,qoriq-device-config-1.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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#sleep-cells = <1>;
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fsl,liodn-bits = <12>;
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};
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pins: global-utilities@e0e00 {
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compatible = "fsl,qoriq-pin-control-1.0";
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reg = <0xe0e00 0x200>;
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#sleep-cells = <2>;
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};
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clockgen: global-utilities@e1000 {
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compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
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reg = <0xe1000 0x1000>;
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clock-frequency = <0>;
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};
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rcpm: global-utilities@e2000 {
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compatible = "fsl,qoriq-rcpm-1.0";
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reg = <0xe2000 0x1000>;
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#sleep-cells = <1>;
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};
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sfp: sfp@e8000 {
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compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
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reg = <0xe8000 0x1000>;
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};
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serdes: serdes@ea000 {
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compatible = "fsl,p4080-serdes";
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reg = <0xea000 0x1000>;
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};
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dma0: dma@100300 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -176,32 +306,28 @@ dma-channel@0 {
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <28 2>;
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interrupts = <28 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <29 2>;
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interrupts = <29 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <30 2>;
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interrupts = <30 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <31 2>;
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interrupts = <31 2 0 0>;
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};
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};
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@ -217,32 +343,28 @@ dma-channel@0 {
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <32 2>;
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interrupts = <32 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <33 2>;
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interrupts = <33 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <34 2>;
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interrupts = <34 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <35 2>;
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interrupts = <35 2 0 0>;
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};
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};
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@ -251,8 +373,7 @@ spi@110000 {
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#size-cells = <0>;
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compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
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reg = <0x110000 0x1000>;
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interrupts = <53 0x2>;
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interrupt-parent = <&mpic>;
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interrupts = <53 0x2 0 0>;
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fsl,espi-num-chipselects = <4>;
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flash@0 {
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@ -286,10 +407,10 @@ partition@fs {
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sdhc: sdhc@114000 {
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compatible = "fsl,p4080-esdhc", "fsl,esdhc";
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reg = <0x114000 0x1000>;
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interrupts = <48 2>;
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interrupt-parent = <&mpic>;
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interrupts = <48 2 0 0>;
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voltage-ranges = <3300 3300>;
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sdhci,auto-cmd12;
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clock-frequency = <0>;
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};
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i2c@118000 {
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@ -298,8 +419,7 @@ i2c@118000 {
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x118000 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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interrupts = <38 2 0 0>;
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dfsrr;
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};
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@ -309,8 +429,7 @@ i2c@118100 {
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x118100 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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interrupts = <38 2 0 0>;
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dfsrr;
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eeprom@51 {
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compatible = "at24,24c256";
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@ -323,8 +442,7 @@ eeprom@52 {
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <0x1 0x1 0 0>;
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};
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};
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@ -334,8 +452,7 @@ i2c@119000 {
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cell-index = <2>;
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compatible = "fsl-i2c";
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reg = <0x119000 0x100>;
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interrupts = <39 2>;
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interrupt-parent = <&mpic>;
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interrupts = <39 2 0 0>;
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dfsrr;
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};
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@ -345,8 +462,7 @@ i2c@119100 {
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cell-index = <3>;
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compatible = "fsl-i2c";
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reg = <0x119100 0x100>;
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interrupts = <39 2>;
|
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interrupt-parent = <&mpic>;
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||||
interrupts = <39 2 0 0>;
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dfsrr;
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||||
};
|
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|
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|
@ -356,8 +472,7 @@ serial0: serial@11c500 {
|
|||
compatible = "ns16550";
|
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reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
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serial1: serial@11c600 {
|
||||
|
|
@ -366,8 +481,7 @@ serial1: serial@11c600 {
|
|||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
|
|
@ -376,8 +490,7 @@ serial2: serial@11d500 {
|
|||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
|
|
@ -386,15 +499,13 @@ serial3: serial@11d600 {
|
|||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p4080-gpio";
|
||||
compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <55 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
|
@ -405,8 +516,7 @@ usb0: usb@210000 {
|
|||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <44 0x2>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
|
|
@ -416,8 +526,7 @@ usb1: usb@211000 {
|
|||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <45 0x2>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
|
@ -429,34 +538,34 @@ crypto: crypto@300000 {
|
|||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <92 2>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <88 2>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <89 2>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <90 2>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <91 2>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
|
|
@ -492,7 +601,7 @@ sec_mon: sec_mon@314000 {
|
|||
compatible = "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <93 2>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -501,17 +610,21 @@ rapidio0: rapidio@ffe0c0000 {
|
|||
#size-cells = <2>;
|
||||
compatible = "fsl,rapidio-delta";
|
||||
reg = <0xf 0xfe0c0000 0 0x20000>;
|
||||
ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* err_irq bell_outb_irq bell_inb_irq
|
||||
msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
|
||||
interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
|
||||
ranges = <0 0 0xc 0x20000000 0 0x01000000>;
|
||||
interrupts = <
|
||||
16 2 1 11 /* err_irq */
|
||||
56 2 0 0 /* bell_outb_irq */
|
||||
57 2 0 0 /* bell_inb_irq */
|
||||
60 2 0 0 /* msg1_tx_irq */
|
||||
61 2 0 0 /* msg1_rx_irq */
|
||||
62 2 0 0 /* msg2_tx_irq */
|
||||
63 2 0 0>; /* msg2_rx_irq */
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xf 0xfe124000 0 0x1000>;
|
||||
interrupts = <25 2>;
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -528,7 +641,6 @@ flash@0,0 {
|
|||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe200000 0 0x1000>;
|
||||
|
|
@ -536,22 +648,23 @@ pci0: pcie@ffe200000 {
|
|||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
fsl,msi = <&msi0>;
|
||||
interrupts = <16 2 1 15>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
@ -565,7 +678,6 @@ pcie@0 {
|
|||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe201000 0 0x1000>;
|
||||
|
|
@ -573,21 +685,23 @@ pci1: pcie@ffe201000 {
|
|||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
fsl,msi = <&msi1>;
|
||||
interrupts = <16 2 1 14>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
@ -601,7 +715,6 @@ pcie@0 {
|
|||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
|
|
@ -609,21 +722,23 @@ pci2: pcie@ffe202000 {
|
|||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 1
|
||||
>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 13>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
|
|||
Loading…
Reference in New Issue