openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/amd/display: Do not grant POST_LT_ADJ when TPS4 is used 

[Description]

The spec does not allow POST_LT_ADJ_GRANTED to be set when TPS4 is used.

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
abdoulaye berthe 2019-05-27 11:38:26 -04:00 committed by Alex Deucher
parent 3de5aa81c5
commit 16b6253a08
1 changed files with 31 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -89,6 +89,29 @@ static void dpcd_set_training_pattern(
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}
static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
{
enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
struct encoder_feature_support *features = &link->link_enc->features;
struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
if (features->flags.bits.IS_TPS3_CAPABLE)
highest_tp = HW_DP_TRAINING_PATTERN_3;
if (features->flags.bits.IS_TPS4_CAPABLE)
highest_tp = HW_DP_TRAINING_PATTERN_4;
if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
highest_tp >= HW_DP_TRAINING_PATTERN_4)
return HW_DP_TRAINING_PATTERN_4;
if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
highest_tp >= HW_DP_TRAINING_PATTERN_3)
return HW_DP_TRAINING_PATTERN_3;
return HW_DP_TRAINING_PATTERN_2;
}
static void dpcd_set_link_settings(
struct dc_link *link,
const struct link_training_settings *lt_settings)
@ -97,6 +120,7 @@ static void dpcd_set_link_settings(
union down_spread_ctrl downspread = { {0} };
union lane_count_set lane_count_set = { {0} };
enum hw_dp_training_pattern hw_tr_pattern;
downspread.raw = (uint8_t)
(lt_settings->link_settings.link_spread);
@ -106,8 +130,13 @@ static void dpcd_set_link_settings(
lane_count_set.bits.ENHANCED_FRAMING = 1;
lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
hw_tr_pattern = get_supported_tp(link);
if (hw_tr_pattern != HW_DP_TRAINING_PATTERN_4) {
lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
}
core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
@ -698,29 +727,6 @@ static bool perform_post_lt_adj_req_sequence(
}
static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
{
enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
struct encoder_feature_support *features = &link->link_enc->features;
struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
if (features->flags.bits.IS_TPS3_CAPABLE)
highest_tp = HW_DP_TRAINING_PATTERN_3;
if (features->flags.bits.IS_TPS4_CAPABLE)
highest_tp = HW_DP_TRAINING_PATTERN_4;
if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
highest_tp >= HW_DP_TRAINING_PATTERN_4)
return HW_DP_TRAINING_PATTERN_4;
if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
highest_tp >= HW_DP_TRAINING_PATTERN_3)
return HW_DP_TRAINING_PATTERN_3;
return HW_DP_TRAINING_PATTERN_2;
}
static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status)
{