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ASoC: rockchip: i2s: configure the sdio pins' iomux mode
There are 3 i2s sdio pins, which iomux mode is as follows: - sdi3_sdo1 - sdi2_sdo2 - sdi1_sdo3 we need to configure these pins' iomux mode via the GRF register when use multi channel playback/capture. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sugar Zhang
Mark Brown
parent
1a695a905c
commit
170abcaae8
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@ -23,6 +23,11 @@ Required properties:
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- rockchip,playback-channels: max playback channels, if not set, 8 channels default.
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- rockchip,capture-channels: max capture channels, if not set, 2 channels default.
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Required properties for controller which support multi channels
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playback/capture:
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- rockchip,grf: the phandle of the syscon node for GRF register.
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Example for rk3288 I2S controller:
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i2s@ff890000 {
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@ -11,8 +11,10 @@
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*/
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/delay.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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@ -23,6 +25,11 @@
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#define DRV_NAME "rockchip-i2s"
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struct rk_i2s_pins {
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u32 reg_offset;
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u32 shift;
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};
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struct rk_i2s_dev {
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struct device *dev;
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@ -33,6 +40,7 @@ struct rk_i2s_dev {
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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struct regmap *grf;
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/*
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* Used to indicate the tx/rx status.
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@ -42,6 +50,7 @@ struct rk_i2s_dev {
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bool tx_start;
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bool rx_start;
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bool is_master_mode;
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const struct rk_i2s_pins *pins;
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};
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static int i2s_runtime_suspend(struct device *dev)
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@ -300,6 +309,30 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
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I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
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val);
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if (!IS_ERR(i2s->grf) && i2s->pins) {
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regmap_read(i2s->regmap, I2S_TXCR, &val);
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val &= I2S_TXCR_CSR_MASK;
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switch (val) {
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case I2S_CHN_4:
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val = I2S_IO_4CH_OUT_6CH_IN;
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break;
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case I2S_CHN_6:
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val = I2S_IO_6CH_OUT_4CH_IN;
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break;
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case I2S_CHN_8:
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val = I2S_IO_8CH_OUT_2CH_IN;
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break;
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default:
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val = I2S_IO_2CH_OUT_8CH_IN;
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break;
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}
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val <<= i2s->pins->shift;
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val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
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regmap_write(i2s->grf, i2s->pins->reg_offset, val);
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}
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
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I2S_DMACR_TDL(16));
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
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@ -485,9 +518,23 @@ static const struct regmap_config rockchip_i2s_regmap_config = {
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.cache_type = REGCACHE_FLAT,
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};
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static const struct rk_i2s_pins rk3399_i2s_pins = {
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.reg_offset = 0xe220,
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.shift = 11,
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};
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static const struct of_device_id rockchip_i2s_match[] = {
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{ .compatible = "rockchip,rk3066-i2s", },
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{ .compatible = "rockchip,rk3188-i2s", },
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{ .compatible = "rockchip,rk3288-i2s", },
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{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
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{},
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};
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static int rockchip_i2s_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct of_device_id *of_id;
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struct rk_i2s_dev *i2s;
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struct snd_soc_dai_driver *soc_dai;
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struct resource *res;
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@ -501,6 +548,17 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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i2s->dev = &pdev->dev;
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i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
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if (!IS_ERR(i2s->grf)) {
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of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
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if (!of_id || !of_id->data)
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return -EINVAL;
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i2s->pins = of_id->data;
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}
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/* try to prepare related clocks */
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i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
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if (IS_ERR(i2s->hclk)) {
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@ -540,7 +598,6 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
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i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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i2s->capture_dma_data.maxburst = 4;
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i2s->dev = &pdev->dev;
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dev_set_drvdata(&pdev->dev, i2s);
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pm_runtime_enable(&pdev->dev);
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@ -606,14 +663,6 @@ static int rockchip_i2s_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id rockchip_i2s_match[] = {
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{ .compatible = "rockchip,rk3066-i2s", },
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{ .compatible = "rockchip,rk3188-i2s", },
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{ .compatible = "rockchip,rk3288-i2s", },
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{ .compatible = "rockchip,rk3399-i2s", },
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{},
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};
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static const struct dev_pm_ops rockchip_i2s_pm_ops = {
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SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
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NULL)
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@ -236,4 +236,11 @@ enum {
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#define I2S_TXDR (0x0024)
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#define I2S_RXDR (0x0028)
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/* io direction cfg register */
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#define I2S_IO_DIRECTION_MASK (7)
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#define I2S_IO_8CH_OUT_2CH_IN (0)
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#define I2S_IO_6CH_OUT_4CH_IN (4)
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#define I2S_IO_4CH_OUT_6CH_IN (6)
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#define I2S_IO_2CH_OUT_8CH_IN (7)
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#endif /* _ROCKCHIP_IIS_H */
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