mirror of https://gitee.com/openkylin/linux.git
Renesas ARM64 Based SoC DT Updates for v4.18
* Cleanups:
- Corresct whitespace
- sort subnodes of the root and soc nodes
* R-Car M3-N (r8a77965) SoC
- Describe MSIOF SPI, PWM, SDHI and I2C devices in DT
- Add thermal support
* R-Car H3 (r8a7795) and R-Car M3-W (r8a7796) SoCs
- Decrease temperature hysteresis
Niklas Söderlund says "... decrease the hysteresis from 2C to 1C for
the two boards we have described upstream. They have no dependencies
and are ready to be accepted if the review is in favor of them."
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Add address properties to rcar_sound port nodes
The rcar_sound port nodes have unit names and thus should have register
properties.
* R-Car H3 (r8a7795), M3-W (r8a7796) V3M (r8a77970) and D3 (r8a77995) SoCs
- Enable IPMMU devices
Magnus Damm says "Following the policy of using DT to describe the
hardware and not software support state, this series makes sure all
IPMMU devices are enabled in DT for SoCs such as r8a7795, r8a7796,
r8a77970 and r8a77995."
* R-Car M3-N (r8a77965) and V3H (r8a77980) SoCs
- Use sysc binding macros
These can be used now that they are present in Linus's tree.
This is a simple replacement of numeric values with symbolic ones.
- Describe USB2 and USB3 devices in DT
* R-Car V3M (r8a77970) SoC
- Add SMP Support
Geert Uytterhoeven says "This patch series enables SMP support on the
R-Car V3M SoC, by adding the second Cortex-A53 CPU core. It also adds
the performance monitor unit, and links it to both CPU cores."
- Correct IPMMU DS1 bit number
Magnus Damm says "Judging by "R-Car-Gen3-rev0.80" IPMMU IMSSTR register
documentation for [R-Car V3M] the DS1 bit field should be bit 0."
* R-Car V3H (r8a77980) SoC
- Use CPG clock binding macros
These can be used now that they are present in Linus's tree.
This is a simple replacement of numeric values with symbolic ones.
* R-Car V3H (r8a77980) and V3M (r8a77970) SoCs
- Disable EtherAVB
Sergei Shtylov says "I'm fixing the issue in the EtherAVB device nodes
in the R8A779{7|8}0 device trees that missed the "status" prop, usually
disabling the SoC devices in anticipation that the board device trees
enable the devices according to their needs. There should be no issues
with the current R8A779{7|8}0 board device trees, as all of them use
EtherAVB anyway, so I'm sending the patches generated against the
'devel' branch..."
* R-Car D3 (r8a77995) SoC
- Describe VIN4 in DT
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support:
+ PSCI
+ CPU (single)
+ Cache controller
+ Main clocks and controller
+ Interrupt controller
+ Timer
+ PMU
+ Reset controller
+ Product register
+ System controller
+ UART for console
* Salvator-XS boards with R-Car H3 (r8a7795) SoC
- Enable USB2.0 channel 3
* Salvator-X and Salvator-XS boards with M3-N (r8a77965) SoC
- Enable DU
Kieran Bingham "This series enables the DU for the M3-N R8A77965 SoC,
and provides output on the VGA and HDMI connectors.
LVDS is not yet supported or tested."
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Enable nable VIN, CSI-2 and ADV7482
Niklas Söderlund says "This series enable capture for H3, M3-W, M3-N
Salvator-X and Salvator-XS boards. It also adds the VIN and CSI-2 nodes
for V3M, but as the ADV7482 is on the V3M expansion boards I have
chosen not include that enablement in this series."
- Add PMIC DDR Backup Power config
Geert Uytterhoeven says " The ROHM BD9571MWV PMIC on the Renesas
Salvator-X(S) and ULCB development boards supports DDR Backup Power,
which means that the DDR power rails can be kept powered while the main
SoC is powered down.
For this to function correctly, the DDR Backup Power configuration
must be described in DT, which is the topic of this series:
- The first patch adds the missing device node for the BD9571 PMIC on
the ULCB boards,
- The last two patches add DDR Backup Mode configuration for
Salvator-X(S) and ULCB."
- Add EEPROM
Wolfram Sang says "Add the EEPROM found on Salvator-X and -XS boards
for H3, M3-W, and M3-N on the IIC_DVFS bus."
- Enable HDMI Sound
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs, and
Draak board with R-Car D3 (r8a77995) SoC
- Consistently name EtherAVB mdio pin group
Geert Uytterhoeven says "When initial support was added for R-Car H3,
the MDIO pin was forgotten, and the MDC pin got its own group named
"mdc". During the addition of support for R-Car M3-W, this mistake was
noticed. But as R-Car H3 and M3-W are pin compatible, and can be
mounted on the same boards, the decision was made to just add the MDIO
pin to the existing "mdc" group. Later this was extended to R-Car H3
ES2.0, and M3-N, because of pin compatibility, and to R-Car D3, in the
name of consistency among R-Car Gen3 SoCs.
However, this decision keeps on being questioned when adding new SoC
support. Hence bite the bullet and admit our mistake, and rename the
pin group from "mdc" to "mdio", like on R-Car Gen2 SoCs."
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support: Memory, Main crystal, Serial console
- Enable Ethernet
- Revise PSCI node
Yoshihiro Shimoda says "The basic support patch 2d2dbadba421 ("arm64:
dts: renesas: Add Renesas R8A77990 SoC support") lacks the compatible
"arm,psci-1.0" in the psci node."
- Revise cache controller node
Yoshihiro Shimoda says "The cache controller node should not have
unit-addresses and reg properties."
* V3HSK board with R-Car V3H (r8a77980) SoC
- Initial board device tree
Sergei Shtylov says "Add the initial device tree for the V3H Starter
Kit board. The board has 1 debug serial port (SCIF0); include support
for it, so that the serial console can work."
- Enable PFC support and use for EtherAVB
* V3MSK board with R-Car V3M (r8a77970) SoC
- Add DU/LVDS/HDMI support
Sergei Shtylyov says "Define the V3M Starter Kit board dependent part
of the DU and LVDS device nodes. Also add the device nodes for Thine
THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI
transmitter..."
- Enable PFC for EtherAVB
* Condor board with R-Car V3H (r8a77980) SoC
- Enable eMMC
Sergei Shtylyov says "We're adding the R8A77980 MMC (SDHI)
device nodes and then enable eMMC support on the Condor board."
- Enable PFC support and use for EtherAVB and SCIF0
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable HDMI output
* Eagle board with R-Car V3M (r8a77970) SoC and
Condor board with R-Car V3H (r8a77980) SoC
- Enable CAN-FD
Adds the CAN-FD device nodes so the DT SoC files and enables
single channel CAN-FD support in DT board files.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlr+pZkACgkQ189kaWo3
T77FOhAAs+F25gyyQZ13/JE38Q+ku2gSrpJLwJJYjztez1EA9Jh15k7xlgU2uEaa
+YtOodVHqL85LeHp8FMyahOmG6bh+pvqXjAc47ZVDootNm+518gdPvhZ0nWbWuYu
SKskMN+W5pxkbDNUfIij3TCApAWEAQH4ExJxAMjTJc9ddTPmYKvOyWZTyQvm3qQA
XsH0uOeDCmasRiJ9rUf6nPBCS4vn7U5w8cbRYQkDymrUmpEO8f+K6nMj+2yTvJJ/
G0sA8R7Q/9ULRGs4XGadIcQ71xmwpBr13FKMC9xtlhI1NI6HIGo2RkHBRwD4mGay
PgBhAQR4oekdyEoVwKu3KlTa3Fpohu/NbiwJMTu1QCgAtdd4MCv1RXq3QZIZtTQn
V3FNVwaH2u4DaX814C2Dmj11zkcehc02uURzRU/pk5UmnIJ4utghu2RmpwO7YQX7
LqBrzRFHd+Qt03Thp/fwbsdWPYvgrRDSL5v9VV/87RD0zJ9yQR/mjr4OyI5DT6g5
bEcj535n9X3FY2SFjFWKl4BjuwOcTtiY15oFKdnFcBF2wobaiKO68YgvaYgFpHMD
T5e+bOgq2IPKW8Z6qMboyj2z9a3oHa6xkEJMEJGKxotViQQC7JUHu3/7cknUelSs
LP1cJy7IP/62Qb9lvUqJ70Py+L430cuHw6+/Ssf98sRaTx0VD2I=
=4IoI
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
Renesas ARM64 Based SoC DT Updates for v4.18
* Cleanups:
- Correct whitespace
- sort subnodes of the root and soc nodes
* R-Car M3-N (r8a77965) SoC
- Describe MSIOF SPI, PWM, SDHI and I2C devices in DT
- Add thermal support
* R-Car H3 (r8a7795) and R-Car M3-W (r8a7796) SoCs
- Decrease temperature hysteresis
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Add address properties to rcar_sound port nodes
* R-Car H3 (r8a7795), M3-W (r8a7796) V3M (r8a77970) and D3 (r8a77995) SoCs
- Enable IPMMU devices
* R-Car M3-N (r8a77965) and V3H (r8a77980) SoCs
- Use sysc binding macros
- Describe USB2 and USB3 devices in DT
* R-Car V3M (r8a77970) SoC
- Add SMP Support
- Correct IPMMU DS1 bit number
* R-Car V3H (r8a77980) SoC
- Use CPG clock binding macros
* R-Car V3H (r8a77980) and V3M (r8a77970) SoCs
- Disable EtherAVB
* R-Car D3 (r8a77995) SoC
- Describe VIN4 in DT
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support
* Salvator-XS boards with R-Car H3 (r8a7795) SoC
- Enable USB2.0 channel 3
* Salvator-X and Salvator-XS boards with M3-N (r8a77965) SoC
- Enable DU
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Enable nable VIN, CSI-2 and ADV7482
- Add PMIC DDR Backup Power config
- Add EEPROM
- Enable HDMI Sound
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs, and
Draak board with R-Car D3 (r8a77995) SoC
- Consistently name EtherAVB mdio pin group
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support: Memory, Main crystal, Serial console
- Enable Ethernet
- Revise PSCI node
- Revise cache controller node
* V3HSK board with R-Car V3H (r8a77980) SoC
- Initial board device tree
- Enable PFC support and use for EtherAVB
* V3MSK board with R-Car V3M (r8a77970) SoC
- Add DU/LVDS/HDMI support
- Enable PFC for EtherAVB
* Condor board with R-Car V3H (r8a77980) SoC
- Enable eMMC
- Enable PFC support and use for EtherAVB and SCIF0
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable HDMI output
* Eagle board with R-Car V3M (r8a77970) SoC and
Condor board with R-Car V3H (r8a77980) SoC
- Enable CAN-FD
* tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
arm64: dts: renesas: salvator-common: Add ADV7482 support
arm64: dts: renesas: salvator-common: enable VIN
arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7795-es1: add CSI-2 node
arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add I2C support
arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB
arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
arm64: dts: renesas: r8a77990: Add GPIO device nodes
arm64: dts: renesas: r8a77990: Add PFC device node
arm64: dts: renesas: initial V3HSK board device tree
arm64: dts: renesas: r8a77980: disable EtherAVB
arm64: dts: renesas: r8a77970: disable EtherAVB
arm64: dts: renesas: r8a77995: Add VIN4
arm64: dts: renesas: r8a77980: add resets property to CAN-FD node
arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
arm64: dts: renesas: r8a77965: Add SDHI device nodes
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
171d429a1d
|
|
@ -208,6 +208,12 @@ config ARCH_R8A77980
|
|||
help
|
||||
This enables support for the Renesas R-Car V3H SoC.
|
||||
|
||||
config ARCH_R8A77990
|
||||
bool "Renesas R-Car E3 SoC Platform"
|
||||
depends on ARCH_RENESAS
|
||||
help
|
||||
This enables support for the Renesas R-Car E3 SoC.
|
||||
|
||||
config ARCH_R8A77995
|
||||
bool "Renesas R-Car D3 SoC Platform"
|
||||
depends on ARCH_RENESAS
|
||||
|
|
|
|||
|
|
@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
|
|||
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
|
||||
|
|
|
|||
|
|
@ -56,6 +56,12 @@ &ehci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
&rsnd_port2>; /* HDMI1 */
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint {
|
|||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint {
|
|||
remote-endpoint = <&hdmi1_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi1_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -94,6 +112,34 @@ &ohci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
rsnd_port2: port@2 {
|
||||
rsnd_endpoint2: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint2>;
|
||||
frame-master = <&rsnd_endpoint2>;
|
||||
|
||||
playback = <&ssi3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ ipmmu_sy: mmu@e7730000 {
|
|||
reg = <0 0xe7730000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 8>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/delete-node/ usb-phy@ee0e0200;
|
||||
|
|
@ -108,6 +107,61 @@ fdp1@fe948000 {
|
|||
resets = <&cpg 117>;
|
||||
renesas,fcp = <&fcpf2>;
|
||||
};
|
||||
|
||||
csi21: csi2@fea90000 {
|
||||
compatible = "renesas,r8a7795-csi2";
|
||||
reg = <0 0xfea90000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 713>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 713>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
csi21vin0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vin0csi21>;
|
||||
};
|
||||
csi21vin1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vin1csi21>;
|
||||
};
|
||||
csi21vin2: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&vin2csi21>;
|
||||
};
|
||||
csi21vin3: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&vin3csi21>;
|
||||
};
|
||||
csi21vin4: endpoint@4 {
|
||||
reg = <4>;
|
||||
remote-endpoint = <&vin4csi21>;
|
||||
};
|
||||
csi21vin5: endpoint@5 {
|
||||
reg = <5>;
|
||||
remote-endpoint = <&vin5csi21>;
|
||||
};
|
||||
csi21vin6: endpoint@6 {
|
||||
reg = <6>;
|
||||
remote-endpoint = <&vin6csi21>;
|
||||
};
|
||||
csi21vin7: endpoint@7 {
|
||||
reg = <7>;
|
||||
remote-endpoint = <&vin7csi21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
|
|
@ -175,3 +229,91 @@ &fcpvd2 {
|
|||
&du {
|
||||
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
|
||||
};
|
||||
|
||||
&vin0 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin0csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin1 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin1csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin2 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin2csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin3 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin3csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin4csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin5 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin5csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin6 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin6csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vin7 {
|
||||
ports {
|
||||
port@1 {
|
||||
vin7csi21: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint= <&csi21vin7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -56,6 +56,12 @@ &ehci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
&rsnd_port2>; /* HDMI1 */
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint {
|
|||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint {
|
|||
remote-endpoint = <&hdmi1_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi1_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -94,6 +112,34 @@ &ohci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
rsnd_port2: port@2 {
|
||||
rsnd_endpoint2: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint2>;
|
||||
frame-master = <&rsnd_endpoint2>;
|
||||
|
||||
playback = <&ssi3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
|
|
|
|||
|
|
@ -56,6 +56,22 @@ &ehci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb3 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
&rsnd_port2>; /* HDMI1 */
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -66,6 +82,12 @@ rcar_dw_hdmi0_out: endpoint {
|
|||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -83,6 +105,12 @@ rcar_dw_hdmi1_out: endpoint {
|
|||
remote-endpoint = <&hdmi1_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi1_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -94,11 +122,61 @@ &ohci2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci3 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
rsnd_port2: port@2 {
|
||||
rsnd_endpoint2: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint2>;
|
||||
frame-master = <&rsnd_endpoint2>;
|
||||
|
||||
playback = <&ssi3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
function = "usb2";
|
||||
};
|
||||
|
||||
/*
|
||||
* - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
|
||||
* (when SW31 is the default setting on Salvator-XS).
|
||||
* - If SW31 is the default setting, you cannot use USB2.0 ch3 on
|
||||
* r8a7795 with Salvator-XS.
|
||||
* Hence the SW31 setting must be changed like 2) below.
|
||||
* 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
|
||||
* - Connect GP6_3[01] to ADV7842.
|
||||
* 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
|
||||
* - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
|
||||
* - Connect GP6_{04,21} to ADV7842.
|
||||
*/
|
||||
usb2_ch3_pins: usb2_ch3 {
|
||||
groups = "usb2_ch3";
|
||||
function = "usb2_ch3";
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
|
|
@ -107,3 +185,10 @@ &usb2_phy2 {
|
|||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy3 {
|
||||
pinctrl-0 = <&usb2_ch3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -40,6 +40,11 @@ &du {
|
|||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1>; /* HDMI0 */
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint {
|
|||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@ &du {
|
|||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1>; /* HDMI0 */
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint {
|
|||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -19,3 +19,31 @@ memory@48000000 {
|
|||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x21_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,3 +19,31 @@ memory@48000000 {
|
|||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock6 1>,
|
||||
<&x21_clk>,
|
||||
<&versaclock6 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -31,9 +31,57 @@ memory@48000000 {
|
|||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
d3p3: regulator-fixed {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
|
||||
vcc-supply = <&d3p3>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
|
@ -47,6 +95,16 @@ phy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
|
@ -68,9 +126,51 @@ io_expander: gpio@20 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb0 {
|
||||
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data_a";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
|
|
@ -93,3 +193,19 @@ &scif0 {
|
|||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,9 +29,71 @@ memory@48000000 {
|
|||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
osc5_clk: osc5-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
vcc_d1_8v: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_D1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_d3_3v: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <&vcc_d3_3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
|
@ -43,6 +105,13 @@ phy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&osc5_clk>;
|
||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
|
@ -52,12 +121,80 @@ &extalr_clk {
|
|||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb0 {
|
||||
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hdmi@39{
|
||||
compatible = "adi,adv7511w";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&vcc_d1_8v>;
|
||||
dvdd-supply = <&vcc_d1_8v>;
|
||||
pvdd-supply = <&vcc_d1_8v>;
|
||||
bgvdd-supply = <&vcc_d1_8v>;
|
||||
dvdd-3v-supply = <&vcc_d3_3v>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -41,6 +41,16 @@ a53_0: cpu@0 {
|
|||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <1>;
|
||||
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
|
||||
power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A77970_PD_CA53_SCU>;
|
||||
|
|
@ -63,11 +73,25 @@ extalr_clk: extalr {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>, <&a53_1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -83,23 +107,6 @@ soc {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1010000 0 0x1000>,
|
||||
<0 0xf1020000 0 0x20000>,
|
||||
<0 0xf1040000 0 0x20000>,
|
||||
<0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a77970-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
|
|
@ -110,75 +117,6 @@ rwdt: watchdog@e6020000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77970-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77970-rst";
|
||||
reg = <0 0xe6160000 0 0x200>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77970-sysc";
|
||||
reg = <0 0xe6180000 0 0x440>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
power-domains = <&sysc R8A77970_PD_A3IR>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77970";
|
||||
reg = <0 0xe6060000 0 0x504>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
|
|
@ -269,6 +207,32 @@ gpio5: gpio@e6055000 {
|
|||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77970";
|
||||
reg = <0 0xe6060000 0 0x504>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77970-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77970-rst";
|
||||
reg = <0 0xe6160000 0 0x200>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77970-sysc";
|
||||
reg = <0 0xe6180000 0 0x440>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -285,67 +249,6 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77970",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77970",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
|
|
@ -502,6 +405,77 @@ hscif3: serial@e66a0000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77970-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77970",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_rt 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a77970",
|
||||
"renesas,rcar-gen3-scif",
|
||||
|
|
@ -573,57 +547,358 @@ scif4: serial@e6c40000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77970",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a77970";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_rt 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&cpg 811>;
|
||||
renesas,id = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a77970";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 810>;
|
||||
renesas,id = <1>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a77970";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 809>;
|
||||
renesas,id = <2>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a77970";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 808>;
|
||||
renesas,id = <3>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77970",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77970",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
power-domains = <&sysc R8A77970_PD_A3IR>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1010000 0 0x1000>,
|
||||
<0 0xf1020000 0 0x20000>,
|
||||
<0 0xf1040000 0 0x20000>,
|
||||
<0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 623>;
|
||||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
};
|
||||
|
||||
csi40: csi2@feaa0000 {
|
||||
compatible = "renesas,r8a77970-csi2";
|
||||
reg = <0 0xfeaa0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 716>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 716>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <1>;
|
||||
|
||||
csi40vin0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vin0csi40>;
|
||||
};
|
||||
csi40vin1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vin1csi40>;
|
||||
};
|
||||
csi40vin2: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&vin2csi40>;
|
||||
};
|
||||
csi40vin3: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&vin3csi40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a77970";
|
||||
reg = <0 0xfeb00000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>;
|
||||
clock-names = "du.0";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 724>;
|
||||
vsps = <&vspd0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds-encoder@feb90000 {
|
||||
compatible = "renesas,r8a77970-lvds";
|
||||
reg = <0 0xfeb90000 0 0x14>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 727>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint =
|
||||
<&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,9 +27,30 @@ memory@48000000 {
|
|||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0 0x48000000 0 0x78000000>;
|
||||
};
|
||||
|
||||
d3_3v: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddq_vin01: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDQ_VIN01";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy0>;
|
||||
renesas,no-ether-link;
|
||||
|
|
@ -41,6 +62,16 @@ phy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
|
@ -49,7 +80,57 @@ &extalr_clk {
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
pinctrl-1 = <&mmc_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&vddq_vin01>;
|
||||
mmc-hs200-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb {
|
||||
groups = "avb_mdio", "avb_rgmii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data_a";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
mmc_pins_uhs: mmc_uhs {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the V3H Starter Kit board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77980.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas V3H Starter Kit board";
|
||||
compatible = "renesas,v3hsk", "renesas,r8a77980";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0 0x48000000 0 0x78000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
|
@ -6,9 +6,10 @@
|
|||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a77980-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77980";
|
||||
|
|
@ -23,20 +24,27 @@ a53_0: cpu@0 {
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0>;
|
||||
clocks = <&cpg CPG_CORE 0>;
|
||||
power-domains = <&sysc 5>;
|
||||
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
|
||||
power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc 21>;
|
||||
power-domains = <&sysc R8A77980_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -71,6 +79,11 @@ soc {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77980";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77980-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
@ -99,13 +112,13 @@ hscif0: serial@e6540000 {
|
|||
reg = <0 0xe6540000 0 0x60>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 520>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
||||
<&dmac2 0x31>, <&dmac2 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 520>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -117,13 +130,13 @@ hscif1: serial@e6550000 {
|
|||
reg = <0 0xe6550000 0 0x60>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 519>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
|
||||
<&dmac2 0x33>, <&dmac2 0x32>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 519>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -135,13 +148,13 @@ hscif2: serial@e6560000 {
|
|||
reg = <0 0xe6560000 0 0x60>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 518>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
|
||||
<&dmac2 0x35>, <&dmac2 0x34>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 518>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -153,17 +166,42 @@ hscif3: serial@e66a0000 {
|
|||
reg = <0 0xe66a0000 0 0x60>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 517>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
|
||||
<&dmac2 0x37>, <&dmac2 0x36>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 517>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77980-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77980",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
|
|
@ -201,11 +239,12 @@ avb: ethernet@e6800000 {
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
|
|
@ -215,13 +254,13 @@ scif0: serial@e6e60000 {
|
|||
reg = <0 0xe6e60000 0 0x40>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 207>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
||||
<&dmac2 0x51>, <&dmac2 0x50>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 207>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -233,13 +272,13 @@ scif1: serial@e6e68000 {
|
|||
reg = <0 0xe6e68000 0 0x40>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 206>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
||||
<&dmac2 0x53>, <&dmac2 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 206>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -251,13 +290,13 @@ scif3: serial@e6c50000 {
|
|||
reg = <0 0xe6c50000 0 0x40>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 204>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
|
||||
<&dmac2 0x57>, <&dmac2 0x56>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 204>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -269,13 +308,13 @@ scif4: serial@e6c40000 {
|
|||
reg = <0 0xe6c40000 0 0x40>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 203>,
|
||||
<&cpg CPG_CORE 19>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
|
||||
<&dmac2 0x59>, <&dmac2 0x58>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 203>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -308,7 +347,7 @@ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
|
|||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
|
|
@ -342,12 +381,24 @@ GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
|
|||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
mmc0: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77980",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -361,7 +412,7 @@ gic: interrupt-controller@f1010000 {
|
|||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Device Tree Source for the ebisu board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas Ebisu board based on r8a77990";
|
||||
compatible = "renesas,ebisu", "renesas,r8a77990";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Device Tree Source for the r8a77990 SoC
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77990";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 1 core only at this point */
|
||||
a53_0: cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc 5>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc 21>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 18>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 912>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 23>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 911>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 26>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 910>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 16>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 909>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 11>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 908>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 20>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a77990",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 18>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 906>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77990";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77990-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77990-rst";
|
||||
reg = <0 0xe6160000 0 0x0200>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77990-sysc";
|
||||
reg = <0 0xe6180000 0 0x0400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77990",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a77990",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
|
@ -91,7 +91,7 @@ &extal_clk {
|
|||
&pfc {
|
||||
avb0_pins: avb {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdc", "avb0_mii";
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_mii";
|
||||
function = "avb0";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,9 +18,11 @@ / {
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -51,18 +53,16 @@ extal_clk: extal {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -76,23 +76,6 @@ soc {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a77995-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
|
|
@ -103,207 +86,6 @@ rwdt: watchdog@e6020000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77995-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77995-rst";
|
||||
reg = <0 0xe6160000 0 0x0200>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77995";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77995-sysc";
|
||||
reg = <0 0xe6180000 0 0x0400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a77995",
|
||||
"renesas,rcar-gen3-gpio",
|
||||
|
|
@ -416,124 +198,46 @@ gpio6: gpio@e6055400 {
|
|||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
can0: can@e6c30000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c30000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77995";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
||||
can1: can@e6c38000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c38000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77995-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77995-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a77995-rst";
|
||||
reg = <0 0xe6160000 0 0x0200>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77995",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a77995-sysc";
|
||||
reg = <0 0xe6180000 0 0x0400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a77995",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
|
|
@ -603,6 +307,252 @@ i2c3: i2c@e66d0000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77995-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77995",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@e6c30000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c30000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6c38000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c38000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 0x8>;
|
||||
|
|
@ -643,15 +593,43 @@ pwm3: pwm@e6e33000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a77995",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 64>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a77995";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 807>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 807>;
|
||||
renesas,id = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -668,18 +646,6 @@ ehci0: usb@ee080100 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@ee080200 {
|
||||
compatible = "renesas,usb2-phy-r8a77995",
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
|
|
@ -692,6 +658,35 @@ usb2_phy0: usb-phy@ee080200 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
vspbs: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
|
|
@ -702,15 +697,6 @@ vspbs: vsp@fe960000 {
|
|||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
|
|
@ -721,15 +707,6 @@ vspd0: vsp@fea20000 {
|
|||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x8000>;
|
||||
|
|
@ -740,6 +717,24 @@ vspd1: vsp@fea28000 {
|
|||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
|
|
@ -783,6 +778,11 @@ du_out_lvds1: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -66,6 +66,29 @@ backlight: backlight {
|
|||
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cvbs-in {
|
||||
compatible = "composite-video-connector";
|
||||
label = "CVBS IN";
|
||||
|
||||
port {
|
||||
cvbs_con: endpoint {
|
||||
remote-endpoint = <&adv7482_ain7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI IN";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_in_con: endpoint {
|
||||
remote-endpoint = <&adv7482_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
|
|
@ -93,20 +116,12 @@ reg_12v: regulator2 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
sound_card: sound {
|
||||
compatible = "audio-graph-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
label = "rcar-sound";
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
dais = <&rsnd_port0>;
|
||||
};
|
||||
|
||||
vbus0_usb2: regulator-vbus0-usb2 {
|
||||
|
|
@ -268,6 +283,37 @@ phy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&csi20 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csi20_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1>;
|
||||
remote-endpoint = <&adv7482_txb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&adv7482_txa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -322,6 +368,12 @@ ak4613: codec@10 {
|
|||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
|
||||
port {
|
||||
ak4613_endpoint: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs2000: clk_multiplier@4f {
|
||||
|
|
@ -359,6 +411,55 @@ csa_dvfs: adc@7f {
|
|||
|
||||
shunt-resistor-micro-ohms = <5000>;
|
||||
};
|
||||
|
||||
video-receiver@70 {
|
||||
compatible = "adi,adv7482";
|
||||
reg = <0x70>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupt-names = "intrq1", "intrq2";
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
|
||||
<31 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
|
||||
adv7482_ain7: endpoint {
|
||||
remote-endpoint = <&cvbs_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <8>;
|
||||
|
||||
adv7482_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_in_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@10 {
|
||||
reg = <10>;
|
||||
|
||||
adv7482_txa: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@11 {
|
||||
reg = <11>;
|
||||
|
||||
adv7482_txb: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1>;
|
||||
remote-endpoint = <&csi20_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
|
|
@ -376,6 +477,8 @@ pmic: pmic@30 {
|
|||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
rohm,ddr-backup-power = <0xf>;
|
||||
rohm,rstbmode-level;
|
||||
|
||||
regulators {
|
||||
dvfs: dvfs {
|
||||
|
|
@ -387,6 +490,12 @@ dvfs: dvfs {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
|
|
@ -416,12 +525,12 @@ &pfc {
|
|||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mdc", "avb_mii";
|
||||
groups = "avb_link", "avb_mdio", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
pins_mdc {
|
||||
groups = "avb_mdc";
|
||||
pins_mdio {
|
||||
groups = "avb_mdio";
|
||||
drive-strength = <24>;
|
||||
};
|
||||
|
||||
|
|
@ -581,10 +690,18 @@ &rcar_sound {
|
|||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
ports {
|
||||
rsnd_port0: port@0 {
|
||||
rsnd_endpoint0: endpoint {
|
||||
remote-endpoint = <&ak4613_endpoint>;
|
||||
|
||||
dai-format = "left_j";
|
||||
bitclock-master = <&rsnd_endpoint0>;
|
||||
frame-master = <&rsnd_endpoint0>;
|
||||
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -689,6 +806,38 @@ &usb3s0_clk {
|
|||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -243,6 +243,32 @@ versaclock5: clock-generator@6a {
|
|||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "rohm,bd9571mwv";
|
||||
reg = <0x30>;
|
||||
interrupt-parent = <&intc_ex>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
rohm,ddr-backup-power = <0xf>;
|
||||
rohm,rstbmode-pulse;
|
||||
|
||||
regulators {
|
||||
dvfs: dvfs {
|
||||
regulator-name = "dvfs";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1030000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
|
|
@ -255,12 +281,12 @@ &pfc {
|
|||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mdc", "avb_mii";
|
||||
groups = "avb_link", "avb_mdio", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
pins_mdc {
|
||||
groups = "avb_mdc";
|
||||
pins_mdio {
|
||||
groups = "avb_mdio";
|
||||
drive-strength = <24>;
|
||||
};
|
||||
|
||||
|
|
@ -276,6 +302,11 @@ i2c2_pins: i2c2 {
|
|||
function = "i2c2";
|
||||
};
|
||||
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
|
|
|
|||
Loading…
Reference in New Issue