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drm/amd/powerplay: fix sw SMU wrong UVD/VCE powergate setting 

The UVD/VCE bits are set wrongly. This causes the UVD/VCE clocks
are not brought back correctly on needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-05-17 13:39:36 +08:00 committed by Alex Deucher
parent d6ee400e79
commit 17a839135f
1 changed files with 11 additions and 11 deletions
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22
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
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@ -1834,17 +1834,6 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu,
}
static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
{
if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
return 0;
if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
return 0;
return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
}
static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
{
if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))
return 0;
@ -1855,6 +1844,17 @@ static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
}
static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
{
if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
return 0;
if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
return 0;
return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
}
static int smu_v11_0_get_current_rpm(struct smu_context *smu,
uint32_t *current_rpm)
{