mirror of https://gitee.com/openkylin/linux.git
powerpc/booke: Move nohash headers
Move the booke related headers below booke/32 or booke/64 Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
1ca7212932
commit
17ed9e3192
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
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#define _ASM_POWERPC_PGTABLE_PPC32_H
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#ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
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#define _ASM_POWERPC_NOHASH_32_PGTABLE_H
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#include <asm-generic/pgtable-nopmd.h>
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@ -106,15 +106,15 @@ extern int icache_44x_need_flush;
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*/
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#if defined(CONFIG_40x)
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#include <asm/pte-40x.h>
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#include <asm/nohash/32/pte-40x.h>
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#elif defined(CONFIG_44x)
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#include <asm/pte-44x.h>
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#include <asm/nohash/32/pte-44x.h>
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#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
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#include <asm/pte-book3e.h>
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#include <asm/nohash/pte-book3e.h>
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#elif defined(CONFIG_FSL_BOOKE)
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#include <asm/pte-fsl-booke.h>
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#include <asm/nohash/32/pte-fsl-booke.h>
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#elif defined(CONFIG_8xx)
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#include <asm/pte-8xx.h>
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#include <asm/nohash/32/pte-8xx.h>
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#endif
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/* And here we include common definitions */
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@ -340,4 +340,4 @@ extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
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#endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PTE_40x_H
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#define _ASM_POWERPC_PTE_40x_H
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_40x_H
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#define _ASM_POWERPC_NOHASH_32_PTE_40x_H
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#ifdef __KERNEL__
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/*
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@ -61,4 +61,4 @@
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#define PTE_ATOMIC_UPDATES 1
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_40x_H */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PTE_44x_H
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#define _ASM_POWERPC_PTE_44x_H
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_44x_H
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#define _ASM_POWERPC_NOHASH_32_PTE_44x_H
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#ifdef __KERNEL__
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/*
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@ -94,4 +94,4 @@
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_44x_H */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PTE_8xx_H
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#define _ASM_POWERPC_PTE_8xx_H
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
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#define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
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#ifdef __KERNEL__
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/*
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@ -62,4 +62,4 @@
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_PAGE_HWWRITE | _PAGE_EXEC)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_8xx_H */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
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#define _ASM_POWERPC_PTE_FSL_BOOKE_H
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
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#define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
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#ifdef __KERNEL__
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/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
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@ -37,4 +37,4 @@
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#define PTE_WIMGE_SHIFT (6)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
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#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
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#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
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#define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
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/*
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* Entries per page directory level. The PTE level must use a 64b record
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* for each page table entry. The PMD and PGD level use a 32b record for
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@ -89,4 +89,4 @@ extern struct page *pgd_page(pgd_t pgd);
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
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#endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
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#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
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#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
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#define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
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#include <asm-generic/pgtable-nopud.h>
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@ -41,4 +41,4 @@
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#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
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#define pte_pgd(pte) ((pgd_t)pte_pud(pte))
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#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
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#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */
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@ -1,14 +1,14 @@
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#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
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#define _ASM_POWERPC_PGTABLE_PPC64_H_
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#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_H
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#define _ASM_POWERPC_NOHASH_64_PGTABLE_H
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/*
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* This file contains the functions and defines necessary to modify and use
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* the ppc64 hashed page table.
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*/
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/pgtable-ppc64-64k.h>
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#include <asm/nohash/64/pgtable-64k.h>
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#else
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#include <asm/pgtable-ppc64-4k.h>
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#include <asm/nohash/64/pgtable-4k.h>
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#endif
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#include <asm/barrier.h>
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@ -18,7 +18,7 @@
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* Size of EA range mapped by our pagetables.
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*/
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#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
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PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
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PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
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#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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@ -97,7 +97,7 @@
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/*
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* Include the PTE bits definitions
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*/
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#include <asm/pte-book3e.h>
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#include <asm/nohash/pte-book3e.h>
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#include <asm/pte-common.h>
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#ifdef CONFIG_PPC_MM_SLICES
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@ -637,4 +637,4 @@ static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
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return true;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
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#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_H */
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@ -1,10 +1,10 @@
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#ifndef _ASM_POWERPC_PGTABLE_BOOK3E_H
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#define _ASM_POWERPC_PGTABLE_BOOK3E_H
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#ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
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#define _ASM_POWERPC_NOHASH_PGTABLE_H
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#if defined(CONFIG_PPC64)
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#include <asm/pgtable-ppc64.h>
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#include <asm/nohash/64/pgtable.h>
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#else
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#include <asm/pgtable-ppc32.h>
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#include <asm/nohash/32/pgtable.h>
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#endif
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#ifndef __ASSEMBLY__
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@ -1,5 +1,5 @@
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#ifndef _ASM_POWERPC_PTE_BOOK3E_H
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#define _ASM_POWERPC_PTE_BOOK3E_H
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#ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
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#define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
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#ifdef __KERNEL__
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/* PTE bit definitions for processors compliant to the Book3E
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@ -84,4 +84,4 @@
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
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#endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */
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@ -15,7 +15,7 @@ struct mm_struct;
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/book3s/pgtable.h>
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#else
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#include <asm/pgtable-book3e.h>
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#include <asm/nohash/pgtable.h>
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#endif /* !CONFIG_PPC_BOOK3S */
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#ifndef __ASSEMBLY__
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