mirror of https://gitee.com/openkylin/linux.git
staging/rdma/hfi1: Fix code alignment
Fix code alignment to fix checkpatch check: CHECK: Alignment should match open parenthesis Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
parent
4d114fdd90
commit
17fb4f2923
File diff suppressed because it is too large
Load Diff
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@ -150,8 +150,8 @@ static int _opcode_stats_seq_show(struct seq_file *s, void *v)
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if (!n_packets && !n_bytes)
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return SEQ_SKIP;
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seq_printf(s, "%02llx %llu/%llu\n", i,
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(unsigned long long)n_packets,
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(unsigned long long)n_bytes);
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(unsigned long long)n_packets,
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(unsigned long long)n_bytes);
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return 0;
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}
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@ -246,7 +246,7 @@ __acquires(RCU)
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}
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static void *_qp_stats_seq_next(struct seq_file *s, void *iter_ptr,
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loff_t *pos)
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loff_t *pos)
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{
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struct qp_iter *iter = iter_ptr;
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@ -392,7 +392,7 @@ static ssize_t portnames_read(struct file *file, char __user *buf,
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/* read the per-port counters */
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static ssize_t portcntrs_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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u64 *counters;
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size_t avail;
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@ -413,7 +413,7 @@ static ssize_t portcntrs_debugfs_read(struct file *file, char __user *buf,
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* read the per-port QSFP data for ppd
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*/
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static ssize_t qsfp_debugfs_dump(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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struct hfi1_pportdata *ppd;
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char *tmp;
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@ -437,7 +437,7 @@ static ssize_t qsfp_debugfs_dump(struct file *file, char __user *buf,
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/* Do an i2c write operation on the chain for the given HFI. */
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static ssize_t __i2c_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos, u32 target)
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size_t count, loff_t *ppos, u32 target)
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{
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struct hfi1_pportdata *ppd;
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char *buff;
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@ -484,21 +484,21 @@ static ssize_t __i2c_debugfs_write(struct file *file, const char __user *buf,
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/* Do an i2c write operation on chain for HFI 0. */
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static ssize_t i2c1_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __i2c_debugfs_write(file, buf, count, ppos, 0);
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}
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/* Do an i2c write operation on chain for HFI 1. */
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static ssize_t i2c2_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __i2c_debugfs_write(file, buf, count, ppos, 1);
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}
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/* Do an i2c read operation on the chain for the given HFI. */
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static ssize_t __i2c_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos, u32 target)
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size_t count, loff_t *ppos, u32 target)
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{
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struct hfi1_pportdata *ppd;
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char *buff;
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@ -545,21 +545,21 @@ static ssize_t __i2c_debugfs_read(struct file *file, char __user *buf,
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/* Do an i2c read operation on chain for HFI 0. */
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static ssize_t i2c1_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __i2c_debugfs_read(file, buf, count, ppos, 0);
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}
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/* Do an i2c read operation on chain for HFI 1. */
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static ssize_t i2c2_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __i2c_debugfs_read(file, buf, count, ppos, 1);
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}
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/* Do a QSFP write operation on the i2c chain for the given HFI. */
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static ssize_t __qsfp_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos, u32 target)
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size_t count, loff_t *ppos, u32 target)
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{
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struct hfi1_pportdata *ppd;
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char *buff;
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@ -605,21 +605,21 @@ static ssize_t __qsfp_debugfs_write(struct file *file, const char __user *buf,
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/* Do a QSFP write operation on i2c chain for HFI 0. */
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static ssize_t qsfp1_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __qsfp_debugfs_write(file, buf, count, ppos, 0);
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}
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/* Do a QSFP write operation on i2c chain for HFI 1. */
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static ssize_t qsfp2_debugfs_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __qsfp_debugfs_write(file, buf, count, ppos, 1);
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}
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/* Do a QSFP read operation on the i2c chain for the given HFI. */
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static ssize_t __qsfp_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos, u32 target)
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size_t count, loff_t *ppos, u32 target)
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{
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struct hfi1_pportdata *ppd;
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char *buff;
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@ -665,14 +665,14 @@ static ssize_t __qsfp_debugfs_read(struct file *file, char __user *buf,
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/* Do a QSFP read operation on i2c chain for HFI 0. */
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static ssize_t qsfp1_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __qsfp_debugfs_read(file, buf, count, ppos, 0);
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}
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/* Do a QSFP read operation on i2c chain for HFI 1. */
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static ssize_t qsfp2_debugfs_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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size_t count, loff_t *ppos)
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{
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return __qsfp_debugfs_read(file, buf, count, ppos, 1);
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}
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@ -438,7 +438,7 @@ static void rcv_hdrerr(struct hfi1_ctxtdata *rcd, struct hfi1_pportdata *ppd,
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}
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static inline void init_packet(struct hfi1_ctxtdata *rcd,
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struct hfi1_packet *packet)
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struct hfi1_packet *packet)
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{
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packet->rsize = rcd->rcvhdrqentsize; /* words */
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packet->maxcnt = rcd->rcvhdrq_cnt * packet->rsize; /* words */
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@ -700,8 +700,9 @@ static inline int process_rcv_packet(struct hfi1_packet *packet, int thread)
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* The +2 is the size of the RHF.
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*/
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prefetch_range(packet->ebuf,
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packet->tlen - ((packet->rcd->rcvhdrqentsize -
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(rhf_hdrq_offset(packet->rhf) + 2)) * 4));
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packet->tlen - ((packet->rcd->rcvhdrqentsize -
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(rhf_hdrq_offset(packet->rhf)
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+ 2)) * 4));
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}
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/*
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@ -958,9 +959,9 @@ int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread)
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prescan_rxq(rcd, &packet);
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while (last == RCV_PKT_OK) {
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if (unlikely(dd->do_drop && atomic_xchg(&dd->drop_packet,
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DROP_PACKET_OFF) == DROP_PACKET_ON)) {
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if (unlikely(dd->do_drop &&
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atomic_xchg(&dd->drop_packet, DROP_PACKET_OFF) ==
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DROP_PACKET_ON)) {
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dd->do_drop = 0;
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/* On to the next packet */
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@ -990,8 +991,7 @@ int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread)
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if (seq != rcd->seq_cnt)
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last = RCV_PKT_DONE;
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if (needset) {
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dd_dev_info(dd,
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"Switching to NO_DMA_RTAIL\n");
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dd_dev_info(dd, "Switching to NO_DMA_RTAIL\n");
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set_all_nodma_rtail(dd);
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needset = 0;
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}
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@ -1234,7 +1234,7 @@ void hfi1_set_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
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if (atomic_inc_return(&ppd->led_override_timer_active) == 1) {
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/* Need to start timer */
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setup_timer(&ppd->led_override_timer, run_led_override,
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(unsigned long)ppd);
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(unsigned long)ppd);
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ppd->led_override_timer.expires = jiffies + 1;
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add_timer(&ppd->led_override_timer);
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@ -1271,8 +1271,8 @@ int hfi1_reset_device(int unit)
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if (!dd->kregbase || !(dd->flags & HFI1_PRESENT)) {
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dd_dev_info(dd,
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"Invalid unit number %u or not initialized or not present\n",
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unit);
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"Invalid unit number %u or not initialized or not present\n",
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unit);
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ret = -ENXIO;
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goto bail;
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}
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@ -1302,11 +1302,11 @@ int hfi1_reset_device(int unit)
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if (ret)
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dd_dev_err(dd,
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"Reinitialize unit %u after reset failed with %d\n",
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unit, ret);
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"Reinitialize unit %u after reset failed with %d\n",
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unit, ret);
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else
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dd_dev_info(dd, "Reinitialized unit %u after resetting\n",
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unit);
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unit);
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bail:
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return ret;
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@ -1363,7 +1363,7 @@ int process_receive_bypass(struct hfi1_packet *packet)
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handle_eflags(packet);
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dd_dev_err(packet->rcd->dd,
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"Bypass packets are not supported in normal operation. Dropping\n");
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"Bypass packets are not supported in normal operation. Dropping\n");
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return RHF_RCV_CONTINUE;
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}
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@ -1401,6 +1401,6 @@ int kdeth_process_eager(struct hfi1_packet *packet)
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int process_receive_invalid(struct hfi1_packet *packet)
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{
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dd_dev_err(packet->rcd->dd, "Invalid packet type %d. Dropping\n",
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rhf_rcv_type(packet->rhf));
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rhf_rcv_type(packet->rhf));
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return RHF_RCV_CONTINUE;
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}
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@ -115,11 +115,9 @@ static DEFINE_MUTEX(eprom_mutex);
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static void write_enable(struct hfi1_devdata *dd)
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{
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/* raise signal */
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write_csr(dd, ASIC_GPIO_OUT,
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read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N);
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write_csr(dd, ASIC_GPIO_OUT, read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N);
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/* raise enable */
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write_csr(dd, ASIC_GPIO_OE,
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read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N);
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write_csr(dd, ASIC_GPIO_OE, read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N);
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}
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/*
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@ -128,11 +126,9 @@ static void write_enable(struct hfi1_devdata *dd)
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static void write_disable(struct hfi1_devdata *dd)
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{
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/* lower signal */
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write_csr(dd, ASIC_GPIO_OUT,
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read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N);
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write_csr(dd, ASIC_GPIO_OUT, read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N);
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/* lower enable */
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write_csr(dd, ASIC_GPIO_OE,
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read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N);
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write_csr(dd, ASIC_GPIO_OE, read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N);
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}
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/*
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@ -210,8 +206,8 @@ static int erase_range(struct hfi1_devdata *dd, u32 start, u32 len)
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/* check the end points for the minimum erase */
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if ((start & MASK_4KB) || (end & MASK_4KB)) {
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dd_dev_err(dd,
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"%s: non-aligned range (0x%x,0x%x) for a 4KB erase\n",
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__func__, start, end);
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"%s: non-aligned range (0x%x,0x%x) for a 4KB erase\n",
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__func__, start, end);
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return -EINVAL;
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}
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@ -275,7 +271,7 @@ static int read_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
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for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
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read_page(dd, start + offset, buffer);
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if (copy_to_user((void __user *)(addr + offset),
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buffer, EP_PAGE_SIZE)) {
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buffer, EP_PAGE_SIZE)) {
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ret = -EFAULT;
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goto done;
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}
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@ -319,7 +315,7 @@ static int write_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
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for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
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if (copy_from_user(buffer, (void __user *)(addr + offset),
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EP_PAGE_SIZE)) {
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EP_PAGE_SIZE)) {
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ret = -EFAULT;
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goto done;
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}
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@ -385,13 +381,13 @@ int handle_eprom_command(struct file *fp, const struct hfi1_cmd *cmd)
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ret = acquire_hw_mutex(dd);
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if (ret) {
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dd_dev_err(dd,
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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goto done_asic;
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}
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dd_dev_info(dd, "%s: cmd: type %d, len 0x%x, addr 0x%016llx\n",
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__func__, cmd->type, cmd->len, cmd->addr);
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__func__, cmd->type, cmd->len, cmd->addr);
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switch (cmd->type) {
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case HFI1_CMD_EP_INFO:
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@ -402,7 +398,7 @@ int handle_eprom_command(struct file *fp, const struct hfi1_cmd *cmd)
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dev_id = read_device_id(dd);
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/* addr points to a u32 user buffer */
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if (copy_to_user((void __user *)cmd->addr, &dev_id,
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sizeof(u32)))
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sizeof(u32)))
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ret = -EFAULT;
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break;
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@ -430,7 +426,7 @@ int handle_eprom_command(struct file *fp, const struct hfi1_cmd *cmd)
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default:
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dd_dev_err(dd, "%s: unexpected command %d\n",
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__func__, cmd->type);
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__func__, cmd->type);
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ret = -EINVAL;
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break;
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}
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@ -464,19 +460,18 @@ int eprom_init(struct hfi1_devdata *dd)
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ret = acquire_hw_mutex(dd);
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if (ret) {
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dd_dev_err(dd,
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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"%s: unable to acquire hw mutex, no EPROM support\n",
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__func__);
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goto done_asic;
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}
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/* reset EPROM to be sure it is in a good state */
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/* set reset */
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write_csr(dd, ASIC_EEP_CTL_STAT,
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ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
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write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
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/* clear reset, set speed */
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write_csr(dd, ASIC_EEP_CTL_STAT,
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EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT);
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EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT);
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/* wake the device with command "release powerdown NoID" */
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write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
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|
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@ -1145,9 +1145,9 @@ static int user_init(struct file *fp)
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* has done it.
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*/
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if (fd->subctxt) {
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ret = wait_event_interruptible(uctxt->wait,
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!test_bit(HFI1_CTXT_MASTER_UNINIT,
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&uctxt->event_flags));
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ret = wait_event_interruptible(uctxt->wait, !test_bit(
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HFI1_CTXT_MASTER_UNINIT,
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&uctxt->event_flags));
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goto expected;
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}
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@ -1592,7 +1592,7 @@ static loff_t ui_lseek(struct file *filp, loff_t offset, int whence)
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/* NOTE: assumes unsigned long is 8 bytes */
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static ssize_t ui_read(struct file *filp, char __user *buf, size_t count,
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loff_t *f_pos)
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loff_t *f_pos)
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{
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struct hfi1_devdata *dd = filp->private_data;
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void __iomem *base = dd->kregbase;
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@ -382,8 +382,8 @@ static int invalid_header(struct hfi1_devdata *dd, const char *what,
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return 0;
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dd_dev_err(dd,
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"invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
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what, expected, actual);
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"invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
|
||||
what, expected, actual);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -393,13 +393,19 @@ static int invalid_header(struct hfi1_devdata *dd, const char *what,
|
|||
static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
|
||||
{
|
||||
/* verify CSS header fields (most sizes are in DW, so add /4) */
|
||||
if (invalid_header(dd, "module_type", css->module_type, CSS_MODULE_TYPE) ||
|
||||
invalid_header(dd, "header_len", css->header_len, (sizeof(struct firmware_file) / 4)) ||
|
||||
invalid_header(dd, "header_version", css->header_version, CSS_HEADER_VERSION) ||
|
||||
invalid_header(dd, "module_vendor", css->module_vendor, CSS_MODULE_VENDOR) ||
|
||||
if (invalid_header(dd, "module_type", css->module_type,
|
||||
CSS_MODULE_TYPE) ||
|
||||
invalid_header(dd, "header_len", css->header_len,
|
||||
(sizeof(struct firmware_file) / 4)) ||
|
||||
invalid_header(dd, "header_version", css->header_version,
|
||||
CSS_HEADER_VERSION) ||
|
||||
invalid_header(dd, "module_vendor", css->module_vendor,
|
||||
CSS_MODULE_VENDOR) ||
|
||||
invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) ||
|
||||
invalid_header(dd, "modulus_size", css->modulus_size, KEY_SIZE / 4) ||
|
||||
invalid_header(dd, "exponent_size", css->exponent_size, EXPONENT_SIZE / 4)) {
|
||||
invalid_header(dd, "modulus_size", css->modulus_size,
|
||||
KEY_SIZE / 4) ||
|
||||
invalid_header(dd, "exponent_size", css->exponent_size,
|
||||
EXPONENT_SIZE / 4)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
|
@ -414,8 +420,8 @@ static int payload_check(struct hfi1_devdata *dd, const char *name,
|
|||
/* make sure we have some payload */
|
||||
if (prefix_size >= file_size) {
|
||||
dd_dev_err(dd,
|
||||
"firmware \"%s\", size %ld, must be larger than %ld bytes\n",
|
||||
name, file_size, prefix_size);
|
||||
"firmware \"%s\", size %ld, must be larger than %ld bytes\n",
|
||||
name, file_size, prefix_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -491,7 +497,7 @@ static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
|
|||
|
||||
/* make sure there are bytes in the payload */
|
||||
ret = payload_check(dd, name, fdet->fw->size,
|
||||
sizeof(struct firmware_file));
|
||||
sizeof(struct firmware_file));
|
||||
if (ret == 0) {
|
||||
fdet->css_header = css;
|
||||
fdet->modulus = ff->modulus;
|
||||
|
@ -516,7 +522,7 @@ static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
|
|||
|
||||
/* make sure there are bytes in the payload */
|
||||
ret = payload_check(dd, name, fdet->fw->size,
|
||||
sizeof(struct augmented_firmware_file));
|
||||
sizeof(struct augmented_firmware_file));
|
||||
if (ret == 0) {
|
||||
fdet->css_header = css;
|
||||
fdet->modulus = aff->modulus;
|
||||
|
@ -531,9 +537,10 @@ static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
|
|||
} else {
|
||||
/* css->size check failed */
|
||||
dd_dev_err(dd,
|
||||
"invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
|
||||
fdet->fw->size / 4, (fdet->fw->size - AUGMENT_SIZE) / 4,
|
||||
css->size);
|
||||
"invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
|
||||
fdet->fw->size / 4,
|
||||
(fdet->fw->size - AUGMENT_SIZE) / 4,
|
||||
css->size);
|
||||
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
@ -696,7 +703,7 @@ static int obtain_firmware(struct hfi1_devdata *dd)
|
|||
if (platform_config_load) {
|
||||
platform_config = NULL;
|
||||
err = request_firmware(&platform_config, platform_config_name,
|
||||
&dd->pcidev->dev);
|
||||
&dd->pcidev->dev);
|
||||
if (err) {
|
||||
platform_config = NULL;
|
||||
goto done;
|
||||
|
@ -837,7 +844,7 @@ static int run_rsa(struct hfi1_devdata *dd, const char *who,
|
|||
>> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
|
||||
if (status != RSA_STATUS_IDLE) {
|
||||
dd_dev_err(dd, "%s security engine not idle - giving up\n",
|
||||
who);
|
||||
who);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
@ -874,7 +881,7 @@ static int run_rsa(struct hfi1_devdata *dd, const char *who,
|
|||
if (status == RSA_STATUS_IDLE) {
|
||||
/* should not happen */
|
||||
dd_dev_err(dd, "%s firmware security bad idle state\n",
|
||||
who);
|
||||
who);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
} else if (status == RSA_STATUS_DONE) {
|
||||
|
@ -908,8 +915,8 @@ static int run_rsa(struct hfi1_devdata *dd, const char *who,
|
|||
* is not keeping the error high.
|
||||
*/
|
||||
write_csr(dd, MISC_ERR_CLEAR,
|
||||
MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK
|
||||
| MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
|
||||
MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK |
|
||||
MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
|
||||
/*
|
||||
* All that is left are the current errors. Print warnings on
|
||||
* authorization failure details, if any. Firmware authorization
|
||||
|
@ -938,7 +945,8 @@ static void load_security_variables(struct hfi1_devdata *dd,
|
|||
write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
|
||||
/* Security variables d. Write the header */
|
||||
write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
|
||||
(u8 *)fdet->css_header, sizeof(struct css_header));
|
||||
(u8 *)fdet->css_header,
|
||||
sizeof(struct css_header));
|
||||
}
|
||||
|
||||
/* return the 8051 firmware state */
|
||||
|
@ -1018,7 +1026,7 @@ static int load_8051_firmware(struct hfi1_devdata *dd,
|
|||
|
||||
/* Firmware load steps 3-5 */
|
||||
ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr,
|
||||
fdet->firmware_len);
|
||||
fdet->firmware_len);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1045,13 +1053,13 @@ static int load_8051_firmware(struct hfi1_devdata *dd,
|
|||
ret = wait_fm_ready(dd, TIMEOUT_8051_START);
|
||||
if (ret) { /* timed out */
|
||||
dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
|
||||
get_firmware_state(dd));
|
||||
get_firmware_state(dd));
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
read_misc_status(dd, &ver_a, &ver_b);
|
||||
dd_dev_info(dd, "8051 firmware version %d.%d\n",
|
||||
(int)ver_b, (int)ver_a);
|
||||
(int)ver_b, (int)ver_a);
|
||||
dd->dc8051_ver = dc8051_ver(ver_b, ver_a);
|
||||
|
||||
return 0;
|
||||
|
@ -1066,11 +1074,11 @@ void sbus_request(struct hfi1_devdata *dd,
|
|||
u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
|
||||
{
|
||||
write_csr(dd, ASIC_CFG_SBUS_REQUEST,
|
||||
((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT)
|
||||
| ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT)
|
||||
| ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT)
|
||||
| ((u64)receiver_addr
|
||||
<< ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
|
||||
((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) |
|
||||
((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) |
|
||||
((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) |
|
||||
((u64)receiver_addr <<
|
||||
ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1088,14 +1096,14 @@ static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
|
|||
return;
|
||||
|
||||
dd_dev_info(dd, "Turning off spicos:%s%s\n",
|
||||
flags & SPICO_SBUS ? " SBus" : "",
|
||||
flags & SPICO_FABRIC ? " fabric" : "");
|
||||
flags & SPICO_SBUS ? " SBus" : "",
|
||||
flags & SPICO_FABRIC ? " fabric" : "");
|
||||
|
||||
write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
|
||||
/* disable SBus spico */
|
||||
if (flags & SPICO_SBUS)
|
||||
sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
|
||||
WRITE_SBUS_RECEIVER, 0x00000040);
|
||||
WRITE_SBUS_RECEIVER, 0x00000040);
|
||||
|
||||
/* disable the fabric serdes spicos */
|
||||
if (flags & SPICO_FABRIC)
|
||||
|
@ -1222,7 +1230,7 @@ static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
|
|||
/* step 5: download SerDes machine code */
|
||||
for (i = 0; i < fdet->firmware_len; i += 4) {
|
||||
sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
}
|
||||
/* step 6: IMEM override off */
|
||||
sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
|
||||
|
@ -1261,7 +1269,7 @@ static int load_sbus_firmware(struct hfi1_devdata *dd,
|
|||
/* step 5: download the SBus Master machine code */
|
||||
for (i = 0; i < fdet->firmware_len; i += 4) {
|
||||
sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
}
|
||||
/* step 6: set IMEM_CNTL_EN off */
|
||||
sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
|
||||
|
@ -1300,7 +1308,7 @@ static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
|
|||
*/
|
||||
for (i = 0; i < fdet->firmware_len; i += 4) {
|
||||
sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
*(u32 *)&fdet->firmware_ptr[i]);
|
||||
}
|
||||
/* step 5: disable XDMEM access */
|
||||
sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
|
||||
|
@ -1334,7 +1342,7 @@ static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
|
|||
* 23:16 BROADCAST_GROUP_2 (default 0xff)
|
||||
*/
|
||||
sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
|
||||
(u32)bg1 << 4 | (u32)bg2 << 16);
|
||||
(u32)bg1 << 4 | (u32)bg2 << 16);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1359,8 +1367,8 @@ int acquire_hw_mutex(struct hfi1_devdata *dd)
|
|||
|
||||
/* timed out */
|
||||
dd_dev_err(dd,
|
||||
"Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
|
||||
(u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
|
||||
"Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
|
||||
(u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
|
||||
|
||||
if (try == 0) {
|
||||
/* break mutex and retry */
|
||||
|
@ -1380,7 +1388,7 @@ void release_hw_mutex(struct hfi1_devdata *dd)
|
|||
void set_sbus_fast_mode(struct hfi1_devdata *dd)
|
||||
{
|
||||
write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
|
||||
ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
|
||||
ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
|
||||
}
|
||||
|
||||
void clear_sbus_fast_mode(struct hfi1_devdata *dd)
|
||||
|
@ -1410,9 +1418,9 @@ int load_firmware(struct hfi1_devdata *dd)
|
|||
set_sbus_fast_mode(dd);
|
||||
|
||||
set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
|
||||
fabric_serdes_broadcast[dd->hfi1_id],
|
||||
fabric_serdes_addrs[dd->hfi1_id],
|
||||
NUM_FABRIC_SERDES);
|
||||
fabric_serdes_broadcast[dd->hfi1_id],
|
||||
fabric_serdes_addrs[dd->hfi1_id],
|
||||
NUM_FABRIC_SERDES);
|
||||
turn_off_spicos(dd, SPICO_FABRIC);
|
||||
do {
|
||||
ret = load_fabric_serdes_firmware(dd, &fw_fabric);
|
||||
|
@ -1551,8 +1559,8 @@ int parse_platform_config(struct hfi1_devdata *dd)
|
|||
header2 = *(ptr + 1);
|
||||
if (header1 != ~header2) {
|
||||
dd_dev_info(dd, "%s: Failed validation at offset %ld\n",
|
||||
__func__, (ptr -
|
||||
(u32 *)dd->platform_config.data));
|
||||
__func__, (ptr - (u32 *)
|
||||
dd->platform_config.data));
|
||||
goto bail;
|
||||
}
|
||||
|
||||
|
@ -1595,9 +1603,10 @@ int parse_platform_config(struct hfi1_devdata *dd)
|
|||
break;
|
||||
default:
|
||||
dd_dev_info(dd,
|
||||
"%s: Unknown data table %d, offset %ld\n",
|
||||
__func__, table_type,
|
||||
(ptr - (u32 *)dd->platform_config.data));
|
||||
"%s: Unknown data table %d, offset %ld\n",
|
||||
__func__, table_type,
|
||||
(ptr - (u32 *)
|
||||
dd->platform_config.data));
|
||||
goto bail; /* We don't trust this file now */
|
||||
}
|
||||
pcfgcache->config_tables[table_type].table = ptr;
|
||||
|
@ -1630,7 +1639,7 @@ int parse_platform_config(struct hfi1_devdata *dd)
|
|||
|
||||
/* Calculate and check table crc */
|
||||
crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
|
||||
(table_length_dwords * 4));
|
||||
(table_length_dwords * 4));
|
||||
crc ^= ~(u32)0;
|
||||
|
||||
/* Jump the table */
|
||||
|
@ -1654,7 +1663,8 @@ int parse_platform_config(struct hfi1_devdata *dd)
|
|||
}
|
||||
|
||||
static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
|
||||
int field, u32 *field_len_bits, u32 *field_start_bits)
|
||||
int field, u32 *field_len_bits,
|
||||
u32 *field_start_bits)
|
||||
{
|
||||
struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
|
||||
u32 *src_ptr = NULL;
|
||||
|
@ -1714,8 +1724,9 @@ static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
|
|||
* @len: length of memory pointed by @data in bytes.
|
||||
*/
|
||||
int get_platform_config_field(struct hfi1_devdata *dd,
|
||||
enum platform_config_table_type_encoding table_type,
|
||||
int table_index, int field_index, u32 *data, u32 len)
|
||||
enum platform_config_table_type_encoding
|
||||
table_type, int table_index, int field_index,
|
||||
u32 *data, u32 len)
|
||||
{
|
||||
int ret = 0, wlen = 0, seek = 0;
|
||||
u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
|
||||
|
@ -1727,7 +1738,8 @@ int get_platform_config_field(struct hfi1_devdata *dd,
|
|||
return -EINVAL;
|
||||
|
||||
ret = get_platform_fw_field_metadata(dd, table_type, field_index,
|
||||
&field_len_bits, &field_start_bits);
|
||||
&field_len_bits,
|
||||
&field_start_bits);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
|
@ -1817,9 +1829,9 @@ int load_pcie_firmware(struct hfi1_devdata *dd)
|
|||
if (fw_pcie_serdes_load) {
|
||||
dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
|
||||
set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
|
||||
pcie_serdes_broadcast[dd->hfi1_id],
|
||||
pcie_serdes_addrs[dd->hfi1_id],
|
||||
NUM_PCIE_SERDES);
|
||||
pcie_serdes_broadcast[dd->hfi1_id],
|
||||
pcie_serdes_addrs[dd->hfi1_id],
|
||||
NUM_PCIE_SERDES);
|
||||
do {
|
||||
ret = load_pcie_serdes_firmware(dd, &fw_pcie);
|
||||
} while (retry_firmware(dd, ret));
|
||||
|
@ -1844,5 +1856,5 @@ void read_guid(struct hfi1_devdata *dd)
|
|||
|
||||
dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
|
||||
dd_dev_info(dd, "GUID %llx",
|
||||
(unsigned long long)dd->base_guid);
|
||||
(unsigned long long)dd->base_guid);
|
||||
}
|
||||
|
|
|
@ -1715,8 +1715,9 @@ void restore_pci_variables(struct hfi1_devdata *dd);
|
|||
int do_pcie_gen3_transition(struct hfi1_devdata *dd);
|
||||
int parse_platform_config(struct hfi1_devdata *dd);
|
||||
int get_platform_config_field(struct hfi1_devdata *dd,
|
||||
enum platform_config_table_type_encoding table_type,
|
||||
int table_index, int field_index, u32 *data, u32 len);
|
||||
enum platform_config_table_type_encoding
|
||||
table_type, int table_index, int field_index,
|
||||
u32 *data, u32 len);
|
||||
|
||||
const char *get_unit_name(int unit);
|
||||
const char *get_card_name(struct rvt_dev_info *rdi);
|
||||
|
|
|
@ -149,7 +149,7 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd)
|
|||
rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
|
||||
if (!rcd) {
|
||||
dd_dev_err(dd,
|
||||
"Unable to allocate kernel receive context, failing\n");
|
||||
"Unable to allocate kernel receive context, failing\n");
|
||||
goto nomem;
|
||||
}
|
||||
/*
|
||||
|
@ -170,7 +170,7 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd)
|
|||
rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
|
||||
if (!rcd->sc) {
|
||||
dd_dev_err(dd,
|
||||
"Unable to allocate kernel send context, failing\n");
|
||||
"Unable to allocate kernel send context, failing\n");
|
||||
dd->rcd[rcd->ctxt] = NULL;
|
||||
hfi1_free_ctxtdata(dd, rcd);
|
||||
goto nomem;
|
||||
|
@ -741,7 +741,7 @@ int hfi1_init(struct hfi1_devdata *dd, int reinit)
|
|||
lastfail = hfi1_setup_eagerbufs(rcd);
|
||||
if (lastfail)
|
||||
dd_dev_err(dd,
|
||||
"failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
|
||||
"failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
|
||||
}
|
||||
if (lastfail)
|
||||
ret = lastfail;
|
||||
|
@ -797,8 +797,8 @@ int hfi1_init(struct hfi1_devdata *dd, int reinit)
|
|||
lastfail = bringup_serdes(ppd);
|
||||
if (lastfail)
|
||||
dd_dev_info(dd,
|
||||
"Failed to bring up port %u\n",
|
||||
ppd->port);
|
||||
"Failed to bring up port %u\n",
|
||||
ppd->port);
|
||||
|
||||
/*
|
||||
* Set status even if port serdes is not initialized
|
||||
|
@ -1542,8 +1542,8 @@ int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
|
|||
|
||||
if (!rcd->rcvhdrq) {
|
||||
dd_dev_err(dd,
|
||||
"attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
|
||||
amt, rcd->ctxt);
|
||||
"attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
|
||||
amt, rcd->ctxt);
|
||||
goto bail;
|
||||
}
|
||||
|
||||
|
@ -1587,8 +1587,8 @@ int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
|
|||
|
||||
bail_free:
|
||||
dd_dev_err(dd,
|
||||
"attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
|
||||
rcd->ctxt);
|
||||
"attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
|
||||
rcd->ctxt);
|
||||
vfree(rcd->user_event_mask);
|
||||
rcd->user_event_mask = NULL;
|
||||
dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
|
||||
|
@ -1678,7 +1678,7 @@ int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
|
|||
if (rcd->egrbufs.rcvtid_size == round_mtu ||
|
||||
!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
|
||||
dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
|
||||
rcd->ctxt);
|
||||
rcd->ctxt);
|
||||
goto bail_rcvegrbuf_phys;
|
||||
}
|
||||
|
||||
|
@ -1760,14 +1760,14 @@ int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
|
|||
|
||||
for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
|
||||
hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
|
||||
rcd->egrbufs.rcvtids[idx].phys, order);
|
||||
rcd->egrbufs.rcvtids[idx].phys, order);
|
||||
cond_resched();
|
||||
}
|
||||
goto bail;
|
||||
|
||||
bail_rcvegrbuf_phys:
|
||||
for (idx = 0; idx < rcd->egrbufs.alloced &&
|
||||
rcd->egrbufs.buffers[idx].addr;
|
||||
rcd->egrbufs.buffers[idx].addr;
|
||||
idx++) {
|
||||
dma_free_coherent(&dd->pcidev->dev,
|
||||
rcd->egrbufs.buffers[idx].len,
|
||||
|
|
|
@ -135,18 +135,16 @@ void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup)
|
|||
set_up_vl15(dd, dd->vau, dd->vl15_init);
|
||||
assign_remote_cm_au_table(dd, dd->vcu);
|
||||
ppd->neighbor_guid =
|
||||
read_csr(dd,
|
||||
DC_DC8051_STS_REMOTE_GUID);
|
||||
read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
|
||||
ppd->neighbor_type =
|
||||
read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
|
||||
DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
|
||||
ppd->neighbor_port_number =
|
||||
read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
|
||||
DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
|
||||
dd_dev_info(dd,
|
||||
"Neighbor GUID: %llx Neighbor type %d\n",
|
||||
ppd->neighbor_guid,
|
||||
ppd->neighbor_type);
|
||||
DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
|
||||
dd_dev_info(dd, "Neighbor GUID: %llx Neighbor type %d\n",
|
||||
ppd->neighbor_guid,
|
||||
ppd->neighbor_type);
|
||||
}
|
||||
|
||||
/* physical link went up */
|
||||
|
|
|
@ -535,7 +535,7 @@ static int __subn_get_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
ibp = &ppd->ibport_data;
|
||||
|
||||
if (ppd->vls_supported / 2 > ARRAY_SIZE(pi->neigh_mtu.pvlx_to_mtu) ||
|
||||
ppd->vls_supported > ARRAY_SIZE(dd->vld)) {
|
||||
ppd->vls_supported > ARRAY_SIZE(dd->vld)) {
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
return reply((struct ib_mad_hdr *)smp);
|
||||
}
|
||||
|
@ -981,9 +981,8 @@ static int set_port_states(struct hfi1_pportdata *ppd, struct opa_smp *smp,
|
|||
link_state = HLS_DN_DOWNDEF;
|
||||
else if (phys_state == IB_PORTPHYSSTATE_POLLING) {
|
||||
link_state = HLS_DN_POLL;
|
||||
set_link_down_reason(ppd,
|
||||
OPA_LINKDOWN_REASON_FM_BOUNCE, 0,
|
||||
OPA_LINKDOWN_REASON_FM_BOUNCE);
|
||||
set_link_down_reason(ppd, OPA_LINKDOWN_REASON_FM_BOUNCE,
|
||||
0, OPA_LINKDOWN_REASON_FM_BOUNCE);
|
||||
} else if (phys_state == IB_PORTPHYSSTATE_DISABLED)
|
||||
link_state = HLS_DN_DISABLE;
|
||||
else {
|
||||
|
@ -1102,7 +1101,7 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
|
||||
/* Must be a valid unicast LID address. */
|
||||
if ((lid == 0 && ls_old > IB_PORT_INIT) ||
|
||||
lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) {
|
||||
lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) {
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
pr_warn("SubnSet(OPA_PortInfo) lid invalid 0x%x\n",
|
||||
lid);
|
||||
|
@ -1135,7 +1134,7 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
|
||||
/* Must be a valid unicast LID address. */
|
||||
if ((smlid == 0 && ls_old > IB_PORT_INIT) ||
|
||||
smlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) {
|
||||
smlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) {
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
pr_warn("SubnSet(OPA_PortInfo) smlid invalid 0x%x\n", smlid);
|
||||
} else if (smlid != ibp->rvp.sm_lid || msl != ibp->rvp.sm_sl) {
|
||||
|
@ -1185,7 +1184,9 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
if (lwe == OPA_LINK_WIDTH_RESET ||
|
||||
lwe == OPA_LINK_WIDTH_RESET_OLD) {
|
||||
set_link_width_downgrade_enabled(ppd,
|
||||
ppd->link_width_downgrade_supported);
|
||||
ppd->
|
||||
link_width_downgrade_supported
|
||||
);
|
||||
} else if ((lwe & ~ppd->link_width_downgrade_supported) == 0) {
|
||||
/* only set and apply if something changed */
|
||||
if (lwe != ppd->link_width_downgrade_enabled) {
|
||||
|
@ -1210,16 +1211,17 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
ibp->rvp.vl_high_limit);
|
||||
|
||||
if (ppd->vls_supported / 2 > ARRAY_SIZE(pi->neigh_mtu.pvlx_to_mtu) ||
|
||||
ppd->vls_supported > ARRAY_SIZE(dd->vld)) {
|
||||
ppd->vls_supported > ARRAY_SIZE(dd->vld)) {
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
return reply((struct ib_mad_hdr *)smp);
|
||||
}
|
||||
for (i = 0; i < ppd->vls_supported; i++) {
|
||||
if ((i % 2) == 0)
|
||||
mtu = enum_to_mtu((pi->neigh_mtu.pvlx_to_mtu[i / 2] >> 4)
|
||||
& 0xF);
|
||||
mtu = enum_to_mtu((pi->neigh_mtu.pvlx_to_mtu[i / 2] >>
|
||||
4) & 0xF);
|
||||
else
|
||||
mtu = enum_to_mtu(pi->neigh_mtu.pvlx_to_mtu[i / 2] & 0xF);
|
||||
mtu = enum_to_mtu(pi->neigh_mtu.pvlx_to_mtu[i / 2] &
|
||||
0xF);
|
||||
if (mtu == 0xffff) {
|
||||
pr_warn("SubnSet(OPA_PortInfo) mtu invalid %d (0x%x)\n",
|
||||
mtu,
|
||||
|
@ -1229,8 +1231,8 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
}
|
||||
if (dd->vld[i].mtu != mtu) {
|
||||
dd_dev_info(dd,
|
||||
"MTU change on vl %d from %d to %d\n",
|
||||
i, dd->vld[i].mtu, mtu);
|
||||
"MTU change on vl %d from %d to %d\n",
|
||||
i, dd->vld[i].mtu, mtu);
|
||||
dd->vld[i].mtu = mtu;
|
||||
call_set_mtu++;
|
||||
}
|
||||
|
@ -1243,8 +1245,8 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
mtu = 2048;
|
||||
if (dd->vld[15].mtu != mtu) {
|
||||
dd_dev_info(dd,
|
||||
"MTU change on vl 15 from %d to %d\n",
|
||||
dd->vld[15].mtu, mtu);
|
||||
"MTU change on vl 15 from %d to %d\n",
|
||||
dd->vld[15].mtu, mtu);
|
||||
dd->vld[15].mtu = mtu;
|
||||
call_set_mtu++;
|
||||
}
|
||||
|
@ -1260,7 +1262,7 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
|
|||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
} else {
|
||||
if (hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_OP_VLS,
|
||||
vls) == -EINVAL)
|
||||
vls) == -EINVAL)
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
}
|
||||
}
|
||||
|
@ -1806,7 +1808,7 @@ static int __subn_get_opa_cable_info(struct opa_smp *smp, u32 am, u8 *data,
|
|||
* addr and (addr + len - 1) are on the same "page"
|
||||
*/
|
||||
if (addr >= 4096 ||
|
||||
(__CI_PAGE_NUM(addr) != __CI_PAGE_NUM(addr + len - 1))) {
|
||||
(__CI_PAGE_NUM(addr) != __CI_PAGE_NUM(addr + len - 1))) {
|
||||
smp->status |= IB_SMP_INVALID_FIELD;
|
||||
return reply((struct ib_mad_hdr *)smp);
|
||||
}
|
||||
|
@ -2271,7 +2273,7 @@ enum error_info_selects {
|
|||
};
|
||||
|
||||
static int pma_get_opa_classportinfo(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u32 *resp_len)
|
||||
struct ib_device *ibdev, u32 *resp_len)
|
||||
{
|
||||
struct opa_class_port_info *p =
|
||||
(struct opa_class_port_info *)pmp->data;
|
||||
|
@ -2320,7 +2322,8 @@ static void a0_portstatus(struct hfi1_pportdata *ppd,
|
|||
}
|
||||
|
||||
static int pma_get_opa_portstatus(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
struct opa_port_status_req *req =
|
||||
(struct opa_port_status_req *)pmp->data;
|
||||
|
@ -2376,7 +2379,7 @@ static int pma_get_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
CNTR_INVALID_VL));
|
||||
rsp->port_multicast_xmit_pkts =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_MC_XMIT_PKTS,
|
||||
CNTR_INVALID_VL));
|
||||
CNTR_INVALID_VL));
|
||||
rsp->port_multicast_rcv_pkts =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_MC_RCV_PKTS,
|
||||
CNTR_INVALID_VL));
|
||||
|
@ -2405,7 +2408,7 @@ static int pma_get_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
}
|
||||
tmp = read_dev_cntr(dd, C_DC_SEQ_CRC_CNT, CNTR_INVALID_VL);
|
||||
tmp2 = tmp + read_dev_cntr(dd, C_DC_REINIT_FROM_PEER_CNT,
|
||||
CNTR_INVALID_VL);
|
||||
CNTR_INVALID_VL);
|
||||
if (tmp2 > (u32)UINT_MAX || tmp2 < tmp) {
|
||||
/* overflow/wrapped */
|
||||
rsp->link_error_recovery = cpu_to_be32(~0);
|
||||
|
@ -2420,7 +2423,7 @@ static int pma_get_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
cpu_to_be64(read_dev_cntr(dd, C_DC_FM_CFG_ERR,
|
||||
CNTR_INVALID_VL));
|
||||
rsp->link_downed = cpu_to_be32(read_port_cntr(ppd, C_SW_LINK_DOWN,
|
||||
CNTR_INVALID_VL));
|
||||
CNTR_INVALID_VL));
|
||||
|
||||
/* rsp->uncorrectable_errors is 8 bits wide, and it pegs at 0xff */
|
||||
tmp = read_dev_cntr(dd, C_DC_UNC_ERR, CNTR_INVALID_VL);
|
||||
|
@ -2442,27 +2445,27 @@ static int pma_get_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
|
||||
rsp->vls[vfi].port_vl_rcv_pkts =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RX_PKT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_data =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_FLIT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_pkts =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_PKT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_wait =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_WAIT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_rcv_fecn =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RCV_FCN_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_rcv_becn =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RCV_BCN_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
vlinfo++;
|
||||
vfi++;
|
||||
|
@ -2492,7 +2495,7 @@ static u64 get_error_counter_summary(struct ib_device *ibdev, u8 port,
|
|||
error_counter_summary += read_port_cntr(ppd, C_SW_XMIT_CSTR_ERR,
|
||||
CNTR_INVALID_VL);
|
||||
error_counter_summary += read_dev_cntr(dd, C_DC_RMT_PHY_ERR,
|
||||
CNTR_INVALID_VL);
|
||||
CNTR_INVALID_VL);
|
||||
/* local link integrity must be right-shifted by the lli resolution */
|
||||
tmp = read_dev_cntr(dd, C_DC_RX_REPLAY, CNTR_INVALID_VL);
|
||||
tmp += read_dev_cntr(dd, C_DC_TX_REPLAY, CNTR_INVALID_VL);
|
||||
|
@ -2502,10 +2505,10 @@ static u64 get_error_counter_summary(struct ib_device *ibdev, u8 port,
|
|||
tmp += read_dev_cntr(dd, C_DC_REINIT_FROM_PEER_CNT, CNTR_INVALID_VL);
|
||||
error_counter_summary += (tmp >> res_ler);
|
||||
error_counter_summary += read_dev_cntr(dd, C_DC_RCV_ERR,
|
||||
CNTR_INVALID_VL);
|
||||
CNTR_INVALID_VL);
|
||||
error_counter_summary += read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
|
||||
error_counter_summary += read_dev_cntr(dd, C_DC_FM_CFG_ERR,
|
||||
CNTR_INVALID_VL);
|
||||
CNTR_INVALID_VL);
|
||||
/* ppd->link_downed is a 32-bit value */
|
||||
error_counter_summary += read_port_cntr(ppd, C_SW_LINK_DOWN,
|
||||
CNTR_INVALID_VL);
|
||||
|
@ -2563,7 +2566,8 @@ static void pma_get_opa_port_dctrs(struct ib_device *ibdev,
|
|||
}
|
||||
|
||||
static int pma_get_opa_datacounters(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
struct opa_port_data_counters_msg *req =
|
||||
(struct opa_port_data_counters_msg *)pmp->data;
|
||||
|
@ -2650,35 +2654,35 @@ static int pma_get_opa_datacounters(struct opa_pma_mad *pmp,
|
|||
* any additional checks for vl.
|
||||
*/
|
||||
for_each_set_bit(vl, (unsigned long *)&(vl_select_mask),
|
||||
8 * sizeof(req->vl_select_mask)) {
|
||||
8 * sizeof(req->vl_select_mask)) {
|
||||
memset(vlinfo, 0, sizeof(*vlinfo));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_data =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_FLIT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_rcv_data =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RX_FLIT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_pkts =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_PKT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_rcv_pkts =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RX_PKT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_xmit_wait =
|
||||
cpu_to_be64(read_port_cntr(ppd, C_TX_WAIT_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
rsp->vls[vfi].port_vl_rcv_fecn =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RCV_FCN_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
rsp->vls[vfi].port_vl_rcv_becn =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_RCV_BCN_VL,
|
||||
idx_from_vl(vl)));
|
||||
idx_from_vl(vl)));
|
||||
|
||||
/* rsp->port_vl_xmit_time_cong is 0 for HFIs */
|
||||
/* rsp->port_vl_xmit_wasted_bw ??? */
|
||||
|
@ -2777,7 +2781,8 @@ static void pma_get_opa_port_ectrs(struct ib_device *ibdev,
|
|||
}
|
||||
|
||||
static int pma_get_opa_porterrors(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
size_t response_data_size;
|
||||
struct _port_ectrs *rsp;
|
||||
|
@ -2820,7 +2825,7 @@ static int pma_get_opa_porterrors(struct opa_pma_mad *pmp,
|
|||
*/
|
||||
port_mask = be64_to_cpu(req->port_select_mask[3]);
|
||||
port_num = find_first_bit((unsigned long *)&port_mask,
|
||||
sizeof(port_mask));
|
||||
sizeof(port_mask));
|
||||
|
||||
if (port_num != port) {
|
||||
pmp->mad_hdr.status |= IB_SMP_INVALID_FIELD;
|
||||
|
@ -2842,7 +2847,7 @@ static int pma_get_opa_porterrors(struct opa_pma_mad *pmp,
|
|||
CNTR_INVALID_VL));
|
||||
rsp->fm_config_errors =
|
||||
cpu_to_be64(read_dev_cntr(dd, C_DC_FM_CFG_ERR,
|
||||
CNTR_INVALID_VL));
|
||||
CNTR_INVALID_VL));
|
||||
tmp = read_dev_cntr(dd, C_DC_UNC_ERR, CNTR_INVALID_VL);
|
||||
|
||||
rsp->uncorrectable_errors = tmp < 0x100 ? (tmp & 0xff) : 0xff;
|
||||
|
@ -2950,7 +2955,8 @@ static int pma_get_ib_portcounters(struct ib_pma_mad *pmp,
|
|||
}
|
||||
|
||||
static int pma_get_opa_errorinfo(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
size_t response_data_size;
|
||||
struct _port_ei *rsp;
|
||||
|
@ -3000,9 +3006,9 @@ static int pma_get_opa_errorinfo(struct opa_pma_mad *pmp,
|
|||
rsp->port_rcv_ei.status_and_code =
|
||||
dd->err_info_rcvport.status_and_code;
|
||||
memcpy(&rsp->port_rcv_ei.ei.ei1to12.packet_flit1,
|
||||
&dd->err_info_rcvport.packet_flit1, sizeof(u64));
|
||||
&dd->err_info_rcvport.packet_flit1, sizeof(u64));
|
||||
memcpy(&rsp->port_rcv_ei.ei.ei1to12.packet_flit2,
|
||||
&dd->err_info_rcvport.packet_flit2, sizeof(u64));
|
||||
&dd->err_info_rcvport.packet_flit2, sizeof(u64));
|
||||
|
||||
/* ExcessiverBufferOverrunInfo */
|
||||
reg = read_csr(dd, RCV_ERR_INFO);
|
||||
|
@ -3047,7 +3053,8 @@ static int pma_get_opa_errorinfo(struct opa_pma_mad *pmp,
|
|||
}
|
||||
|
||||
static int pma_set_opa_portstatus(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
struct opa_clear_port_status *req =
|
||||
(struct opa_clear_port_status *)pmp->data;
|
||||
|
@ -3131,7 +3138,7 @@ static int pma_set_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
if (counter_select & CS_LINK_ERROR_RECOVERY) {
|
||||
write_dev_cntr(dd, C_DC_SEQ_CRC_CNT, CNTR_INVALID_VL, 0);
|
||||
write_dev_cntr(dd, C_DC_REINIT_FROM_PEER_CNT,
|
||||
CNTR_INVALID_VL, 0);
|
||||
CNTR_INVALID_VL, 0);
|
||||
}
|
||||
|
||||
if (counter_select & CS_PORT_RCV_ERRORS)
|
||||
|
@ -3194,7 +3201,8 @@ static int pma_set_opa_portstatus(struct opa_pma_mad *pmp,
|
|||
}
|
||||
|
||||
static int pma_set_opa_errorinfo(struct opa_pma_mad *pmp,
|
||||
struct ib_device *ibdev, u8 port, u32 *resp_len)
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
struct _port_ei *rsp;
|
||||
struct opa_port_error_info_msg *req;
|
||||
|
@ -3295,9 +3303,8 @@ static int __subn_get_opa_cong_info(struct opa_smp *smp, u32 am, u8 *data,
|
|||
}
|
||||
|
||||
static int __subn_get_opa_cong_setting(struct opa_smp *smp, u32 am,
|
||||
u8 *data,
|
||||
struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
u8 *data, struct ib_device *ibdev,
|
||||
u8 port, u32 *resp_len)
|
||||
{
|
||||
int i;
|
||||
struct opa_congestion_setting_attr *p =
|
||||
|
@ -3402,7 +3409,7 @@ static int __subn_get_opa_hfi1_cong_log(struct opa_smp *smp, u32 am,
|
|||
continue;
|
||||
memcpy(cong_log->events[i].local_qp_cn_entry, &cce->lqpn, 3);
|
||||
memcpy(cong_log->events[i].remote_qp_number_cn_entry,
|
||||
&cce->rqpn, 3);
|
||||
&cce->rqpn, 3);
|
||||
cong_log->events[i].sl_svc_type_cn_entry =
|
||||
((cce->sl & 0x1f) << 3) | (cce->svc_type & 0x7);
|
||||
cong_log->events[i].remote_lid_cn_entry =
|
||||
|
@ -3584,8 +3591,8 @@ static int __subn_get_opa_led_info(struct opa_smp *smp, u32 am, u8 *data,
|
|||
|
||||
reg = read_csr(dd, DCC_CFG_LED_CNTRL);
|
||||
if ((reg & DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK) &&
|
||||
((reg & DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK) == 0xf))
|
||||
p->rsvd_led_mask = cpu_to_be32(OPA_LED_MASK);
|
||||
((reg & DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK) == 0xf))
|
||||
p->rsvd_led_mask = cpu_to_be32(OPA_LED_MASK);
|
||||
|
||||
if (resp_len)
|
||||
*resp_len += sizeof(struct opa_led_info);
|
||||
|
@ -3653,7 +3660,7 @@ static int subn_get_opa_sma(__be16 attr_id, struct opa_smp *smp, u32 am,
|
|||
break;
|
||||
case OPA_ATTRIB_ID_SC_TO_VLNT_MAP:
|
||||
ret = __subn_get_opa_sc_to_vlnt(smp, am, data, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_ATTRIB_ID_PORT_STATE_INFO:
|
||||
ret = __subn_get_opa_psi(smp, am, data, ibdev, port,
|
||||
|
@ -3735,7 +3742,7 @@ static int subn_set_opa_sma(__be16 attr_id, struct opa_smp *smp, u32 am,
|
|||
break;
|
||||
case OPA_ATTRIB_ID_SC_TO_VLNT_MAP:
|
||||
ret = __subn_set_opa_sc_to_vlnt(smp, am, data, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_ATTRIB_ID_PORT_STATE_INFO:
|
||||
ret = __subn_set_opa_psi(smp, am, data, ibdev, port,
|
||||
|
@ -4092,10 +4099,10 @@ static int process_subn(struct ib_device *ibdev, int mad_flags,
|
|||
port_num && port_num <= ibdev->phys_port_cnt &&
|
||||
port != port_num)
|
||||
(void)check_mkey(to_iport(ibdev, port_num),
|
||||
(struct ib_mad_hdr *)smp, 0,
|
||||
smp->mkey,
|
||||
(__force __be32)smp->dr_slid,
|
||||
smp->return_path, smp->hop_cnt);
|
||||
(struct ib_mad_hdr *)smp, 0,
|
||||
smp->mkey,
|
||||
(__force __be32)smp->dr_slid,
|
||||
smp->return_path, smp->hop_cnt);
|
||||
ret = IB_MAD_RESULT_FAILURE;
|
||||
return ret;
|
||||
}
|
||||
|
@ -4203,19 +4210,19 @@ static int process_perf_opa(struct ib_device *ibdev, u8 port,
|
|||
break;
|
||||
case OPA_PM_ATTRIB_ID_PORT_STATUS:
|
||||
ret = pma_get_opa_portstatus(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_PM_ATTRIB_ID_DATA_PORT_COUNTERS:
|
||||
ret = pma_get_opa_datacounters(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_PM_ATTRIB_ID_ERROR_PORT_COUNTERS:
|
||||
ret = pma_get_opa_porterrors(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_PM_ATTRIB_ID_ERROR_INFO:
|
||||
ret = pma_get_opa_errorinfo(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
default:
|
||||
pmp->mad_hdr.status |= IB_SMP_UNSUP_METH_ATTR;
|
||||
|
@ -4228,11 +4235,11 @@ static int process_perf_opa(struct ib_device *ibdev, u8 port,
|
|||
switch (pmp->mad_hdr.attr_id) {
|
||||
case OPA_PM_ATTRIB_ID_CLEAR_PORT_STATUS:
|
||||
ret = pma_set_opa_portstatus(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
case OPA_PM_ATTRIB_ID_ERROR_INFO:
|
||||
ret = pma_set_opa_errorinfo(pmp, ibdev, port,
|
||||
resp_len);
|
||||
resp_len);
|
||||
break;
|
||||
default:
|
||||
pmp->mad_hdr.status |= IB_SMP_UNSUP_METH_ATTR;
|
||||
|
|
|
@ -217,10 +217,9 @@ int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev,
|
|||
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl);
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &dd->pcie_lnkctl);
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
|
||||
&dd->pcie_devctl2);
|
||||
&dd->pcie_devctl2);
|
||||
pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
|
||||
pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
|
||||
&dd->pci_lnkctl3);
|
||||
pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, &dd->pci_lnkctl3);
|
||||
pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2);
|
||||
|
||||
return 0;
|
||||
|
@ -271,7 +270,7 @@ void hfi1_pcie_flr(struct hfi1_devdata *dd)
|
|||
|
||||
clear:
|
||||
pcie_capability_set_word(dd->pcidev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_BCR_FLR);
|
||||
PCI_EXP_DEVCTL_BCR_FLR);
|
||||
/* PCIe spec requires the function to be back within 100ms */
|
||||
msleep(100);
|
||||
}
|
||||
|
@ -377,8 +376,8 @@ int pcie_speeds(struct hfi1_devdata *dd)
|
|||
pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
|
||||
if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) {
|
||||
dd_dev_info(dd,
|
||||
"This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
|
||||
linkcap & PCI_EXP_LNKCAP_SLS);
|
||||
"This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
|
||||
linkcap & PCI_EXP_LNKCAP_SLS);
|
||||
dd->link_gen3_capable = 0;
|
||||
}
|
||||
|
||||
|
@ -432,19 +431,15 @@ void hfi1_enable_intx(struct pci_dev *pdev)
|
|||
void restore_pci_variables(struct hfi1_devdata *dd)
|
||||
{
|
||||
pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
|
||||
pci_write_config_dword(dd->pcidev,
|
||||
PCI_BASE_ADDRESS_0, dd->pcibar0);
|
||||
pci_write_config_dword(dd->pcidev,
|
||||
PCI_BASE_ADDRESS_1, dd->pcibar1);
|
||||
pci_write_config_dword(dd->pcidev,
|
||||
PCI_ROM_ADDRESS, dd->pci_rom);
|
||||
pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, dd->pcibar0);
|
||||
pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, dd->pcibar1);
|
||||
pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, dd->pcie_devctl);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, dd->pcie_lnkctl);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
|
||||
dd->pcie_devctl2);
|
||||
dd->pcie_devctl2);
|
||||
pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
|
||||
pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
|
||||
dd->pci_lnkctl3);
|
||||
pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, dd->pci_lnkctl3);
|
||||
pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2);
|
||||
}
|
||||
|
||||
|
@ -746,21 +741,22 @@ static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
|
|||
c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
|
||||
c_plus1 = eq[i][POST] / div;
|
||||
pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
|
||||
eq_value(c_minus1, c0, c_plus1));
|
||||
eq_value(c_minus1, c0, c_plus1));
|
||||
/* check if these coefficients violate EQ rules */
|
||||
pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL105,
|
||||
&violation);
|
||||
&violation);
|
||||
if (violation
|
||||
& PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
|
||||
if (hit_error == 0) {
|
||||
dd_dev_err(dd,
|
||||
"Gen3 EQ Table Coefficient rule violations\n");
|
||||
"Gen3 EQ Table Coefficient rule violations\n");
|
||||
dd_dev_err(dd, " prec attn post\n");
|
||||
}
|
||||
dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
|
||||
i, (u32)eq[i][0], (u32)eq[i][1], (u32)eq[i][2]);
|
||||
i, (u32)eq[i][0], (u32)eq[i][1],
|
||||
(u32)eq[i][2]);
|
||||
dd_dev_err(dd, " %02x %02x %02x\n",
|
||||
(u32)c_minus1, (u32)c0, (u32)c_plus1);
|
||||
(u32)c_minus1, (u32)c0, (u32)c_plus1);
|
||||
hit_error = 1;
|
||||
}
|
||||
}
|
||||
|
@ -815,8 +811,8 @@ static int trigger_sbr(struct hfi1_devdata *dd)
|
|||
list_for_each_entry(pdev, &dev->bus->devices, bus_list)
|
||||
if (pdev != dev) {
|
||||
dd_dev_err(dd,
|
||||
"%s: another device is on the same bus\n",
|
||||
__func__);
|
||||
"%s: another device is on the same bus\n",
|
||||
__func__);
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
|
@ -840,8 +836,8 @@ static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
|
|||
u16 code, u16 data)
|
||||
{
|
||||
write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
|
||||
(((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT)
|
||||
| ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
|
||||
(((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
|
||||
((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -851,14 +847,13 @@ static void arm_gasket_logic(struct hfi1_devdata *dd)
|
|||
{
|
||||
u64 reg;
|
||||
|
||||
reg = (((u64)1 << dd->hfi1_id)
|
||||
<< ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT)
|
||||
| ((u64)pcie_serdes_broadcast[dd->hfi1_id]
|
||||
<< ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT
|
||||
| ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK
|
||||
| ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK)
|
||||
<< ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT
|
||||
);
|
||||
reg = (((u64)1 << dd->hfi1_id) <<
|
||||
ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
|
||||
((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
|
||||
ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
|
||||
ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
|
||||
((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
|
||||
ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
|
||||
write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
|
||||
/* read back to push the write */
|
||||
read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
|
||||
|
@ -982,8 +977,8 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
/* if already at target speed, done (unless forced) */
|
||||
if (dd->lbus_speed == target_speed) {
|
||||
dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
|
||||
pcie_target,
|
||||
pcie_force ? "re-doing anyway" : "skipping");
|
||||
pcie_target,
|
||||
pcie_force ? "re-doing anyway" : "skipping");
|
||||
if (!pcie_force)
|
||||
return 0;
|
||||
}
|
||||
|
@ -1087,8 +1082,10 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
default_pset = DEFAULT_MCP_PSET;
|
||||
}
|
||||
pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
|
||||
(fs << PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT)
|
||||
| (lf << PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
|
||||
(fs <<
|
||||
PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
|
||||
(lf <<
|
||||
PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
|
||||
ret = load_eq_table(dd, eq, fs, div);
|
||||
if (ret)
|
||||
goto done;
|
||||
|
@ -1102,15 +1099,15 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
pcie_pset = default_pset;
|
||||
if (pcie_pset > 10) { /* valid range is 0-10, inclusive */
|
||||
dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
|
||||
__func__, pcie_pset, default_pset);
|
||||
__func__, pcie_pset, default_pset);
|
||||
pcie_pset = default_pset;
|
||||
}
|
||||
dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset);
|
||||
pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
|
||||
((1 << pcie_pset)
|
||||
<< PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT)
|
||||
| PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK
|
||||
| PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
|
||||
((1 << pcie_pset) <<
|
||||
PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
|
||||
PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
|
||||
PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
|
||||
|
||||
/*
|
||||
* step 5b: Do post firmware download steps via SBus
|
||||
|
@ -1165,13 +1162,13 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
parent = dd->pcidev->bus->self;
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
|
||||
dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
|
||||
(u32)lnkctl2);
|
||||
(u32)lnkctl2);
|
||||
/* only write to parent if target is not as high as ours */
|
||||
if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) {
|
||||
lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
|
||||
lnkctl2 |= target_vector;
|
||||
dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
|
||||
(u32)lnkctl2);
|
||||
(u32)lnkctl2);
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL2, lnkctl2);
|
||||
} else {
|
||||
dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
|
||||
|
@ -1180,11 +1177,11 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
dd_dev_info(dd, "%s: setting target link speed\n", __func__);
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
|
||||
dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
|
||||
(u32)lnkctl2);
|
||||
(u32)lnkctl2);
|
||||
lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
|
||||
lnkctl2 |= target_vector;
|
||||
dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
|
||||
(u32)lnkctl2);
|
||||
(u32)lnkctl2);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
|
||||
|
||||
/* step 5h: arm gasket logic */
|
||||
|
@ -1221,8 +1218,8 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
|
||||
if (ret) {
|
||||
dd_dev_info(dd,
|
||||
"%s: read of VendorID failed after SBR, err %d\n",
|
||||
__func__, ret);
|
||||
"%s: read of VendorID failed after SBR, err %d\n",
|
||||
__func__, ret);
|
||||
return_error = 1;
|
||||
goto done;
|
||||
}
|
||||
|
@ -1273,8 +1270,8 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
& ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
|
||||
if ((status & (1 << dd->hfi1_id)) == 0) {
|
||||
dd_dev_err(dd,
|
||||
"%s: gasket status 0x%x, expecting 0x%x\n",
|
||||
__func__, status, 1 << dd->hfi1_id);
|
||||
"%s: gasket status 0x%x, expecting 0x%x\n",
|
||||
__func__, status, 1 << dd->hfi1_id);
|
||||
ret = -EIO;
|
||||
goto done;
|
||||
}
|
||||
|
@ -1291,13 +1288,13 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
|
|||
/* update our link information cache */
|
||||
update_lbus_info(dd);
|
||||
dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
|
||||
dd->lbus_info);
|
||||
dd->lbus_info);
|
||||
|
||||
if (dd->lbus_speed != target_speed) { /* not target */
|
||||
/* maybe retry */
|
||||
do_retry = retry_count < pcie_retry;
|
||||
dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n",
|
||||
pcie_target, do_retry ? ", retrying" : "");
|
||||
pcie_target, do_retry ? ", retrying" : "");
|
||||
retry_count++;
|
||||
if (do_retry) {
|
||||
msleep(100); /* allow time to settle */
|
||||
|
|
|
@ -511,7 +511,7 @@ static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
|
|||
sci = &dd->send_contexts[sw_index];
|
||||
if (!sci->allocated) {
|
||||
dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
|
||||
__func__, sw_index, hw_context);
|
||||
__func__, sw_index, hw_context);
|
||||
}
|
||||
sci->allocated = 0;
|
||||
dd->hw_to_sw[hw_context] = INVALID_SCI;
|
||||
|
@ -627,7 +627,7 @@ void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
|
|||
& SC(CREDIT_CTRL_THRESHOLD_MASK))
|
||||
<< SC(CREDIT_CTRL_THRESHOLD_SHIFT));
|
||||
write_kctxt_csr(sc->dd, sc->hw_context,
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
|
||||
/* force a credit return on change to avoid a possible stall */
|
||||
force_return = 1;
|
||||
|
@ -765,9 +765,9 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
|
|||
|
||||
/* set the default partition key */
|
||||
write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
|
||||
(DEFAULT_PKEY &
|
||||
SC(CHECK_PARTITION_KEY_VALUE_MASK))
|
||||
<< SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
|
||||
(DEFAULT_PKEY &
|
||||
SC(CHECK_PARTITION_KEY_VALUE_MASK)) <<
|
||||
SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
|
||||
|
||||
/* per context type checks */
|
||||
if (type == SC_USER) {
|
||||
|
@ -780,8 +780,8 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
|
|||
|
||||
/* set the send context check opcode mask and value */
|
||||
write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
|
||||
((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
|
||||
((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
|
||||
((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
|
||||
((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
|
||||
|
||||
/* set up credit return */
|
||||
reg = pa & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
|
||||
|
@ -799,7 +799,7 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
|
|||
thresh = sc_percent_to_threshold(sc, 50);
|
||||
} else if (type == SC_USER) {
|
||||
thresh = sc_percent_to_threshold(sc,
|
||||
user_credit_return_threshold);
|
||||
user_credit_return_threshold);
|
||||
} else { /* kernel */
|
||||
thresh = sc_mtu_to_threshold(sc, hfi1_max_mtu, hdrqentsize);
|
||||
}
|
||||
|
@ -972,11 +972,11 @@ static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
|
|||
if (loop > 500) {
|
||||
/* timed out - bounce the link */
|
||||
dd_dev_err(dd,
|
||||
"%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
|
||||
__func__, sc->sw_index,
|
||||
sc->hw_context, (u32)reg);
|
||||
"%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
|
||||
__func__, sc->sw_index,
|
||||
sc->hw_context, (u32)reg);
|
||||
queue_work(dd->pport->hfi1_wq,
|
||||
&dd->pport->link_bounce_work);
|
||||
&dd->pport->link_bounce_work);
|
||||
break;
|
||||
}
|
||||
loop++;
|
||||
|
@ -1022,7 +1022,7 @@ int sc_restart(struct send_context *sc)
|
|||
return -EINVAL;
|
||||
|
||||
dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
|
||||
sc->hw_context);
|
||||
sc->hw_context);
|
||||
|
||||
/*
|
||||
* Step 1: Wait for the context to actually halt.
|
||||
|
@ -1037,7 +1037,7 @@ int sc_restart(struct send_context *sc)
|
|||
break;
|
||||
if (loop > 100) {
|
||||
dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
|
||||
__func__, sc->sw_index, sc->hw_context);
|
||||
__func__, sc->sw_index, sc->hw_context);
|
||||
return -ETIME;
|
||||
}
|
||||
loop++;
|
||||
|
@ -1063,9 +1063,9 @@ int sc_restart(struct send_context *sc)
|
|||
break;
|
||||
if (loop > 100) {
|
||||
dd_dev_err(dd,
|
||||
"%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
|
||||
__func__, sc->sw_index,
|
||||
sc->hw_context, count);
|
||||
"%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
|
||||
__func__, sc->sw_index,
|
||||
sc->hw_context, count);
|
||||
}
|
||||
loop++;
|
||||
udelay(1);
|
||||
|
@ -1178,18 +1178,18 @@ void pio_reset_all(struct hfi1_devdata *dd)
|
|||
if (ret == -EIO) {
|
||||
/* clear the error */
|
||||
write_csr(dd, SEND_PIO_ERR_CLEAR,
|
||||
SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
|
||||
SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
|
||||
}
|
||||
|
||||
/* reset init all */
|
||||
write_csr(dd, SEND_PIO_INIT_CTXT,
|
||||
SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
|
||||
SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
|
||||
udelay(2);
|
||||
ret = pio_init_wait_progress(dd);
|
||||
if (ret < 0) {
|
||||
dd_dev_err(dd,
|
||||
"PIO send context init %s while initializing all PIO blocks\n",
|
||||
ret == -ETIMEDOUT ? "is stuck" : "had an error");
|
||||
"PIO send context init %s while initializing all PIO blocks\n",
|
||||
ret == -ETIMEDOUT ? "is stuck" : "had an error");
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1237,8 +1237,7 @@ int sc_enable(struct send_context *sc)
|
|||
*/
|
||||
reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
|
||||
if (reg)
|
||||
write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR),
|
||||
reg);
|
||||
write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
|
||||
|
||||
/*
|
||||
* The HW PIO initialization engine can handle only one init
|
||||
|
@ -1296,7 +1295,7 @@ void sc_return_credits(struct send_context *sc)
|
|||
|
||||
/* a 0->1 transition schedules a credit return */
|
||||
write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
|
||||
SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
|
||||
SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
|
||||
/*
|
||||
* Ensure that the write is flushed and the credit return is
|
||||
* scheduled. We care more about the 0 -> 1 transition.
|
||||
|
@ -1322,7 +1321,7 @@ void sc_drop(struct send_context *sc)
|
|||
return;
|
||||
|
||||
dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
|
||||
__func__, sc->sw_index, sc->hw_context);
|
||||
__func__, sc->sw_index, sc->hw_context);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1472,7 +1471,7 @@ void sc_add_credit_return_intr(struct send_context *sc)
|
|||
if (sc->credit_intr_count == 0) {
|
||||
sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
|
||||
write_kctxt_csr(sc->dd, sc->hw_context,
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
}
|
||||
sc->credit_intr_count++;
|
||||
spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
|
||||
|
@ -1494,7 +1493,7 @@ void sc_del_credit_return_intr(struct send_context *sc)
|
|||
if (sc->credit_intr_count == 0) {
|
||||
sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
|
||||
write_kctxt_csr(sc->dd, sc->hw_context,
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
SC(CREDIT_CTRL), sc->credit_ctrl);
|
||||
}
|
||||
spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
|
||||
}
|
||||
|
@ -1667,7 +1666,7 @@ void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
|
|||
sw_index = dd->hw_to_sw[hw_context];
|
||||
if (unlikely(sw_index >= dd->num_send_contexts)) {
|
||||
dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
|
||||
__func__, hw_context, sw_index);
|
||||
__func__, hw_context, sw_index);
|
||||
goto done;
|
||||
}
|
||||
sc = dd->send_contexts[sw_index].sc;
|
||||
|
@ -1680,8 +1679,8 @@ void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
|
|||
sw_index = dd->hw_to_sw[gc];
|
||||
if (unlikely(sw_index >= dd->num_send_contexts)) {
|
||||
dd_dev_err(dd,
|
||||
"%s: invalid hw (%u) to sw (%u) mapping\n",
|
||||
__func__, hw_context, sw_index);
|
||||
"%s: invalid hw (%u) to sw (%u) mapping\n",
|
||||
__func__, hw_context, sw_index);
|
||||
continue;
|
||||
}
|
||||
sc_release_update(dd->send_contexts[sw_index].sc);
|
||||
|
@ -2009,8 +2008,8 @@ int init_credit_return(struct hfi1_devdata *dd)
|
|||
if (!dd->cr_base[i].va) {
|
||||
set_dev_node(&dd->pcidev->dev, dd->node);
|
||||
dd_dev_err(dd,
|
||||
"Unable to allocate credit return DMA range for NUMA %d\n",
|
||||
i);
|
||||
"Unable to allocate credit return DMA range for NUMA %d\n",
|
||||
i);
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
@ -2034,10 +2033,10 @@ void free_credit_return(struct hfi1_devdata *dd)
|
|||
for (i = 0; i < num_numa; i++) {
|
||||
if (dd->cr_base[i].va) {
|
||||
dma_free_coherent(&dd->pcidev->dev,
|
||||
TXE_NUM_CONTEXTS
|
||||
* sizeof(struct credit_return),
|
||||
dd->cr_base[i].va,
|
||||
dd->cr_base[i].pa);
|
||||
TXE_NUM_CONTEXTS *
|
||||
sizeof(struct credit_return),
|
||||
dd->cr_base[i].va,
|
||||
dd->cr_base[i].pa);
|
||||
}
|
||||
}
|
||||
kfree(dd->cr_base);
|
||||
|
|
|
@ -289,7 +289,7 @@ void sc_flush(struct send_context *sc);
|
|||
void sc_drop(struct send_context *sc);
|
||||
void sc_stop(struct send_context *sc, int bit);
|
||||
struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
|
||||
pio_release_cb cb, void *arg);
|
||||
pio_release_cb cb, void *arg);
|
||||
void sc_release_update(struct send_context *sc);
|
||||
void sc_return_credits(struct send_context *sc);
|
||||
void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
|
||||
|
@ -322,7 +322,7 @@ void pio_send_control(struct hfi1_devdata *dd, int op);
|
|||
void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
|
||||
const void *from, size_t count);
|
||||
void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
|
||||
const void *from, size_t nbytes);
|
||||
const void *from, size_t nbytes);
|
||||
void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
|
||||
void seg_pio_copy_end(struct pio_buf *pbuf);
|
||||
|
||||
|
|
|
@ -200,7 +200,7 @@ void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
|
|||
* o nbytes must not span a QW boundary
|
||||
*/
|
||||
static inline void read_low_bytes(struct pio_buf *pbuf, const void *from,
|
||||
unsigned int nbytes)
|
||||
unsigned int nbytes)
|
||||
{
|
||||
unsigned long off;
|
||||
|
||||
|
@ -227,7 +227,7 @@ static inline void read_low_bytes(struct pio_buf *pbuf, const void *from,
|
|||
* o nbytes may span a QW boundary
|
||||
*/
|
||||
static inline void read_extra_bytes(struct pio_buf *pbuf,
|
||||
const void *from, unsigned int nbytes)
|
||||
const void *from, unsigned int nbytes)
|
||||
{
|
||||
unsigned long off = (unsigned long)from & 0x7;
|
||||
unsigned int room, xbytes;
|
||||
|
@ -366,7 +366,7 @@ static inline void jcopy(u8 *dest, const u8 *src, u32 n)
|
|||
* o from may _not_ be u64 aligned.
|
||||
*/
|
||||
static inline void read_low_bytes(struct pio_buf *pbuf, const void *from,
|
||||
unsigned int nbytes)
|
||||
unsigned int nbytes)
|
||||
{
|
||||
jcopy(&pbuf->carry.val8[0], from, nbytes);
|
||||
pbuf->carry_bytes = nbytes;
|
||||
|
@ -381,7 +381,7 @@ static inline void read_low_bytes(struct pio_buf *pbuf, const void *from,
|
|||
* o nbytes may span a QW boundary
|
||||
*/
|
||||
static inline void read_extra_bytes(struct pio_buf *pbuf,
|
||||
const void *from, unsigned int nbytes)
|
||||
const void *from, unsigned int nbytes)
|
||||
{
|
||||
jcopy(&pbuf->carry.val8[pbuf->carry_bytes], from, nbytes);
|
||||
pbuf->carry_bytes += nbytes;
|
||||
|
@ -437,7 +437,7 @@ static inline int carry_write8(struct pio_buf *pbuf, void *dest)
|
|||
u64 zero = 0;
|
||||
|
||||
jcopy(&pbuf->carry.val8[pbuf->carry_bytes], (u8 *)&zero,
|
||||
8 - pbuf->carry_bytes);
|
||||
8 - pbuf->carry_bytes);
|
||||
writeq(pbuf->carry.val64, dest);
|
||||
return 1;
|
||||
}
|
||||
|
@ -457,7 +457,7 @@ static inline int carry_write8(struct pio_buf *pbuf, void *dest)
|
|||
* @nbytes: bytes to copy
|
||||
*/
|
||||
void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
|
||||
const void *from, size_t nbytes)
|
||||
const void *from, size_t nbytes)
|
||||
{
|
||||
void __iomem *dest = pbuf->start + SOP_DISTANCE;
|
||||
void __iomem *send = dest + PIO_BLOCK_SIZE;
|
||||
|
@ -647,7 +647,7 @@ static void mid_copy_mix(struct pio_buf *pbuf, const void *from, size_t nbytes)
|
|||
* Must handle nbytes < 8.
|
||||
*/
|
||||
static void mid_copy_straight(struct pio_buf *pbuf,
|
||||
const void *from, size_t nbytes)
|
||||
const void *from, size_t nbytes)
|
||||
{
|
||||
void __iomem *dest = pbuf->start + (pbuf->qw_written * sizeof(u64));
|
||||
void __iomem *dend; /* 8-byte data end */
|
||||
|
|
|
@ -468,7 +468,7 @@ int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, u32 len,
|
|||
|
||||
if (port_num > dd->num_pports || port_num < 1) {
|
||||
dd_dev_info(dd, "%s: Invalid port number %d\n",
|
||||
__func__, port_num);
|
||||
__func__, port_num);
|
||||
ret = -EINVAL;
|
||||
goto set_zeroes;
|
||||
}
|
||||
|
|
|
@ -1773,8 +1773,8 @@ static inline void rc_cancel_ack(struct rvt_qp *qp)
|
|||
* schedule a response to be sent.
|
||||
*/
|
||||
static noinline int rc_rcv_error(struct hfi1_other_headers *ohdr, void *data,
|
||||
struct rvt_qp *qp, u32 opcode, u32 psn, int diff,
|
||||
struct hfi1_ctxtdata *rcd)
|
||||
struct rvt_qp *qp, u32 opcode, u32 psn,
|
||||
int diff, struct hfi1_ctxtdata *rcd)
|
||||
{
|
||||
struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
|
||||
struct rvt_ack_entry *e;
|
||||
|
|
|
@ -283,9 +283,10 @@ int hfi1_ruc_check_hdr(struct hfi1_ibport *ibp, struct hfi1_ib_header *hdr,
|
|||
if (!gid_ok(&hdr->u.l.grh.dgid, ibp->rvp.gid_prefix,
|
||||
guid))
|
||||
goto err;
|
||||
if (!gid_ok(&hdr->u.l.grh.sgid,
|
||||
qp->alt_ah_attr.grh.dgid.global.subnet_prefix,
|
||||
qp->alt_ah_attr.grh.dgid.global.interface_id))
|
||||
if (!gid_ok(
|
||||
&hdr->u.l.grh.sgid,
|
||||
qp->alt_ah_attr.grh.dgid.global.subnet_prefix,
|
||||
qp->alt_ah_attr.grh.dgid.global.interface_id))
|
||||
goto err;
|
||||
}
|
||||
if (unlikely(rcv_pkey_check(ppd_from_ibp(ibp), (u16)bth0,
|
||||
|
@ -317,9 +318,10 @@ int hfi1_ruc_check_hdr(struct hfi1_ibport *ibp, struct hfi1_ib_header *hdr,
|
|||
if (!gid_ok(&hdr->u.l.grh.dgid, ibp->rvp.gid_prefix,
|
||||
guid))
|
||||
goto err;
|
||||
if (!gid_ok(&hdr->u.l.grh.sgid,
|
||||
qp->remote_ah_attr.grh.dgid.global.subnet_prefix,
|
||||
qp->remote_ah_attr.grh.dgid.global.interface_id))
|
||||
if (!gid_ok(
|
||||
&hdr->u.l.grh.sgid,
|
||||
qp->remote_ah_attr.grh.dgid.global.subnet_prefix,
|
||||
qp->remote_ah_attr.grh.dgid.global.interface_id))
|
||||
goto err;
|
||||
}
|
||||
if (unlikely(rcv_pkey_check(ppd_from_ibp(ibp), (u16)bth0,
|
||||
|
|
|
@ -325,9 +325,9 @@ static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
|
|||
if (lcnt++ > 500) {
|
||||
/* timed out - bounce the link */
|
||||
dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
|
||||
__func__, sde->this_idx, (u32)reg);
|
||||
__func__, sde->this_idx, (u32)reg);
|
||||
queue_work(dd->pport->hfi1_wq,
|
||||
&dd->pport->link_bounce_work);
|
||||
&dd->pport->link_bounce_work);
|
||||
break;
|
||||
}
|
||||
udelay(1);
|
||||
|
@ -458,8 +458,8 @@ static void sdma_err_halt_wait(struct work_struct *work)
|
|||
break;
|
||||
if (time_after(jiffies, timeout)) {
|
||||
dd_dev_err(sde->dd,
|
||||
"SDMA engine %d - timeout waiting for engine to halt\n",
|
||||
sde->this_idx);
|
||||
"SDMA engine %d - timeout waiting for engine to halt\n",
|
||||
sde->this_idx);
|
||||
/*
|
||||
* Continue anyway. This could happen if there was
|
||||
* an uncorrectable error in the wrong spot.
|
||||
|
@ -656,7 +656,7 @@ static void sdma_start_hw_clean_up(struct sdma_engine *sde)
|
|||
}
|
||||
|
||||
static void sdma_set_state(struct sdma_engine *sde,
|
||||
enum sdma_states next_state)
|
||||
enum sdma_states next_state)
|
||||
{
|
||||
struct sdma_state *ss = &sde->state;
|
||||
const struct sdma_set_state_action *action = sdma_action_table;
|
||||
|
@ -908,7 +908,7 @@ int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
|
|||
/* newmap in hand, save old map */
|
||||
spin_lock_irq(&dd->sde_map_lock);
|
||||
oldmap = rcu_dereference_protected(dd->sdma_map,
|
||||
lockdep_is_held(&dd->sde_map_lock));
|
||||
lockdep_is_held(&dd->sde_map_lock));
|
||||
|
||||
/* publish newmap */
|
||||
rcu_assign_pointer(dd->sdma_map, newmap);
|
||||
|
@ -1006,16 +1006,16 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
|
|||
return 0;
|
||||
}
|
||||
if (mod_num_sdma &&
|
||||
/* can't exceed chip support */
|
||||
mod_num_sdma <= dd->chip_sdma_engines &&
|
||||
/* count must be >= vls */
|
||||
mod_num_sdma >= num_vls)
|
||||
/* can't exceed chip support */
|
||||
mod_num_sdma <= dd->chip_sdma_engines &&
|
||||
/* count must be >= vls */
|
||||
mod_num_sdma >= num_vls)
|
||||
num_engines = mod_num_sdma;
|
||||
|
||||
dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
|
||||
dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines);
|
||||
dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
|
||||
dd->chip_sdma_mem_size);
|
||||
dd->chip_sdma_mem_size);
|
||||
|
||||
per_sdma_credits =
|
||||
dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE);
|
||||
|
@ -1026,7 +1026,7 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
|
|||
|
||||
descq_cnt = sdma_get_descq_cnt();
|
||||
dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
|
||||
num_engines, descq_cnt);
|
||||
num_engines, descq_cnt);
|
||||
|
||||
/* alloc memory for array of send engines */
|
||||
dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL);
|
||||
|
@ -1086,10 +1086,10 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
|
|||
SDMA_DESC1_INT_REQ_FLAG;
|
||||
|
||||
tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
|
||||
(unsigned long)sde);
|
||||
(unsigned long)sde);
|
||||
|
||||
tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
|
||||
(unsigned long)sde);
|
||||
(unsigned long)sde);
|
||||
INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
|
||||
INIT_WORK(&sde->flush_worker, sdma_field_flush);
|
||||
|
||||
|
@ -1240,7 +1240,7 @@ void sdma_exit(struct hfi1_devdata *dd)
|
|||
sde = &dd->per_sdma[this_idx];
|
||||
if (!list_empty(&sde->dmawait))
|
||||
dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
|
||||
sde->this_idx);
|
||||
sde->this_idx);
|
||||
sdma_process_event(sde, sdma_event_e00_go_hw_down);
|
||||
|
||||
del_timer_sync(&sde->err_progress_check_timer);
|
||||
|
@ -1370,9 +1370,9 @@ static inline u16 sdma_gethead(struct sdma_engine *sde)
|
|||
|
||||
if (unlikely(!sane)) {
|
||||
dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
|
||||
sde->this_idx,
|
||||
use_dmahead ? "dma" : "kreg",
|
||||
hwhead, swhead, swtail, cnt);
|
||||
sde->this_idx,
|
||||
use_dmahead ? "dma" : "kreg",
|
||||
hwhead, swhead, swtail, cnt);
|
||||
if (use_dmahead) {
|
||||
/* try one more time, using csr */
|
||||
use_dmahead = 0;
|
||||
|
@ -1550,10 +1550,10 @@ void sdma_engine_error(struct sdma_engine *sde, u64 status)
|
|||
__sdma_process_event(sde, sdma_event_e60_hw_halted);
|
||||
if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
|
||||
dd_dev_err(sde->dd,
|
||||
"SDMA (%u) engine error: 0x%llx state %s\n",
|
||||
sde->this_idx,
|
||||
(unsigned long long)status,
|
||||
sdma_state_names[sde->state.current_state]);
|
||||
"SDMA (%u) engine error: 0x%llx state %s\n",
|
||||
sde->this_idx,
|
||||
(unsigned long long)status,
|
||||
sdma_state_names[sde->state.current_state]);
|
||||
dump_sdma_state(sde);
|
||||
}
|
||||
write_sequnlock(&sde->head_lock);
|
||||
|
@ -1597,8 +1597,8 @@ static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
|
|||
|
||||
if (op & SDMA_SENDCTRL_OP_CLEANUP)
|
||||
write_sde_csr(sde, SD(CTRL),
|
||||
sde->p_senddmactrl |
|
||||
SD(CTRL_SDMA_CLEANUP_SMASK));
|
||||
sde->p_senddmactrl |
|
||||
SD(CTRL_SDMA_CLEANUP_SMASK));
|
||||
else
|
||||
write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
|
||||
|
||||
|
@ -1622,12 +1622,10 @@ static void sdma_setlengen(struct sdma_engine *sde)
|
|||
* generation counter.
|
||||
*/
|
||||
write_sde_csr(sde, SD(LEN_GEN),
|
||||
(sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)
|
||||
);
|
||||
(sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
|
||||
write_sde_csr(sde, SD(LEN_GEN),
|
||||
((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT))
|
||||
| (4ULL << SD(LEN_GEN_GENERATION_SHIFT))
|
||||
);
|
||||
((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
|
||||
(4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
|
||||
}
|
||||
|
||||
static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
|
||||
|
@ -1707,17 +1705,16 @@ static void init_sdma_regs(
|
|||
write_sde_csr(sde, SD(DESC_CNT), 0);
|
||||
write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
|
||||
write_sde_csr(sde, SD(MEMORY),
|
||||
((u64)credits <<
|
||||
SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
|
||||
((u64)(credits * sde->this_idx) <<
|
||||
SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
|
||||
((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
|
||||
((u64)(credits * sde->this_idx) <<
|
||||
SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
|
||||
write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
|
||||
set_sdma_integrity(sde);
|
||||
opmask = OPCODE_CHECK_MASK_DISABLED;
|
||||
opval = OPCODE_CHECK_VAL_DISABLED;
|
||||
write_sde_csr(sde, SD(CHECK_OPCODE),
|
||||
(opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
|
||||
(opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
|
||||
(opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
|
||||
(opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SDMA_VERBOSITY
|
||||
|
@ -1796,12 +1793,9 @@ static void dump_sdma_state(struct sdma_engine *sde)
|
|||
descq = sde->descq;
|
||||
|
||||
dd_dev_err(sde->dd,
|
||||
"SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
|
||||
sde->this_idx,
|
||||
head,
|
||||
tail,
|
||||
cnt,
|
||||
!list_empty(&sde->flushlist));
|
||||
"SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
|
||||
sde->this_idx, head, tail, cnt,
|
||||
!list_empty(&sde->flushlist));
|
||||
|
||||
/* print info for each entry in the descriptor queue */
|
||||
while (head != tail) {
|
||||
|
@ -1822,20 +1816,23 @@ static void dump_sdma_state(struct sdma_engine *sde)
|
|||
len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
|
||||
& SDMA_DESC0_BYTE_COUNT_MASK;
|
||||
dd_dev_err(sde->dd,
|
||||
"SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
|
||||
head, flags, addr, gen, len);
|
||||
"SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
|
||||
head, flags, addr, gen, len);
|
||||
dd_dev_err(sde->dd,
|
||||
"\tdesc0:0x%016llx desc1 0x%016llx\n",
|
||||
desc[0], desc[1]);
|
||||
"\tdesc0:0x%016llx desc1 0x%016llx\n",
|
||||
desc[0], desc[1]);
|
||||
if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
|
||||
dd_dev_err(sde->dd,
|
||||
"\taidx: %u amode: %u alen: %u\n",
|
||||
(u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
|
||||
>> SDMA_DESC1_HEADER_INDEX_SHIFT),
|
||||
(u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
|
||||
>> SDMA_DESC1_HEADER_MODE_SHIFT),
|
||||
(u8)((desc[1] & SDMA_DESC1_HEADER_DWS_SMASK)
|
||||
>> SDMA_DESC1_HEADER_DWS_SHIFT));
|
||||
"\taidx: %u amode: %u alen: %u\n",
|
||||
(u8)((desc[1] &
|
||||
SDMA_DESC1_HEADER_INDEX_SMASK) >>
|
||||
SDMA_DESC1_HEADER_INDEX_SHIFT),
|
||||
(u8)((desc[1] &
|
||||
SDMA_DESC1_HEADER_MODE_SMASK) >>
|
||||
SDMA_DESC1_HEADER_MODE_SHIFT),
|
||||
(u8)((desc[1] &
|
||||
SDMA_DESC1_HEADER_DWS_SMASK) >>
|
||||
SDMA_DESC1_HEADER_DWS_SHIFT));
|
||||
head++;
|
||||
head &= sde->sdma_mask;
|
||||
}
|
||||
|
@ -1862,29 +1859,26 @@ void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
|
|||
head = sde->descq_head & sde->sdma_mask;
|
||||
tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
|
||||
seq_printf(s, SDE_FMT, sde->this_idx,
|
||||
sde->cpu,
|
||||
sdma_state_name(sde->state.current_state),
|
||||
(unsigned long long)read_sde_csr(sde, SD(CTRL)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(STATUS)),
|
||||
(unsigned long long)read_sde_csr(sde,
|
||||
SD(ENG_ERR_STATUS)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(TAIL)),
|
||||
tail,
|
||||
(unsigned long long)read_sde_csr(sde, SD(HEAD)),
|
||||
head,
|
||||
(unsigned long long)le64_to_cpu(*sde->head_dma),
|
||||
(unsigned long long)read_sde_csr(sde, SD(MEMORY)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
|
||||
(unsigned long long)sde->last_status,
|
||||
(unsigned long long)sde->ahg_bits,
|
||||
sde->tx_tail,
|
||||
sde->tx_head,
|
||||
sde->descq_tail,
|
||||
sde->descq_head,
|
||||
sde->cpu,
|
||||
sdma_state_name(sde->state.current_state),
|
||||
(unsigned long long)read_sde_csr(sde, SD(CTRL)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(STATUS)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
|
||||
(unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
|
||||
(unsigned long long)le64_to_cpu(*sde->head_dma),
|
||||
(unsigned long long)read_sde_csr(sde, SD(MEMORY)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
|
||||
(unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
|
||||
(unsigned long long)sde->last_status,
|
||||
(unsigned long long)sde->ahg_bits,
|
||||
sde->tx_tail,
|
||||
sde->tx_head,
|
||||
sde->descq_tail,
|
||||
sde->descq_head,
|
||||
!list_empty(&sde->flushlist),
|
||||
sde->descq_full_count,
|
||||
(unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
|
||||
sde->descq_full_count,
|
||||
(unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
|
||||
|
||||
/* print info for each entry in the descriptor queue */
|
||||
while (head != tail) {
|
||||
|
@ -1905,14 +1899,16 @@ void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
|
|||
len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
|
||||
& SDMA_DESC0_BYTE_COUNT_MASK;
|
||||
seq_printf(s,
|
||||
"\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
|
||||
head, flags, addr, gen, len);
|
||||
"\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
|
||||
head, flags, addr, gen, len);
|
||||
if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
|
||||
seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
|
||||
(u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
|
||||
>> SDMA_DESC1_HEADER_INDEX_SHIFT),
|
||||
(u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
|
||||
>> SDMA_DESC1_HEADER_MODE_SHIFT));
|
||||
(u8)((desc[1] &
|
||||
SDMA_DESC1_HEADER_INDEX_SMASK) >>
|
||||
SDMA_DESC1_HEADER_INDEX_SHIFT),
|
||||
(u8)((desc[1] &
|
||||
SDMA_DESC1_HEADER_MODE_SMASK) >>
|
||||
SDMA_DESC1_HEADER_MODE_SHIFT));
|
||||
head = (head + 1) & sde->sdma_mask;
|
||||
}
|
||||
}
|
||||
|
@ -2108,9 +2104,8 @@ int sdma_send_txreq(struct sdma_engine *sde,
|
|||
* -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
|
||||
* -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
|
||||
*/
|
||||
int sdma_send_txlist(struct sdma_engine *sde,
|
||||
struct iowait *wait,
|
||||
struct list_head *tx_list)
|
||||
int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait,
|
||||
struct list_head *tx_list)
|
||||
{
|
||||
struct sdma_txreq *tx, *tx_next;
|
||||
int ret = 0;
|
||||
|
@ -2178,8 +2173,7 @@ int sdma_send_txlist(struct sdma_engine *sde,
|
|||
goto update_tail;
|
||||
}
|
||||
|
||||
static void sdma_process_event(struct sdma_engine *sde,
|
||||
enum sdma_events event)
|
||||
static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
|
@ -2196,7 +2190,7 @@ static void sdma_process_event(struct sdma_engine *sde,
|
|||
}
|
||||
|
||||
static void __sdma_process_event(struct sdma_engine *sde,
|
||||
enum sdma_events event)
|
||||
enum sdma_events event)
|
||||
{
|
||||
struct sdma_state *ss = &sde->state;
|
||||
int need_progress = 0;
|
||||
|
@ -2227,7 +2221,7 @@ static void __sdma_process_event(struct sdma_engine *sde,
|
|||
/* This reference means the state machine is started */
|
||||
sdma_get(&sde->state);
|
||||
sdma_set_state(sde,
|
||||
sdma_state_s10_hw_start_up_halt_wait);
|
||||
sdma_state_s10_hw_start_up_halt_wait);
|
||||
break;
|
||||
case sdma_event_e15_hw_halt_done:
|
||||
break;
|
||||
|
@ -2265,7 +2259,7 @@ static void __sdma_process_event(struct sdma_engine *sde,
|
|||
break;
|
||||
case sdma_event_e15_hw_halt_done:
|
||||
sdma_set_state(sde,
|
||||
sdma_state_s15_hw_start_up_clean_wait);
|
||||
sdma_state_s15_hw_start_up_clean_wait);
|
||||
sdma_start_hw_clean_up(sde);
|
||||
break;
|
||||
case sdma_event_e25_hw_clean_up_done:
|
||||
|
@ -3003,7 +2997,8 @@ void sdma_freeze(struct hfi1_devdata *dd)
|
|||
* continuing.
|
||||
*/
|
||||
ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
|
||||
atomic_read(&dd->sdma_unfreeze_count) <= 0);
|
||||
atomic_read(&dd->sdma_unfreeze_count) <=
|
||||
0);
|
||||
/* interrupted or count is negative, then unloading - just exit */
|
||||
if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
|
||||
return;
|
||||
|
@ -3040,7 +3035,7 @@ void sdma_unfreeze(struct hfi1_devdata *dd)
|
|||
/* tell all engines start freeze clean up */
|
||||
for (i = 0; i < dd->num_sdma; i++)
|
||||
sdma_process_event(&dd->per_sdma[i],
|
||||
sdma_event_e82_hw_unfreeze);
|
||||
sdma_event_e82_hw_unfreeze);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -3054,5 +3049,6 @@ void _sdma_engine_progress_schedule(
|
|||
trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
|
||||
/* assume we have selected a good cpu */
|
||||
write_csr(sde->dd,
|
||||
CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)), sde->progress_mask);
|
||||
CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
|
||||
sde->progress_mask);
|
||||
}
|
||||
|
|
|
@ -61,8 +61,8 @@
|
|||
* Congestion control table size followed by table entries
|
||||
*/
|
||||
static ssize_t read_cc_table_bin(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t count)
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t count)
|
||||
{
|
||||
int ret;
|
||||
struct hfi1_pportdata *ppd =
|
||||
|
@ -110,8 +110,8 @@ static struct bin_attribute cc_table_bin_attr = {
|
|||
* trigger threshold and the minimum injection rate delay.
|
||||
*/
|
||||
static ssize_t read_cc_setting_bin(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t count)
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t count)
|
||||
{
|
||||
int ret;
|
||||
struct hfi1_pportdata *ppd =
|
||||
|
@ -550,7 +550,7 @@ static ssize_t show_nctxts(struct device *device,
|
|||
}
|
||||
|
||||
static ssize_t show_nfreectxts(struct device *device,
|
||||
struct device_attribute *attr, char *buf)
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct hfi1_ibdev *dev =
|
||||
container_of(device, struct hfi1_ibdev, rdi.ibdev.dev);
|
||||
|
@ -660,8 +660,8 @@ int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
|
|||
|
||||
if (!port_num || port_num > dd->num_pports) {
|
||||
dd_dev_err(dd,
|
||||
"Skipping infiniband class with invalid port %u\n",
|
||||
port_num);
|
||||
"Skipping infiniband class with invalid port %u\n",
|
||||
port_num);
|
||||
return -ENODEV;
|
||||
}
|
||||
ppd = &dd->pport[port_num - 1];
|
||||
|
@ -700,34 +700,32 @@ int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
|
|||
kobj, "CCMgtA");
|
||||
if (ret) {
|
||||
dd_dev_err(dd,
|
||||
"Skipping Congestion Control sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
"Skipping Congestion Control sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
goto bail_vl2mtu;
|
||||
}
|
||||
|
||||
kobject_uevent(&ppd->pport_cc_kobj, KOBJ_ADD);
|
||||
|
||||
ret = sysfs_create_bin_file(&ppd->pport_cc_kobj,
|
||||
&cc_setting_bin_attr);
|
||||
ret = sysfs_create_bin_file(&ppd->pport_cc_kobj, &cc_setting_bin_attr);
|
||||
if (ret) {
|
||||
dd_dev_err(dd,
|
||||
"Skipping Congestion Control setting sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
"Skipping Congestion Control setting sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
goto bail_cc;
|
||||
}
|
||||
|
||||
ret = sysfs_create_bin_file(&ppd->pport_cc_kobj,
|
||||
&cc_table_bin_attr);
|
||||
ret = sysfs_create_bin_file(&ppd->pport_cc_kobj, &cc_table_bin_attr);
|
||||
if (ret) {
|
||||
dd_dev_err(dd,
|
||||
"Skipping Congestion Control table sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
"Skipping Congestion Control table sysfs info, (err %d) port %u\n",
|
||||
ret, port_num);
|
||||
goto bail_cc_entry_bin;
|
||||
}
|
||||
|
||||
dd_dev_info(dd,
|
||||
"IB%u: Congestion Control Agent enabled for port %d\n",
|
||||
dd->unit, port_num);
|
||||
"IB%u: Congestion Control Agent enabled for port %d\n",
|
||||
dd->unit, port_num);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -109,17 +109,17 @@ const char *parse_everbs_hdrs(
|
|||
case OP(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE):
|
||||
case OP(UC, RDMA_WRITE_LAST_WITH_IMMEDIATE):
|
||||
trace_seq_printf(p, IMM_PRN,
|
||||
be32_to_cpu(eh->imm_data));
|
||||
be32_to_cpu(eh->imm_data));
|
||||
break;
|
||||
/* reth + imm */
|
||||
case OP(RC, RDMA_WRITE_ONLY_WITH_IMMEDIATE):
|
||||
case OP(UC, RDMA_WRITE_ONLY_WITH_IMMEDIATE):
|
||||
trace_seq_printf(p, RETH_PRN " " IMM_PRN,
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->rc.reth.vaddr),
|
||||
be32_to_cpu(eh->rc.reth.rkey),
|
||||
be32_to_cpu(eh->rc.reth.length),
|
||||
be32_to_cpu(eh->rc.imm_data));
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->rc.reth.vaddr),
|
||||
be32_to_cpu(eh->rc.reth.rkey),
|
||||
be32_to_cpu(eh->rc.reth.length),
|
||||
be32_to_cpu(eh->rc.imm_data));
|
||||
break;
|
||||
/* reth */
|
||||
case OP(RC, RDMA_READ_REQUEST):
|
||||
|
@ -128,10 +128,10 @@ const char *parse_everbs_hdrs(
|
|||
case OP(RC, RDMA_WRITE_ONLY):
|
||||
case OP(UC, RDMA_WRITE_ONLY):
|
||||
trace_seq_printf(p, RETH_PRN,
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->rc.reth.vaddr),
|
||||
be32_to_cpu(eh->rc.reth.rkey),
|
||||
be32_to_cpu(eh->rc.reth.length));
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->rc.reth.vaddr),
|
||||
be32_to_cpu(eh->rc.reth.rkey),
|
||||
be32_to_cpu(eh->rc.reth.length));
|
||||
break;
|
||||
case OP(RC, RDMA_READ_RESPONSE_FIRST):
|
||||
case OP(RC, RDMA_READ_RESPONSE_LAST):
|
||||
|
@ -154,19 +154,20 @@ const char *parse_everbs_hdrs(
|
|||
case OP(RC, COMPARE_SWAP):
|
||||
case OP(RC, FETCH_ADD):
|
||||
trace_seq_printf(p, ATOMICETH_PRN,
|
||||
(unsigned long long)ib_u64_get(eh->atomic_eth.vaddr),
|
||||
eh->atomic_eth.rkey,
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->atomic_eth.swap_data),
|
||||
(unsigned long long)ib_u64_get(
|
||||
(unsigned long long)ib_u64_get(
|
||||
eh->atomic_eth.vaddr),
|
||||
eh->atomic_eth.rkey,
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->atomic_eth.swap_data),
|
||||
(unsigned long long)ib_u64_get(
|
||||
(__be32 *)&eh->atomic_eth.compare_data));
|
||||
break;
|
||||
/* deth */
|
||||
case OP(UD, SEND_ONLY):
|
||||
case OP(UD, SEND_ONLY_WITH_IMMEDIATE):
|
||||
trace_seq_printf(p, DETH_PRN,
|
||||
be32_to_cpu(eh->ud.deth[0]),
|
||||
be32_to_cpu(eh->ud.deth[1]) & RVT_QPN_MASK);
|
||||
be32_to_cpu(eh->ud.deth[0]),
|
||||
be32_to_cpu(eh->ud.deth[1]) & RVT_QPN_MASK);
|
||||
break;
|
||||
}
|
||||
trace_seq_putc(p, 0);
|
||||
|
@ -187,12 +188,12 @@ const char *parse_sdma_flags(
|
|||
trace_seq_printf(p, "%s", flags);
|
||||
if (desc0 & SDMA_DESC0_FIRST_DESC_FLAG)
|
||||
trace_seq_printf(p, " amode:%u aidx:%u alen:%u",
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_MODE_SHIFT)
|
||||
& SDMA_DESC1_HEADER_MODE_MASK),
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_INDEX_SHIFT)
|
||||
& SDMA_DESC1_HEADER_INDEX_MASK),
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_DWS_SHIFT)
|
||||
& SDMA_DESC1_HEADER_DWS_MASK));
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_MODE_SHIFT) &
|
||||
SDMA_DESC1_HEADER_MODE_MASK),
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_INDEX_SHIFT) &
|
||||
SDMA_DESC1_HEADER_INDEX_MASK),
|
||||
(u8)((desc1 >> SDMA_DESC1_HEADER_DWS_SHIFT) &
|
||||
SDMA_DESC1_HEADER_DWS_MASK));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -131,7 +131,7 @@ static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
|
|||
}
|
||||
if (rise_usec <= 0)
|
||||
dd_dev_err(dd, "SCL interface stuck low > %d uSec\n",
|
||||
SCL_WAIT_USEC);
|
||||
SCL_WAIT_USEC);
|
||||
}
|
||||
i2c_wait_for_writes(dd, target);
|
||||
}
|
||||
|
|
|
@ -318,7 +318,7 @@ void hfi1_uc_rcv(struct hfi1_packet *packet)
|
|||
sl = ibp->sc_to_sl[sc5];
|
||||
|
||||
process_becn(ppd, sl, rlid, lqpn, rqpn,
|
||||
IB_CC_SVCTYPE_UC);
|
||||
IB_CC_SVCTYPE_UC);
|
||||
}
|
||||
|
||||
if (bth1 & HFI1_FECN_SMASK) {
|
||||
|
|
|
@ -320,9 +320,10 @@ int hfi1_make_ud_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||
if (ah_attr->dlid < be16_to_cpu(IB_MULTICAST_LID_BASE) ||
|
||||
ah_attr->dlid == be16_to_cpu(IB_LID_PERMISSIVE)) {
|
||||
lid = ah_attr->dlid & ~((1 << ppd->lmc) - 1);
|
||||
if (unlikely(!loopback && (lid == ppd->lid ||
|
||||
(lid == be16_to_cpu(IB_LID_PERMISSIVE) &&
|
||||
qp->ibqp.qp_type == IB_QPT_GSI)))) {
|
||||
if (unlikely(!loopback &&
|
||||
(lid == ppd->lid ||
|
||||
(lid == be16_to_cpu(IB_LID_PERMISSIVE) &&
|
||||
qp->ibqp.qp_type == IB_QPT_GSI)))) {
|
||||
unsigned long flags;
|
||||
/*
|
||||
* If DMAs are in progress, we can't generate
|
||||
|
|
|
@ -728,7 +728,7 @@ int hfi1_user_sdma_process_request(struct file *fp, struct iovec *iovec,
|
|||
}
|
||||
|
||||
static inline u32 compute_data_length(struct user_sdma_request *req,
|
||||
struct user_sdma_txreq *tx)
|
||||
struct user_sdma_txreq *tx)
|
||||
{
|
||||
/*
|
||||
* Determine the proper size of the packet data.
|
||||
|
|
|
@ -970,7 +970,8 @@ static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
|
|||
|
||||
/* The most likely matching pkey has index qp->s_pkey_index */
|
||||
if (unlikely(!egress_pkey_matches_entry(pkey,
|
||||
ppd->pkeys[qp->s_pkey_index]))) {
|
||||
ppd->pkeys
|
||||
[qp->s_pkey_index]))) {
|
||||
/* no match - try the entire table */
|
||||
for (; i < MAX_PKEY_VALUES; i++) {
|
||||
if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
|
||||
|
|
Loading…
Reference in New Issue