mirror of https://gitee.com/openkylin/linux.git
x86: make intel.c have 64-bit support code
prepare for unification. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
81faaae457
commit
185f3b9da2
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@ -15,6 +15,11 @@
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#include <asm/ds.h>
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#include <asm/bugs.h>
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#ifdef CONFIG_X86_64
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#include <asm/topology.h>
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#include <asm/numa_64.h>
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#endif
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#include "cpu.h"
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#ifdef CONFIG_X86_LOCAL_APIC
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@ -25,14 +30,20 @@
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static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#else
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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#endif
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}
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#ifdef CONFIG_X86_32
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/*
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* Early probe support logic for ppro memory erratum #50
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*
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@ -73,6 +84,40 @@ static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
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}
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#ifdef CONFIG_X86_F00F_BUG
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static void __cpuinit trap_init_f00f_bug(void)
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{
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__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
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/*
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* Update the IDT descriptor and reload the IDT so that
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* it uses the read-only mapped virtual address.
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*/
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idt_descr.address = fix_to_virt(FIX_F00F_IDT);
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load_idt(&idt_descr);
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}
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#endif
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#endif
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static void __cpuinit srat_detect_node(void)
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{
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#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
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unsigned node;
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int cpu = smp_processor_id();
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int apicid = hard_smp_processor_id();
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/* Don't do the funky fallback heuristics the AMD version employs
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for now. */
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node = apicid_to_node[apicid];
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if (node == NUMA_NO_NODE || !node_online(node))
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node = first_node(node_online_map);
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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}
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/*
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* find out the number of processor cores on the die
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*/
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@ -91,20 +136,6 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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return 1;
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}
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#ifdef CONFIG_X86_F00F_BUG
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static void __cpuinit trap_init_f00f_bug(void)
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{
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__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
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/*
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* Update the IDT descriptor and reload the IDT so that
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* it uses the read-only mapped virtual address.
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*/
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idt_descr.address = fix_to_virt(FIX_F00F_IDT);
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load_idt(&idt_descr);
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}
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#endif
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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unsigned int l2 = 0;
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@ -139,6 +170,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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#ifdef CONFIG_X86_32
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/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_cpu_cap(c, X86_FEATURE_SEP);
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@ -176,18 +208,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if (p)
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strcpy(c->x86_model_id, p);
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detect_extended_topology(c);
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if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
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/*
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* let's use the legacy cpuid vector 0x1 and 0x4 for topology
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* detection.
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*/
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c->x86_max_cores = intel_num_cpu_cores(c);
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detect_ht(c);
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}
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/* Work around errata */
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Intel_errata_workarounds(c);
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#ifdef CONFIG_X86_INTEL_USERCOPY
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@ -206,14 +226,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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movsl_mask.mask = 7;
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break;
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}
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#endif
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#endif
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if (cpu_has_xmm2)
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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if (c->x86 == 15)
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set_cpu_cap(c, X86_FEATURE_P4);
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_P3);
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if (cpu_has_ds) {
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unsigned int l1;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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@ -224,6 +242,17 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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ds_init_intel(c);
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}
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#ifdef CONFIG_X86_64
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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#else
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if (c->x86 == 15)
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set_cpu_cap(c, X86_FEATURE_P4);
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_P3);
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if (cpu_has_bts)
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ptrace_bts_init_intel(c);
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@ -240,8 +269,25 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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#ifdef CONFIG_X86_NUMAQ
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numaq_tsc_disable();
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#endif
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#endif
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detect_extended_topology(c);
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if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
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/*
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* let's use the legacy cpuid vector 0x1 and 0x4 for topology
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* detection.
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*/
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c->x86_max_cores = intel_num_cpu_cores(c);
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#ifdef CONFIG_X86_32
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detect_ht(c);
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#endif
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}
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/* Work around errata */
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srat_detect_node();
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}
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#ifdef CONFIG_X86_32
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static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/*
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@ -254,10 +300,12 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned i
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size = 256;
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return size;
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}
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#endif
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static struct cpu_dev intel_cpu_dev __cpuinitdata = {
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.c_vendor = "Intel",
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.c_ident = { "GenuineIntel" },
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#ifdef CONFIG_X86_32
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.c_models = {
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{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
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{
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@ -307,13 +355,12 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
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}
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},
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},
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.c_size_cache = intel_size_cache,
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#endif
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.c_early_init = early_init_intel,
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.c_init = init_intel,
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.c_size_cache = intel_size_cache,
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.c_x86_vendor = X86_VENDOR_INTEL,
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};
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cpu_dev_register(intel_cpu_dev);
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/* arch_initcall(intel_cpu_init); */
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