mirror of https://gitee.com/openkylin/linux.git
ARM: PL08x: avoid duplicating registers in txd and phychan structures
As we now have all the code accessing the phychan {csrc,cdst,clli,cctl, ccfg} members in one function, there's no point storing the data into the struct. Get rid of the struct members. Re-order the register dump in the dev_dbg() to reflect the order we write the registers to the DMA device. The txd {csrc,cdst,clli,cctl} values are duplicates of the lli[0] values, so there's no point duplicating these either. Program the DMAC registers directly from the lli[0] values. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -193,33 +193,25 @@ static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
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{
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_phy_chan *phychan = plchan->phychan;
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u32 val;
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struct pl08x_lli *lli = &txd->llis_va[0];
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u32 val, ccfg;
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plchan->at = txd;
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/* Copy the basic control register calculated at transfer config */
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phychan->csrc = txd->csrc;
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phychan->cdst = txd->cdst;
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phychan->clli = txd->clli;
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phychan->cctl = txd->cctl;
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/* Assign the signal to the proper control registers */
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phychan->ccfg = plchan->cd->ccfg;
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phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
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phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
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ccfg = plchan->cd->ccfg;
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ccfg &= ~(PL080_CONFIG_SRC_SEL_MASK | PL080_CONFIG_DST_SEL_MASK);
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/* If it wasn't set from AMBA, ignore it */
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if (txd->direction == DMA_TO_DEVICE)
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/* Select signal as destination */
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phychan->ccfg |=
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(phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
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ccfg |= phychan->signal << PL080_CONFIG_DST_SEL_SHIFT;
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else if (txd->direction == DMA_FROM_DEVICE)
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/* Select signal as source */
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phychan->ccfg |=
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(phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
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/* Always enable error interrupts */
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phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
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/* Always enable terminal interrupts */
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phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
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ccfg |= phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
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/* Always enable error and terminal interrupts */
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ccfg |= PL080_CONFIG_ERR_IRQ_MASK | PL080_CONFIG_TC_IRQ_MASK;
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/* Wait for channel inactive */
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while (pl08x_phy_channel_busy(phychan))
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@ -227,19 +219,15 @@ static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
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dev_vdbg(&pl08x->adev->dev,
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"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
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"cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
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phychan->id,
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phychan->csrc,
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phychan->cdst,
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phychan->cctl,
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phychan->clli,
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phychan->ccfg);
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"clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
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phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
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ccfg);
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writel(phychan->csrc, phychan->base + PL080_CH_SRC_ADDR);
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writel(phychan->cdst, phychan->base + PL080_CH_DST_ADDR);
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writel(phychan->clli, phychan->base + PL080_CH_LLI);
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writel(phychan->cctl, phychan->base + PL080_CH_CONTROL);
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writel(phychan->ccfg, phychan->base + PL080_CH_CONFIG);
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writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
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writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
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writel(lli->lli, phychan->base + PL080_CH_LLI);
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writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
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writel(ccfg, phychan->base + PL080_CH_CONFIG);
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/* Enable the DMA channel */
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/* Do not access config register until channel shows as disabled */
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@ -920,13 +908,6 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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*/
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llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
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/* Now store the channel register values */
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txd->csrc = llis_va[0].src;
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txd->cdst = llis_va[0].dst;
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txd->clli = llis_va[0].lli;
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txd->cctl = llis_va[0].cctl;
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/* ccfg will be set at physical channel allocation time */
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#ifdef VERBOSE_DEBUG
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{
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int i;
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@ -95,11 +95,6 @@ struct pl08x_phy_chan {
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spinlock_t lock;
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int signal;
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struct pl08x_dma_chan *serving;
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u32 csrc;
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u32 cdst;
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u32 clli;
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u32 cctl;
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u32 ccfg;
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};
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/**
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@ -118,14 +113,6 @@ struct pl08x_txd {
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void *llis_va;
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struct pl08x_channel_data *cd;
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bool active;
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/*
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* Settings to be put into the physical channel when we
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* trigger this txd
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*/
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u32 csrc;
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u32 cdst;
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u32 clli;
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u32 cctl;
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};
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/**
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