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MIPS: Add function for flushing the TLB using the TLBINV instruction 

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6136/
This commit is contained in:
Leonid Yegoshin 2013-11-14 16:12:29 +00:00 committed by Ralf Baechle
parent b0d4d30026
commit 198bb4cef1
1 changed files with 13 additions and 0 deletions
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13
arch/mips/include/asm/mipsregs.h
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@ -704,6 +704,19 @@ static inline int mm_insn_16bit(u16 insn)
return (opcode >= 1 && opcode <= 3) ? 1 : 0;
}
/*
* TLB Invalidate Flush
*/
static inline void tlbinvf(void)
{
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
".word 0x42000004\n\t" /* tlbinvf */
".set pop");
}
/*
* Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit