mirror of https://gitee.com/openkylin/linux.git
MIPS: Octeon: Support 256 MSI on PCIe
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
0c2f4551df
commit
1aa2b2782a
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@ -172,7 +172,7 @@
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#ifdef CONFIG_PCI_MSI
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/* 152 - 215 represent the MSI interrupts 0-63 */
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#define OCTEON_IRQ_MSI_BIT0 152
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 63)
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#else
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2009 Cavium Networks
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* Copyright (C) 2005-2009, 2010 Cavium Networks
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -22,7 +22,7 @@
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* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
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* in use.
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*/
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static uint64_t msi_free_irq_bitmask;
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static u64 msi_free_irq_bitmask[4];
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/*
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* Each bit in msi_multiple_irq_bitmask tells that the device using
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@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask;
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* is used so we can disable all of the MSI interrupts when a device
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* uses multiple.
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*/
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static uint64_t msi_multiple_irq_bitmask;
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static u64 msi_multiple_irq_bitmask[4];
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/*
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* This lock controls updates to msi_free_irq_bitmask and
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@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask;
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*/
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static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
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/*
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* Number of MSI IRQs used. This variable is set up in
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* the module init time.
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*/
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static int msi_irq_size;
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/**
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* Called when a driver request MSI interrupts instead of the
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@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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{
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struct msi_msg msg;
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uint16_t control;
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u16 control;
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int configured_private_bits;
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int request_private_bits;
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int irq;
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int irq = 0;
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int irq_step;
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uint64_t search_mask;
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u64 search_mask;
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int index;
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/*
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* Read the MSI config to figure out how many IRQs this device
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@ -111,29 +117,31 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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* use.
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*/
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spin_lock(&msi_free_irq_bitmask_lock);
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for (irq = 0; irq < 64; irq += irq_step) {
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if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
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msi_free_irq_bitmask |= search_mask << irq;
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msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
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break;
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for (index = 0; index < msi_irq_size/64; index++) {
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for (irq = 0; irq < 64; irq += irq_step) {
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if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
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msi_free_irq_bitmask[index] |= search_mask << irq;
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msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
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goto msi_irq_allocated;
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}
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}
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}
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msi_irq_allocated:
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spin_unlock(&msi_free_irq_bitmask_lock);
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/* Make sure the search for available interrupts didn't fail */
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if (irq >= 64) {
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if (request_private_bits) {
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pr_err("arch_setup_msi_irq: Unable to find %d free "
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"interrupts, trying just one",
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pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
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1 << request_private_bits);
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request_private_bits = 0;
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goto try_only_one;
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} else
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panic("arch_setup_msi_irq: Unable to find a free MSI "
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"interrupt");
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panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
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}
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/* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
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irq += index*64;
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irq += OCTEON_IRQ_MSI_BIT0;
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switch (octeon_dma_bar_type) {
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@ -179,12 +187,18 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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void arch_teardown_msi_irq(unsigned int irq)
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{
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int number_irqs;
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uint64_t bitmask;
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u64 bitmask;
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int index = 0;
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int irq0;
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if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_LAST))
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if ((irq < OCTEON_IRQ_MSI_BIT0)
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|| (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
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panic("arch_teardown_msi_irq: Attempted to teardown illegal "
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"MSI interrupt (%d)", irq);
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irq -= OCTEON_IRQ_MSI_BIT0;
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index = irq / 64;
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irq0 = irq % 64;
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/*
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* Count the number of IRQs we need to free by looking at the
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@ -192,151 +206,197 @@ void arch_teardown_msi_irq(unsigned int irq)
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* IRQ is also owned by this device.
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*/
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number_irqs = 0;
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while ((irq+number_irqs < 64) &&
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(msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
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while ((irq0 + number_irqs < 64) &&
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(msi_multiple_irq_bitmask[index]
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& (1ull << (irq0 + number_irqs))))
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number_irqs++;
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number_irqs++;
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/* Mask with one bit for each IRQ */
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bitmask = (1 << number_irqs) - 1;
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/* Shift the mask to the correct bit location */
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bitmask <<= irq;
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if ((msi_free_irq_bitmask & bitmask) != bitmask)
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bitmask <<= irq0;
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if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
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panic("arch_teardown_msi_irq: Attempted to teardown MSI "
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"interrupt (%d) not in use", irq);
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/* Checks are done, update the in use bitmask */
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spin_lock(&msi_free_irq_bitmask_lock);
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msi_free_irq_bitmask &= ~bitmask;
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msi_multiple_irq_bitmask &= ~bitmask;
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msi_free_irq_bitmask[index] &= ~bitmask;
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msi_multiple_irq_bitmask[index] &= ~bitmask;
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spin_unlock(&msi_free_irq_bitmask_lock);
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}
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static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
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static u64 msi_rcv_reg[4];
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static u64 mis_ena_reg[4];
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static void octeon_irq_msi_enable_pcie(unsigned int irq)
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{
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u64 en;
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unsigned long flags;
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int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
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int irq_index = msi_number >> 6;
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int irq_bit = msi_number & 0x3f;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(mis_ena_reg[irq_index]);
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en |= 1ull << irq_bit;
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cvmx_write_csr(mis_ena_reg[irq_index], en);
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cvmx_read_csr(mis_ena_reg[irq_index]);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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static void octeon_irq_msi_disable_pcie(unsigned int irq)
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{
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u64 en;
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unsigned long flags;
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int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
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int irq_index = msi_number >> 6;
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int irq_bit = msi_number & 0x3f;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(mis_ena_reg[irq_index]);
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en &= ~(1ull << irq_bit);
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cvmx_write_csr(mis_ena_reg[irq_index], en);
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cvmx_read_csr(mis_ena_reg[irq_index]);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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static struct irq_chip octeon_irq_chip_msi_pcie = {
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.name = "MSI",
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.enable = octeon_irq_msi_enable_pcie,
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.disable = octeon_irq_msi_disable_pcie,
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};
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static void octeon_irq_msi_enable_pci(unsigned int irq)
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{
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/*
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* Octeon PCI doesn't have the ability to mask/unmask MSI
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* interrupts individually. Instead of masking/unmasking them
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* in groups of 16, we simple assume MSI devices are well
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* behaved. MSI interrupts are always enable and the ACK is
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* assumed to be enough
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*/
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}
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static void octeon_irq_msi_disable_pci(unsigned int irq)
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{
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/* See comment in enable */
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}
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static struct irq_chip octeon_irq_chip_msi_pci = {
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.name = "MSI",
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.enable = octeon_irq_msi_enable_pci,
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.disable = octeon_irq_msi_disable_pci,
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};
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/*
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* Called by the interrupt handling code when an MSI interrupt
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* occurs.
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*/
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static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
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static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
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{
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uint64_t msi_bits;
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int irq;
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int bit;
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
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msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
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else
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msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
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irq = fls64(msi_bits);
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if (irq) {
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irq += OCTEON_IRQ_MSI_BIT0 - 1;
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if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* These chips have PCIe */
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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} else {
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/* These chips have PCI */
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cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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}
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if (irq_desc[irq].action) {
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do_IRQ(irq);
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return IRQ_HANDLED;
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} else {
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pr_err("Spurious MSI interrupt %d\n", irq);
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}
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bit = fls64(msi_bits);
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if (bit) {
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bit--;
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/* Acknowledge it first. */
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cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
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irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
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do_IRQ(irq);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
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static void octeon_irq_msi_enable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/*
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* Octeon PCI doesn't have the ability to mask/unmask
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* MSI interrupts individually. Instead of
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* masking/unmasking them in groups of 16, we simple
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* assume MSI devices are well behaved. MSI
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* interrupts are always enable and the ACK is assumed
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* to be enough.
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*/
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} else {
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/* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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#define OCTEON_MSI_INT_HANDLER_X(x) \
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static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
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{ \
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u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
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return __octeon_msi_do_interrupt((x), msi_bits); \
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}
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static void octeon_irq_msi_disable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* See comment in enable */
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} else {
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/*
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* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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}
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static struct irq_chip octeon_irq_chip_msi = {
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.name = "MSI",
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.enable = octeon_irq_msi_enable,
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.disable = octeon_irq_msi_disable,
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};
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/*
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* Create octeon_msi_interrupt{0-3} function body
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*/
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OCTEON_MSI_INT_HANDLER_X(0);
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OCTEON_MSI_INT_HANDLER_X(1);
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OCTEON_MSI_INT_HANDLER_X(2);
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OCTEON_MSI_INT_HANDLER_X(3);
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/*
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* Initializes the MSI interrupt handling code
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*/
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static int __init octeon_msi_initialize(void)
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int __init octeon_msi_initialize(void)
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{
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int irq;
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struct irq_chip *msi;
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) {
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set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_simple_irq);
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
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msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
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msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
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msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
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msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
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mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
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mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
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mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
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mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
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msi = &octeon_irq_chip_msi_pcie;
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} else {
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msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
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#define INVALID_GENERATE_ADE 0x8700000000000000ULL;
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msi_rcv_reg[1] = INVALID_GENERATE_ADE;
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msi_rcv_reg[2] = INVALID_GENERATE_ADE;
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msi_rcv_reg[3] = INVALID_GENERATE_ADE;
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mis_ena_reg[0] = INVALID_GENERATE_ADE;
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mis_ena_reg[1] = INVALID_GENERATE_ADE;
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mis_ena_reg[2] = INVALID_GENERATE_ADE;
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mis_ena_reg[3] = INVALID_GENERATE_ADE;
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msi = &octeon_irq_chip_msi_pci;
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}
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
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set_irq_chip_and_handler(irq, msi, handle_simple_irq);
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if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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0, "MSI[0:63]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
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} else if (octeon_is_pci_host()) {
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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0, "MSI[0:15]", octeon_msi_interrupt))
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
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0, "MSI[0:63]", octeon_msi_interrupt0))
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panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
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if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
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0, "MSI[16:31]", octeon_msi_interrupt))
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if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
|
||||
0, "MSI[64:127]", octeon_msi_interrupt1))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
|
||||
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
|
||||
0, "MSI[32:47]", octeon_msi_interrupt))
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
|
||||
0, "MSI[127:191]", octeon_msi_interrupt2))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
|
||||
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
|
||||
0, "MSI[48:63]", octeon_msi_interrupt))
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
|
||||
0, "MSI[192:255]", octeon_msi_interrupt3))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
|
||||
|
||||
msi_irq_size = 256;
|
||||
} else if (octeon_is_pci_host()) {
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
|
||||
0, "MSI[0:15]", octeon_msi_interrupt0))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
|
||||
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
|
||||
0, "MSI[16:31]", octeon_msi_interrupt0))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
|
||||
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
|
||||
0, "MSI[32:47]", octeon_msi_interrupt0))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
|
||||
|
||||
if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
|
||||
0, "MSI[48:63]", octeon_msi_interrupt0))
|
||||
panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
|
||||
msi_irq_size = 64;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue