mirror of https://gitee.com/openkylin/linux.git
Merge branches 'pm-avs', 'pm-clk' and 'powercap'
* pm-avs: PM / AVS: rockchip-io: Fix module autoload for OF platform driver * pm-clk: PM / clk: Fix broken build due to non-matching code and header #ifdefs * powercap: powercap / RAPL: Enable Broxton RAPL support
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commit
1ab68460b1
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@ -17,7 +17,7 @@
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#include <linux/err.h>
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#include <linux/pm_runtime.h>
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM_CLK
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enum pce_status {
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PCE_STATUS_NONE = 0,
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@ -404,7 +404,7 @@ int pm_clk_runtime_resume(struct device *dev)
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return pm_generic_runtime_resume(dev);
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}
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#else /* !CONFIG_PM */
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#else /* !CONFIG_PM_CLK */
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/**
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* enable_clock - Enable a device clock.
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@ -484,7 +484,7 @@ static int pm_clk_notify(struct notifier_block *nb,
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return 0;
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}
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#endif /* !CONFIG_PM */
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#endif /* !CONFIG_PM_CLK */
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/**
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* pm_clk_add_notifier - Add bus type notifier for power management clocks.
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@ -271,6 +271,7 @@ static const struct of_device_id rockchip_iodomain_match[] = {
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
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static int rockchip_iodomain_probe(struct platform_device *pdev)
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{
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@ -1102,6 +1102,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
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RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
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RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
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RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
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RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
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RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
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RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
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{}
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