mirror of https://gitee.com/openkylin/linux.git
rsi: configure new boot parameters to device
Boot parameters are changed in new firmware. Also three new sdio sleep parameters are added for ultra low power save. Signed-off-by: Prameela Rani Garnepudi <prameela.j04cs@gmail.com> Signed-off-by: Amitkumar Karwar <amit.karwar@redpinesignals.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -45,10 +45,10 @@ static struct bootup_params boot_params_20 = {
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}
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},
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.switch_clk_g = {
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.switch_clk_info = cpu_to_le16(BIT(3)),
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.bbp_lmac_clk_reg_val = cpu_to_le16(0x121),
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.umac_clock_reg_config = 0x0,
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.qspi_uart_clock_reg_config = 0x0
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.switch_clk_info = cpu_to_le16(0xb),
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.bbp_lmac_clk_reg_val = cpu_to_le16(0x111),
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.umac_clock_reg_config = cpu_to_le16(0x48),
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.qspi_uart_clock_reg_config = cpu_to_le16(0x1211)
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}
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},
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{
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@ -106,7 +106,10 @@ static struct bootup_params boot_params_20 = {
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.wdt_prog_value = 0x0,
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.wdt_soc_rst_delay = 0x0,
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.dcdc_operation_mode = 0x0,
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.soc_reset_wait_cnt = 0x0
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.soc_reset_wait_cnt = 0x0,
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.waiting_time_at_fresh_sleep = 0x0,
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.max_threshold_to_avoid_sleep = 0x0,
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.beacon_resedue_alg_en = 0,
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};
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static struct bootup_params boot_params_40 = {
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@ -139,7 +142,7 @@ static struct bootup_params boot_params_40 = {
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.switch_clk_info = cpu_to_le16(0x09),
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.bbp_lmac_clk_reg_val = cpu_to_le16(0x1121),
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.umac_clock_reg_config = cpu_to_le16(0x48),
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.qspi_uart_clock_reg_config = 0x0
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.qspi_uart_clock_reg_config = cpu_to_le16(0x1211)
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}
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},
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{
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@ -197,7 +200,10 @@ static struct bootup_params boot_params_40 = {
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.wdt_prog_value = 0x0,
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.wdt_soc_rst_delay = 0x0,
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.dcdc_operation_mode = 0x0,
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.soc_reset_wait_cnt = 0x0
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.soc_reset_wait_cnt = 0x0,
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.waiting_time_at_fresh_sleep = 0x0,
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.max_threshold_to_avoid_sleep = 0x0,
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.beacon_resedue_alg_en = 0,
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};
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static u16 mcs[] = {13, 26, 39, 52, 78, 104, 117, 130};
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@ -24,19 +24,19 @@
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#define WIFI_AFEPLL_CONFIGS BIT(7)
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#define WIFI_SWITCH_CLK_CONFIGS BIT(8)
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#define TA_PLL_M_VAL_20 8
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#define TA_PLL_N_VAL_20 1
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#define TA_PLL_M_VAL_20 9
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#define TA_PLL_N_VAL_20 0
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#define TA_PLL_P_VAL_20 4
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#define PLL960_M_VAL_20 0x14
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#define PLL960_N_VAL_20 0
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#define PLL960_P_VAL_20 5
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#define UMAC_CLK_40MHZ 40
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#define UMAC_CLK_40MHZ 80
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#define TA_PLL_M_VAL_40 46
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#define TA_PLL_N_VAL_40 3
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#define TA_PLL_P_VAL_40 3
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#define TA_PLL_M_VAL_40 9
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#define TA_PLL_N_VAL_40 0
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#define TA_PLL_P_VAL_40 4
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#define PLL960_M_VAL_40 0x14
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#define PLL960_N_VAL_40 0
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@ -122,5 +122,8 @@ struct bootup_params {
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/* dcdc modes configs */
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__le32 dcdc_operation_mode;
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__le32 soc_reset_wait_cnt;
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__le32 waiting_time_at_fresh_sleep;
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__le32 max_threshold_to_avoid_sleep;
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u8 beacon_resedue_alg_en;
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} __packed;
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#endif
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