mirror of https://gitee.com/openkylin/linux.git
arm64: KVM: vgic-v3: Avoid accessing ICH registers
Just like on GICv2, we're a bit hammer-happy with GICv3, and access them more often than we should. Adopt a policy similar to what we do for GICv2, only save/restoring the minimal set of registers. As we don't access the registers linearly anymore (we may skip some), the convoluted accessors become slightly simpler, and we can drop the ugly indexing macro that tended to confuse the reviewers. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier
parent
667a87a928
commit
1b8e83c04e
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@ -37,12 +37,104 @@
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asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
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} while (0)
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/* vcpu is already in the HYP VA space */
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static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
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{
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switch (lr & 0xf) {
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case 0:
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return read_gicreg(ICH_LR0_EL2);
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case 1:
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return read_gicreg(ICH_LR1_EL2);
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case 2:
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return read_gicreg(ICH_LR2_EL2);
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case 3:
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return read_gicreg(ICH_LR3_EL2);
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case 4:
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return read_gicreg(ICH_LR4_EL2);
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case 5:
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return read_gicreg(ICH_LR5_EL2);
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case 6:
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return read_gicreg(ICH_LR6_EL2);
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case 7:
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return read_gicreg(ICH_LR7_EL2);
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case 8:
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return read_gicreg(ICH_LR8_EL2);
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case 9:
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return read_gicreg(ICH_LR9_EL2);
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case 10:
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return read_gicreg(ICH_LR10_EL2);
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case 11:
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return read_gicreg(ICH_LR11_EL2);
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case 12:
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return read_gicreg(ICH_LR12_EL2);
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case 13:
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return read_gicreg(ICH_LR13_EL2);
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case 14:
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return read_gicreg(ICH_LR14_EL2);
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case 15:
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return read_gicreg(ICH_LR15_EL2);
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}
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unreachable();
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}
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static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
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{
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switch (lr & 0xf) {
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case 0:
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write_gicreg(val, ICH_LR0_EL2);
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break;
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case 1:
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write_gicreg(val, ICH_LR1_EL2);
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break;
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case 2:
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write_gicreg(val, ICH_LR2_EL2);
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break;
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case 3:
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write_gicreg(val, ICH_LR3_EL2);
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break;
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case 4:
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write_gicreg(val, ICH_LR4_EL2);
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break;
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case 5:
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write_gicreg(val, ICH_LR5_EL2);
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break;
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case 6:
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write_gicreg(val, ICH_LR6_EL2);
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break;
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case 7:
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write_gicreg(val, ICH_LR7_EL2);
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break;
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case 8:
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write_gicreg(val, ICH_LR8_EL2);
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break;
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case 9:
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write_gicreg(val, ICH_LR9_EL2);
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break;
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case 10:
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write_gicreg(val, ICH_LR10_EL2);
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break;
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case 11:
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write_gicreg(val, ICH_LR11_EL2);
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break;
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case 12:
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write_gicreg(val, ICH_LR12_EL2);
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break;
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case 13:
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write_gicreg(val, ICH_LR13_EL2);
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break;
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case 14:
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write_gicreg(val, ICH_LR14_EL2);
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break;
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case 15:
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write_gicreg(val, ICH_LR15_EL2);
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break;
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}
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}
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void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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u64 val;
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u32 max_lr_idx, nr_pri_bits;
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/*
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* Make sure stores to the GIC via the memory mapped interface
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@ -51,68 +143,58 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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dsb(st);
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cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
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cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
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cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
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cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
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write_gicreg(0, ICH_HCR_EL2);
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val = read_gicreg(ICH_VTR_EL2);
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max_lr_idx = vtr_to_max_lr_idx(val);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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if (vcpu->arch.vgic_cpu.live_lrs) {
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int i;
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u32 max_lr_idx, nr_pri_bits;
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switch (max_lr_idx) {
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case 15:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)] = read_gicreg(ICH_LR15_EL2);
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case 14:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)] = read_gicreg(ICH_LR14_EL2);
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case 13:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)] = read_gicreg(ICH_LR13_EL2);
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case 12:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)] = read_gicreg(ICH_LR12_EL2);
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case 11:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)] = read_gicreg(ICH_LR11_EL2);
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case 10:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)] = read_gicreg(ICH_LR10_EL2);
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case 9:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)] = read_gicreg(ICH_LR9_EL2);
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case 8:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)] = read_gicreg(ICH_LR8_EL2);
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case 7:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)] = read_gicreg(ICH_LR7_EL2);
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case 6:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)] = read_gicreg(ICH_LR6_EL2);
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case 5:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)] = read_gicreg(ICH_LR5_EL2);
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case 4:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)] = read_gicreg(ICH_LR4_EL2);
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case 3:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)] = read_gicreg(ICH_LR3_EL2);
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case 2:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)] = read_gicreg(ICH_LR2_EL2);
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case 1:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)] = read_gicreg(ICH_LR1_EL2);
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case 0:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)] = read_gicreg(ICH_LR0_EL2);
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}
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cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
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cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
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cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
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cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
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case 6:
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cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
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default:
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cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
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}
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write_gicreg(0, ICH_HCR_EL2);
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val = read_gicreg(ICH_VTR_EL2);
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max_lr_idx = vtr_to_max_lr_idx(val);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
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cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
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case 6:
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cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
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default:
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cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
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for (i = 0; i <= max_lr_idx; i++) {
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if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
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cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
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}
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
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cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
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case 6:
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cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
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default:
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cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
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}
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
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cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
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case 6:
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cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
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default:
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cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
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}
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vcpu->arch.vgic_cpu.live_lrs = 0;
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} else {
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cpu_if->vgic_misr = 0;
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cpu_if->vgic_eisr = 0;
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cpu_if->vgic_elrsr = 0xffff;
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cpu_if->vgic_ap0r[0] = 0;
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cpu_if->vgic_ap0r[1] = 0;
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cpu_if->vgic_ap0r[2] = 0;
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cpu_if->vgic_ap0r[3] = 0;
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cpu_if->vgic_ap1r[0] = 0;
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cpu_if->vgic_ap1r[1] = 0;
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cpu_if->vgic_ap1r[2] = 0;
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cpu_if->vgic_ap1r[3] = 0;
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}
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val = read_gicreg(ICC_SRE_EL2);
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@ -126,6 +208,8 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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u64 val;
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u32 max_lr_idx, nr_pri_bits;
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u16 live_lrs = 0;
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int i;
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/*
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* VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
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@ -138,66 +222,48 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
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isb();
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write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
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write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
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val = read_gicreg(ICH_VTR_EL2);
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max_lr_idx = vtr_to_max_lr_idx(val);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
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write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
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for (i = 0; i <= max_lr_idx; i++) {
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if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
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live_lrs |= (1 << i);
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}
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
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write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
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}
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write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
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switch (max_lr_idx) {
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case 15:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)], ICH_LR15_EL2);
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case 14:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)], ICH_LR14_EL2);
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case 13:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)], ICH_LR13_EL2);
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case 12:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)], ICH_LR12_EL2);
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case 11:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)], ICH_LR11_EL2);
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case 10:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)], ICH_LR10_EL2);
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case 9:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)], ICH_LR9_EL2);
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case 8:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)], ICH_LR8_EL2);
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case 7:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)], ICH_LR7_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)], ICH_LR6_EL2);
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case 5:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)], ICH_LR5_EL2);
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case 4:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)], ICH_LR4_EL2);
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case 3:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)], ICH_LR3_EL2);
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case 2:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)], ICH_LR2_EL2);
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case 1:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)], ICH_LR1_EL2);
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case 0:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)], ICH_LR0_EL2);
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if (live_lrs) {
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write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
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write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
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}
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
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write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
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}
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for (i = 0; i <= max_lr_idx; i++) {
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val = 0;
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if (live_lrs & (1 << i))
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val = cpu_if->vgic_lr[i];
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__gic_v3_set_lr(val, i);
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}
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}
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/*
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@ -207,6 +273,7 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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*/
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isb();
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dsb(sy);
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vcpu->arch.vgic_cpu.live_lrs = live_lrs;
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/*
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* Prevent the guest from touching the GIC system registers if
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@ -279,12 +279,6 @@ struct vgic_v2_cpu_if {
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u32 vgic_lr[VGIC_V2_MAX_LRS];
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};
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/*
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* LRs are stored in reverse order in memory. make sure we index them
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* correctly.
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*/
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#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
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struct vgic_v3_cpu_if {
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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u32 vgic_hcr;
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@ -42,7 +42,7 @@ static u32 ich_vtr_el2;
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static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
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{
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struct vgic_lr lr_desc;
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u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)];
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u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];
|
||||
|
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if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
|
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lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
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|
@ -106,7 +106,7 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
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lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
|
||||
}
|
||||
|
||||
vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)] = lr_val;
|
||||
vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;
|
||||
|
||||
if (!(lr_desc.state & LR_STATE_MASK))
|
||||
vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
|
||||
|
|
|
|||
Loading…
Reference in New Issue