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drm/amd/display: Expose configure_encoder for link_encoder 

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2018-06-18 18:32:43 -04:00 committed by Alex Deucher
parent 8e8539c2fc
commit 1bd493e378
2 changed files with 5 additions and 2 deletions
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3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View File

@ -445,12 +445,11 @@ static uint8_t get_frontend_source(
} }
} }
static void configure_encoder( void configure_encoder(
struct dcn10_link_encoder *enc10, struct dcn10_link_encoder *enc10,
const struct dc_link_settings *link_settings) const struct dc_link_settings *link_settings)
{ {
/* set number of lanes */ /* set number of lanes */
REG_SET(DP_CONFIG, 0, REG_SET(DP_CONFIG, 0,
DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
View File

@ -271,6 +271,10 @@ void dcn10_link_encoder_setup(
struct link_encoder *enc, struct link_encoder *enc,
enum signal_type signal); enum signal_type signal);
void configure_encoder(
struct dcn10_link_encoder *enc10,
const struct dc_link_settings *link_settings);
/* enables TMDS PHY output */ /* enables TMDS PHY output */
/* TODO: still need depth or just pass in adjusted pixel clock? */ /* TODO: still need depth or just pass in adjusted pixel clock? */
void dcn10_link_encoder_enable_tmds_output( void dcn10_link_encoder_enable_tmds_output(