mirror of https://gitee.com/openkylin/linux.git
PCI: mediatek-gen3: Add MSI support
Add MSI support for MediaTek Gen3 PCIe controller.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-----+
| GIC |
+-----+
^
|
port->irq
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+-+-+-+-+-+-+-+-+
|0|1|2|3|4|5|6|7| (PCIe intc)
+-+-+-+-+-+-+-+-+
^ ^ ^
| | ... |
+-------+ +------+ +-----------+
| | |
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
|0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | | | (MSI vectors)
| | | | | | | | | | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Link: https://lore.kernel.org/r/20210420061723.989-6-jianjun.wang@mediatek.com
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
This commit is contained in:
Jianjun Wang
Lorenzo Pieralisi
parent
814cceebba
commit
1bdafba538
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@ -14,6 +14,7 @@
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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@ -48,12 +49,29 @@
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#define PCIE_LINK_STATUS_REG 0x154
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#define PCIE_PORT_LINKUP BIT(8)
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#define PCIE_MSI_SET_NUM 8
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#define PCIE_MSI_IRQS_PER_SET 32
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#define PCIE_MSI_IRQS_NUM \
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(PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
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#define PCIE_INT_ENABLE_REG 0x180
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#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
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#define PCIE_MSI_SHIFT 8
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#define PCIE_INTX_SHIFT 24
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#define PCIE_INTX_ENABLE \
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GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
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#define PCIE_INT_STATUS_REG 0x184
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#define PCIE_MSI_SET_ENABLE_REG 0x190
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#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
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#define PCIE_MSI_SET_BASE_REG 0xc00
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#define PCIE_MSI_SET_OFFSET 0x10
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#define PCIE_MSI_SET_STATUS_OFFSET 0x04
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#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
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#define PCIE_MSI_SET_ADDR_HI_BASE 0xc80
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#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
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#define PCIE_TRANS_TABLE_BASE_REG 0x800
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#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
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@ -73,6 +91,16 @@
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#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
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#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
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/**
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* struct mtk_msi_set - MSI information for each set
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* @base: IO mapped register base
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* @msg_addr: MSI message address
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*/
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struct mtk_msi_set {
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void __iomem *base;
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phys_addr_t msg_addr;
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};
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/**
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* struct mtk_pcie_port - PCIe port information
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* @dev: pointer to PCIe device
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@ -86,6 +114,11 @@
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* @irq: PCIe controller interrupt number
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* @irq_lock: lock protecting IRQ register access
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* @intx_domain: legacy INTx IRQ domain
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* @msi_domain: MSI IRQ domain
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* @msi_bottom_domain: MSI IRQ bottom domain
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* @msi_sets: MSI sets information
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* @lock: lock protecting IRQ bit map
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* @msi_irq_in_use: bit map for assigned MSI IRQ
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*/
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struct mtk_pcie_port {
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struct device *dev;
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@ -100,6 +133,11 @@ struct mtk_pcie_port {
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int irq;
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raw_spinlock_t irq_lock;
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struct irq_domain *intx_domain;
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struct irq_domain *msi_domain;
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struct irq_domain *msi_bottom_domain;
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struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
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struct mutex lock;
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DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
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};
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/**
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@ -196,6 +234,35 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,
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return 0;
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}
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static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
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{
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int i;
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u32 val;
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for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
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struct mtk_msi_set *msi_set = &port->msi_sets[i];
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msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
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i * PCIE_MSI_SET_OFFSET;
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msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
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i * PCIE_MSI_SET_OFFSET;
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/* Configure the MSI capture address */
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writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
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writel_relaxed(upper_32_bits(msi_set->msg_addr),
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port->base + PCIE_MSI_SET_ADDR_HI_BASE +
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i * PCIE_MSI_SET_ADDR_HI_OFFSET);
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}
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val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG);
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val |= PCIE_MSI_SET_ENABLE;
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writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG);
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val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
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val |= PCIE_MSI_ENABLE;
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writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
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}
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static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
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{
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struct resource_entry *entry;
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@ -247,6 +314,8 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
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return err;
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}
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mtk_pcie_enable_msi(port);
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/* Set PCIe translation windows */
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resource_list_for_each_entry(entry, &host->windows) {
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struct resource *res = entry->res;
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@ -289,6 +358,147 @@ static int mtk_pcie_set_affinity(struct irq_data *data,
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return -EINVAL;
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}
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static void mtk_pcie_msi_irq_mask(struct irq_data *data)
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{
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pci_msi_mask_irq(data);
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irq_chip_mask_parent(data);
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}
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static void mtk_pcie_msi_irq_unmask(struct irq_data *data)
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{
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pci_msi_unmask_irq(data);
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irq_chip_unmask_parent(data);
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}
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static struct irq_chip mtk_msi_irq_chip = {
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = mtk_pcie_msi_irq_mask,
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.irq_unmask = mtk_pcie_msi_irq_unmask,
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.name = "MSI",
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};
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static struct msi_domain_info mtk_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
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.chip = &mtk_msi_irq_chip,
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};
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static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
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struct mtk_pcie_port *port = data->domain->host_data;
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unsigned long hwirq;
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
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msg->address_hi = upper_32_bits(msi_set->msg_addr);
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msg->address_lo = lower_32_bits(msi_set->msg_addr);
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msg->data = hwirq;
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dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",
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hwirq, msg->address_hi, msg->address_lo, msg->data);
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}
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static void mtk_msi_bottom_irq_ack(struct irq_data *data)
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{
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
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unsigned long hwirq;
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
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writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
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}
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static void mtk_msi_bottom_irq_mask(struct irq_data *data)
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{
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
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struct mtk_pcie_port *port = data->domain->host_data;
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unsigned long hwirq, flags;
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u32 val;
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
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raw_spin_lock_irqsave(&port->irq_lock, flags);
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val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
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val &= ~BIT(hwirq);
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writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
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raw_spin_unlock_irqrestore(&port->irq_lock, flags);
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}
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static void mtk_msi_bottom_irq_unmask(struct irq_data *data)
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{
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struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data);
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struct mtk_pcie_port *port = data->domain->host_data;
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unsigned long hwirq, flags;
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u32 val;
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hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET;
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raw_spin_lock_irqsave(&port->irq_lock, flags);
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val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
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val |= BIT(hwirq);
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writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
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raw_spin_unlock_irqrestore(&port->irq_lock, flags);
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}
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static struct irq_chip mtk_msi_bottom_irq_chip = {
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.irq_ack = mtk_msi_bottom_irq_ack,
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.irq_mask = mtk_msi_bottom_irq_mask,
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.irq_unmask = mtk_msi_bottom_irq_unmask,
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.irq_compose_msi_msg = mtk_compose_msi_msg,
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.irq_set_affinity = mtk_pcie_set_affinity,
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.name = "MSI",
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};
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static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *arg)
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{
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struct mtk_pcie_port *port = domain->host_data;
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struct mtk_msi_set *msi_set;
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int i, hwirq, set_idx;
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mutex_lock(&port->lock);
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hwirq = bitmap_find_free_region(port->msi_irq_in_use, PCIE_MSI_IRQS_NUM,
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order_base_2(nr_irqs));
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mutex_unlock(&port->lock);
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if (hwirq < 0)
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return -ENOSPC;
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set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
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msi_set = &port->msi_sets[set_idx];
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&mtk_msi_bottom_irq_chip, msi_set,
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handle_edge_irq, NULL, NULL);
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return 0;
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}
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static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct mtk_pcie_port *port = domain->host_data;
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struct irq_data *data = irq_domain_get_irq_data(domain, virq);
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mutex_lock(&port->lock);
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bitmap_release_region(port->msi_irq_in_use, data->hwirq,
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order_base_2(nr_irqs));
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mutex_unlock(&port->lock);
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {
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.alloc = mtk_msi_bottom_domain_alloc,
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.free = mtk_msi_bottom_domain_free,
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};
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static void mtk_intx_mask(struct irq_data *data)
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{
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struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
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@ -357,6 +567,7 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
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{
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struct device *dev = port->dev;
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struct device_node *intc_node, *node = dev->of_node;
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int ret;
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raw_spin_lock_init(&port->irq_lock);
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@ -374,7 +585,34 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
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return -ENODEV;
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}
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/* Setup MSI */
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mutex_init(&port->lock);
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port->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,
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&mtk_msi_bottom_domain_ops, port);
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if (!port->msi_bottom_domain) {
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dev_err(dev, "failed to create MSI bottom domain\n");
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ret = -ENODEV;
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goto err_msi_bottom_domain;
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}
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port->msi_domain = pci_msi_create_irq_domain(dev->fwnode,
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&mtk_msi_domain_info,
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port->msi_bottom_domain);
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if (!port->msi_domain) {
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dev_err(dev, "failed to create MSI domain\n");
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ret = -ENODEV;
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goto err_msi_domain;
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}
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return 0;
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err_msi_domain:
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irq_domain_remove(port->msi_bottom_domain);
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err_msi_bottom_domain:
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irq_domain_remove(port->intx_domain);
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return ret;
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}
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static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port)
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@ -384,9 +622,39 @@ static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port)
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if (port->intx_domain)
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irq_domain_remove(port->intx_domain);
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if (port->msi_domain)
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irq_domain_remove(port->msi_domain);
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if (port->msi_bottom_domain)
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irq_domain_remove(port->msi_bottom_domain);
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irq_dispose_mapping(port->irq);
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}
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static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)
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{
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struct mtk_msi_set *msi_set = &port->msi_sets[set_idx];
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unsigned long msi_enable, msi_status;
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unsigned int virq;
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irq_hw_number_t bit, hwirq;
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msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
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do {
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msi_status = readl_relaxed(msi_set->base +
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PCIE_MSI_SET_STATUS_OFFSET);
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msi_status &= msi_enable;
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if (!msi_status)
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break;
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for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) {
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hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET;
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virq = irq_find_mapping(port->msi_bottom_domain, hwirq);
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generic_handle_irq(virq);
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}
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} while (true);
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}
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static void mtk_pcie_irq_handler(struct irq_desc *desc)
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{
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struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
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@ -405,6 +673,14 @@ static void mtk_pcie_irq_handler(struct irq_desc *desc)
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generic_handle_irq(virq);
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}
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irq_bit = PCIE_MSI_SHIFT;
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for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
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PCIE_MSI_SHIFT) {
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mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT);
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writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG);
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}
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chained_irq_exit(irqchip, desc);
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}
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