mirror of https://gitee.com/openkylin/linux.git
spi: spi-zynqmp-gqspi: Update driver to use spi-mem framework
Updated Zynqmp qspi controller driver to use spi-mem framework. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/490a7642a975f4d3dd9618304e9e45f7e2414661.1600931476.git.michal.simek@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Amit Kumar Mahapatra
Mark Brown
parent
91af6eb04a
commit
1c26372e5a
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@ -21,6 +21,7 @@
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#include <linux/spi/spi.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/spi/spi-mem.h>
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/* Generic QSPI register offsets */
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#define GQSPI_CONFIG_OFST 0x00000100
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@ -153,6 +154,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
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* @dma_addr: DMA address after mapping the kernel buffer
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* @genfifoentry: Used for storing the genfifoentry instruction.
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* @mode: Defines the mode in which QSPI is operating
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* @data_completion: completion structure
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*/
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struct zynqmp_qspi {
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void __iomem *regs;
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@ -170,6 +172,7 @@ struct zynqmp_qspi {
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dma_addr_t dma_addr;
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u32 genfifoentry;
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enum mode_type mode;
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struct completion data_completion;
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};
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/**
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@ -344,40 +347,6 @@ static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
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xqspi->bytes_to_receive -= size;
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}
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/**
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* zynqmp_prepare_transfer_hardware - Prepares hardware for transfer.
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* @master: Pointer to the spi_master structure which provides
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* information about the controller.
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*
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* This function enables SPI master controller.
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*
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* Return: 0 on success; error value otherwise
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*/
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static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
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{
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struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
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zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
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return 0;
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}
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/**
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* zynqmp_unprepare_transfer_hardware - Relaxes hardware after transfer
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* @master: Pointer to the spi_master structure which provides
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* information about the controller.
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*
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* This function disables the SPI master controller.
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*
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* Return: Always 0
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*/
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static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
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{
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struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
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zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
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return 0;
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}
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/**
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* zynqmp_qspi_chipselect - Select or deselect the chip select line
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* @qspi: Pointer to the spi_device structure
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@ -387,12 +356,14 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
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{
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struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
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ulong timeout;
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u32 genfifoentry = 0x0, statusreg;
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u32 genfifoentry = 0, statusreg;
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genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
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genfifoentry |= xqspi->genfifobus;
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if (!is_high) {
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xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
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xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
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genfifoentry |= xqspi->genfifobus;
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genfifoentry |= xqspi->genfifocs;
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genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
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} else {
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@ -424,11 +395,38 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
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}
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/**
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* zynqmp_qspi_setup_transfer - Configure QSPI controller for specified
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* zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
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* @xqspi: xqspi is a pointer to the GQSPI instance
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* @spimode: spimode - SPI or DUAL or QUAD.
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* Return: Mask to set desired SPI mode in GENFIFO entry.
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*/
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static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
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u8 spimode)
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{
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u32 mask = 0;
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switch (spimode) {
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case GQSPI_SELECT_MODE_DUALSPI:
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mask = GQSPI_GENFIFO_MODE_DUALSPI;
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break;
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case GQSPI_SELECT_MODE_QUADSPI:
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mask = GQSPI_GENFIFO_MODE_QUADSPI;
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break;
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case GQSPI_SELECT_MODE_SPI:
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mask = GQSPI_GENFIFO_MODE_SPI;
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break;
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default:
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dev_warn(xqspi->dev, "Invalid SPI mode\n");
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}
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return mask;
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}
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/**
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* zynqmp_qspi_config_op - Configure QSPI controller for specified
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* transfer
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @qspi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer setup parameters
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*
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* Sets the operational mode of QSPI controller for the next QSPI transfer and
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* sets the requested clock frequency.
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@ -445,17 +443,11 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
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* by the QSPI controller the driver will set the highest or lowest
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* frequency supported by controller.
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*/
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static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
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struct spi_transfer *transfer)
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static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
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struct spi_device *qspi)
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{
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struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
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ulong clk_rate;
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u32 config_reg, req_hz, baud_rate_val = 0;
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if (transfer)
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req_hz = transfer->speed_hz;
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else
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req_hz = qspi->max_speed_hz;
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u32 config_reg, baud_rate_val = 0;
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/* Set the clock frequency */
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/* If req_hz == 0, default to lowest speed */
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@ -463,7 +455,7 @@ static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
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while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
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(clk_rate /
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(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
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(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
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baud_rate_val++;
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config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
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@ -483,7 +475,7 @@ static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
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}
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/**
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* zynqmp_qspi_setup - Configure the QSPI controller
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* zynqmp_qspi_setup_op - Configure the QSPI controller
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* @qspi: Pointer to the spi_device structure
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*
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* Sets the operational mode of QSPI controller for the next QSPI transfer,
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@ -491,10 +483,30 @@ static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
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*
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* Return: 0 on success; error value otherwise.
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*/
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static int zynqmp_qspi_setup(struct spi_device *qspi)
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static int zynqmp_qspi_setup_op(struct spi_device *qspi)
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{
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if (qspi->master->busy)
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struct spi_controller *ctlr = qspi->master;
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struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
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struct device *dev = &ctlr->dev;
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int ret;
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if (ctlr->busy)
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return -EBUSY;
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ret = clk_enable(xqspi->refclk);
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if (ret) {
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dev_err(dev, "Cannot enable device clock.\n");
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return ret;
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}
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ret = clk_enable(xqspi->pclk);
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if (ret) {
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dev_err(dev, "Cannot enable APB clock.\n");
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clk_disable(xqspi->refclk);
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return ret;
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}
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zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
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return 0;
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}
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@ -552,6 +564,75 @@ static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
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}
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}
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/**
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* zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @nbits: Transfer/Receive buswidth.
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* @genfifoentry: Variable in which GENFIFO mask is saved
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*/
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static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
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u32 genfifoentry)
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{
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u32 transfer_len = 0;
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if (xqspi->txbuf) {
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genfifoentry &= ~GQSPI_GENFIFO_RX;
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genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
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genfifoentry |= GQSPI_GENFIFO_TX;
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transfer_len = xqspi->bytes_to_transfer;
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} else {
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genfifoentry &= ~GQSPI_GENFIFO_TX;
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genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
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genfifoentry |= GQSPI_GENFIFO_RX;
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if (xqspi->mode == GQSPI_MODE_DMA)
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transfer_len = xqspi->dma_rx_bytes;
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else
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transfer_len = xqspi->bytes_to_receive;
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}
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genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
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xqspi->genfifoentry = genfifoentry;
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if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
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genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
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genfifoentry |= transfer_len;
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zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
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} else {
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int tempcount = transfer_len;
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u32 exponent = 8; /* 2^8 = 256 */
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u8 imm_data = tempcount & 0xFF;
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tempcount &= ~(tempcount & 0xFF);
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/* Immediate entry */
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if (tempcount != 0) {
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/* Exponent entries */
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genfifoentry |= GQSPI_GENFIFO_EXP;
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while (tempcount != 0) {
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if (tempcount & GQSPI_GENFIFO_EXP_START) {
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genfifoentry &=
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~GQSPI_GENFIFO_IMM_DATA_MASK;
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genfifoentry |= exponent;
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zynqmp_gqspi_write(xqspi,
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GQSPI_GEN_FIFO_OFST,
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genfifoentry);
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}
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tempcount = tempcount >> 1;
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exponent++;
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}
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}
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if (imm_data != 0) {
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genfifoentry &= ~GQSPI_GENFIFO_EXP;
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genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
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genfifoentry |= (u8)(imm_data & 0xFF);
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zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
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genfifoentry);
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}
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}
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if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
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/* Dummy generic FIFO entry */
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zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
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}
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}
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/**
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* zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
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* controller
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@ -614,9 +695,8 @@ static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
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*/
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static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
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int ret = IRQ_NONE;
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struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
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irqreturn_t ret = IRQ_NONE;
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u32 status, mask, dma_status = 0;
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status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
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@ -648,45 +728,17 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
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if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
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&& ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
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zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
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spi_finalize_current_transfer(master);
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complete(&xqspi->data_completion);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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/**
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* zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
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* @xqspi: xqspi is a pointer to the GQSPI instance
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* @spimode: spimode - SPI or DUAL or QUAD.
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* Return: Mask to set desired SPI mode in GENFIFO entry.
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*/
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static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
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u8 spimode)
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{
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u32 mask = 0;
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switch (spimode) {
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case GQSPI_SELECT_MODE_DUALSPI:
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mask = GQSPI_GENFIFO_MODE_DUALSPI;
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break;
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case GQSPI_SELECT_MODE_QUADSPI:
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mask = GQSPI_GENFIFO_MODE_QUADSPI;
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break;
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case GQSPI_SELECT_MODE_SPI:
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mask = GQSPI_GENFIFO_MODE_SPI;
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break;
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default:
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dev_warn(xqspi->dev, "Invalid SPI mode\n");
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}
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return mask;
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}
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/**
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* zynq_qspi_setuprxdma - This function sets up the RX DMA operation
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* zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
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* @xqspi: xqspi is a pointer to the GQSPI instance.
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*/
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static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
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static void zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
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{
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u32 rx_bytes, rx_rem, config_reg;
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dma_addr_t addr;
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@ -733,162 +785,44 @@ static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
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}
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/**
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* zynqmp_qspi_txrxsetup - This function checks the TX/RX buffers in
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* the transfer and sets up the GENFIFO entries,
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* TX FIFO as required.
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* @xqspi: xqspi is a pointer to the GQSPI instance.
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* @transfer: It is a pointer to the structure containing transfer data.
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* @genfifoentry: genfifoentry is pointer to the variable in which
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* GENFIFO mask is returned to calling function
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* zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
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* TX FIFO, and fills the TX FIFO with as many
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* bytes as possible.
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* @xqspi: Pointer to the GQSPI instance.
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* @tx_nbits: Transfer buswidth.
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* @genfifoentry: Variable in which GENFIFO mask is returned
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* to calling function
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*/
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static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
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struct spi_transfer *transfer,
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u32 *genfifoentry)
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static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
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u32 genfifoentry)
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{
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u32 config_reg;
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/* Transmit */
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if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
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/* Setup data to be TXed */
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*genfifoentry &= ~GQSPI_GENFIFO_RX;
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*genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
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*genfifoentry |= GQSPI_GENFIFO_TX;
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*genfifoentry |=
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zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
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xqspi->bytes_to_transfer = transfer->len;
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if (xqspi->mode == GQSPI_MODE_DMA) {
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config_reg = zynqmp_gqspi_read(xqspi,
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GQSPI_CONFIG_OFST);
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config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
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zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
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config_reg);
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xqspi->mode = GQSPI_MODE_IO;
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}
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zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
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/* Discard RX data */
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xqspi->bytes_to_receive = 0;
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} else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
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/* Receive */
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/* TX auto fill */
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*genfifoentry &= ~GQSPI_GENFIFO_TX;
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/* Setup RX */
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*genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
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*genfifoentry |= GQSPI_GENFIFO_RX;
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*genfifoentry |=
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zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
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xqspi->bytes_to_transfer = 0;
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xqspi->bytes_to_receive = transfer->len;
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zynq_qspi_setuprxdma(xqspi);
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zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
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zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
|
||||
if (xqspi->mode == GQSPI_MODE_DMA) {
|
||||
config_reg = zynqmp_gqspi_read(xqspi,
|
||||
GQSPI_CONFIG_OFST);
|
||||
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
config_reg);
|
||||
xqspi->mode = GQSPI_MODE_IO;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_qspi_start_transfer - Initiates the QSPI transfer
|
||||
* @master: Pointer to the spi_master structure which provides
|
||||
* information about the controller.
|
||||
* @qspi: Pointer to the spi_device structure
|
||||
* @transfer: Pointer to the spi_transfer structure which provide information
|
||||
* about next transfer parameters
|
||||
*
|
||||
* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
|
||||
* transfer to be completed.
|
||||
*
|
||||
* Return: Number of bytes transferred in the last transfer
|
||||
* zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
|
||||
* RX DMA operation.
|
||||
* @xqspi: xqspi is a pointer to the GQSPI instance.
|
||||
* @rx_nbits: Receive buswidth.
|
||||
* @genfifoentry: genfifoentry is pointer to the variable in which
|
||||
* GENFIFO mask is returned to calling function
|
||||
*/
|
||||
static int zynqmp_qspi_start_transfer(struct spi_master *master,
|
||||
struct spi_device *qspi,
|
||||
struct spi_transfer *transfer)
|
||||
static void zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
|
||||
u32 genfifoentry)
|
||||
{
|
||||
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
|
||||
u32 genfifoentry = 0x0, transfer_len;
|
||||
|
||||
xqspi->txbuf = transfer->tx_buf;
|
||||
xqspi->rxbuf = transfer->rx_buf;
|
||||
|
||||
zynqmp_qspi_setup_transfer(qspi, transfer);
|
||||
|
||||
genfifoentry |= xqspi->genfifocs;
|
||||
genfifoentry |= xqspi->genfifobus;
|
||||
|
||||
zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
|
||||
|
||||
if (xqspi->mode == GQSPI_MODE_DMA)
|
||||
transfer_len = xqspi->dma_rx_bytes;
|
||||
else
|
||||
transfer_len = transfer->len;
|
||||
|
||||
xqspi->genfifoentry = genfifoentry;
|
||||
if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
|
||||
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
|
||||
genfifoentry |= transfer_len;
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
|
||||
} else {
|
||||
int tempcount = transfer_len;
|
||||
u32 exponent = 8; /* 2^8 = 256 */
|
||||
u8 imm_data = tempcount & 0xFF;
|
||||
|
||||
tempcount &= ~(tempcount & 0xFF);
|
||||
/* Immediate entry */
|
||||
if (tempcount != 0) {
|
||||
/* Exponent entries */
|
||||
genfifoentry |= GQSPI_GENFIFO_EXP;
|
||||
while (tempcount != 0) {
|
||||
if (tempcount & GQSPI_GENFIFO_EXP_START) {
|
||||
genfifoentry &=
|
||||
~GQSPI_GENFIFO_IMM_DATA_MASK;
|
||||
genfifoentry |= exponent;
|
||||
zynqmp_gqspi_write(xqspi,
|
||||
GQSPI_GEN_FIFO_OFST,
|
||||
genfifoentry);
|
||||
}
|
||||
tempcount = tempcount >> 1;
|
||||
exponent++;
|
||||
}
|
||||
}
|
||||
if (imm_data != 0) {
|
||||
genfifoentry &= ~GQSPI_GENFIFO_EXP;
|
||||
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
|
||||
genfifoentry |= (u8) (imm_data & 0xFF);
|
||||
zynqmp_gqspi_write(xqspi,
|
||||
GQSPI_GEN_FIFO_OFST, genfifoentry);
|
||||
}
|
||||
}
|
||||
|
||||
if ((xqspi->mode == GQSPI_MODE_IO) &&
|
||||
(xqspi->rxbuf != NULL)) {
|
||||
/* Dummy generic FIFO entry */
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
|
||||
}
|
||||
|
||||
/* Since we are using manual mode */
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
|
||||
if (xqspi->txbuf != NULL)
|
||||
/* Enable interrupts for TX */
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_TXEMPTY_MASK |
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_TXNOT_FULL_MASK);
|
||||
|
||||
if (xqspi->rxbuf != NULL) {
|
||||
/* Enable interrupts for RX */
|
||||
if (xqspi->mode == GQSPI_MODE_DMA) {
|
||||
/* Enable DMA interrupts */
|
||||
zynqmp_gqspi_write(xqspi,
|
||||
GQSPI_QSPIDMA_DST_I_EN_OFST,
|
||||
GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
|
||||
} else {
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_RXNEMPTY_MASK |
|
||||
GQSPI_IER_RXEMPTY_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
return transfer->len;
|
||||
zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
|
||||
zynqmp_qspi_setuprxdma(xqspi);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -901,11 +835,12 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master,
|
|||
*/
|
||||
static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
||||
struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
|
||||
|
||||
spi_master_suspend(master);
|
||||
spi_controller_suspend(ctlr);
|
||||
|
||||
zynqmp_unprepare_transfer_hardware(master);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -921,8 +856,8 @@ static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
|
|||
*/
|
||||
static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
||||
struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_enable(xqspi->pclk);
|
||||
|
|
@ -938,7 +873,7 @@ static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
spi_master_resume(master);
|
||||
spi_controller_resume(ctlr);
|
||||
|
||||
clk_disable(xqspi->refclk);
|
||||
clk_disable(xqspi->pclk);
|
||||
|
|
@ -955,8 +890,7 @@ static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
|
|||
*/
|
||||
static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
|
||||
struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
|
||||
|
||||
clk_disable(xqspi->refclk);
|
||||
clk_disable(xqspi->pclk);
|
||||
|
|
@ -974,8 +908,7 @@ static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
|
|||
*/
|
||||
static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
|
||||
struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(xqspi->pclk);
|
||||
|
|
@ -994,12 +927,177 @@ static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_qspi_exec_op() - Initiates the QSPI transfer
|
||||
* @mem: The SPI memory
|
||||
* @op: The memory operation to execute
|
||||
*
|
||||
* Executes a memory operation.
|
||||
*
|
||||
* This function first selects the chip and starts the memory operation.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error code otherwise.
|
||||
*/
|
||||
static int zynqmp_qspi_exec_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct zynqmp_qspi *xqspi = spi_controller_get_devdata
|
||||
(mem->spi->master);
|
||||
int err = 0, i;
|
||||
u8 *tmpbuf;
|
||||
u32 genfifoentry = 0;
|
||||
|
||||
dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
|
||||
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
|
||||
op->dummy.buswidth, op->data.buswidth);
|
||||
|
||||
zynqmp_qspi_config_op(xqspi, mem->spi);
|
||||
zynqmp_qspi_chipselect(mem->spi, false);
|
||||
genfifoentry |= xqspi->genfifocs;
|
||||
genfifoentry |= xqspi->genfifobus;
|
||||
|
||||
if (op->cmd.opcode) {
|
||||
tmpbuf = kzalloc(op->cmd.nbytes, GFP_KERNEL | GFP_DMA);
|
||||
if (!tmpbuf)
|
||||
return -ENOMEM;
|
||||
tmpbuf[0] = op->cmd.opcode;
|
||||
reinit_completion(&xqspi->data_completion);
|
||||
xqspi->txbuf = tmpbuf;
|
||||
xqspi->rxbuf = NULL;
|
||||
xqspi->bytes_to_transfer = op->cmd.nbytes;
|
||||
xqspi->bytes_to_receive = 0;
|
||||
zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_TXNOT_FULL_MASK);
|
||||
if (!wait_for_completion_interruptible_timeout
|
||||
(&xqspi->data_completion, msecs_to_jiffies(1000))) {
|
||||
err = -ETIMEDOUT;
|
||||
kfree(tmpbuf);
|
||||
goto return_err;
|
||||
}
|
||||
kfree(tmpbuf);
|
||||
}
|
||||
|
||||
if (op->addr.nbytes) {
|
||||
for (i = 0; i < op->addr.nbytes; i++) {
|
||||
*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
|
||||
(8 * (op->addr.nbytes - i - 1));
|
||||
}
|
||||
|
||||
reinit_completion(&xqspi->data_completion);
|
||||
xqspi->rxbuf = NULL;
|
||||
xqspi->bytes_to_transfer = op->addr.nbytes;
|
||||
xqspi->bytes_to_receive = 0;
|
||||
zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read(xqspi,
|
||||
GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_TXEMPTY_MASK |
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_TXNOT_FULL_MASK);
|
||||
if (!wait_for_completion_interruptible_timeout
|
||||
(&xqspi->data_completion, msecs_to_jiffies(1000))) {
|
||||
err = -ETIMEDOUT;
|
||||
goto return_err;
|
||||
}
|
||||
}
|
||||
|
||||
if (op->dummy.nbytes) {
|
||||
tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL | GFP_DMA);
|
||||
if (!tmpbuf)
|
||||
return -ENOMEM;
|
||||
memset(tmpbuf, 0xff, op->dummy.nbytes);
|
||||
reinit_completion(&xqspi->data_completion);
|
||||
xqspi->txbuf = tmpbuf;
|
||||
xqspi->rxbuf = NULL;
|
||||
xqspi->bytes_to_transfer = op->dummy.nbytes;
|
||||
xqspi->bytes_to_receive = 0;
|
||||
zynqmp_qspi_write_op(xqspi, op->dummy.buswidth,
|
||||
genfifoentry);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_TXEMPTY_MASK |
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_TXNOT_FULL_MASK);
|
||||
if (!wait_for_completion_interruptible_timeout
|
||||
(&xqspi->data_completion, msecs_to_jiffies(1000))) {
|
||||
err = -ETIMEDOUT;
|
||||
kfree(tmpbuf);
|
||||
goto return_err;
|
||||
}
|
||||
|
||||
kfree(tmpbuf);
|
||||
}
|
||||
|
||||
if (op->data.nbytes) {
|
||||
reinit_completion(&xqspi->data_completion);
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT) {
|
||||
xqspi->txbuf = (u8 *)op->data.buf.out;
|
||||
xqspi->rxbuf = NULL;
|
||||
xqspi->bytes_to_transfer = op->data.nbytes;
|
||||
xqspi->bytes_to_receive = 0;
|
||||
zynqmp_qspi_write_op(xqspi, op->data.buswidth,
|
||||
genfifoentry);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read
|
||||
(xqspi, GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_TXEMPTY_MASK |
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_TXNOT_FULL_MASK);
|
||||
} else {
|
||||
xqspi->txbuf = NULL;
|
||||
xqspi->rxbuf = (u8 *)op->data.buf.in;
|
||||
xqspi->bytes_to_receive = op->data.nbytes;
|
||||
xqspi->bytes_to_transfer = 0;
|
||||
zynqmp_qspi_read_op(xqspi, op->data.buswidth,
|
||||
genfifoentry);
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
||||
zynqmp_gqspi_read
|
||||
(xqspi, GQSPI_CONFIG_OFST) |
|
||||
GQSPI_CFG_START_GEN_FIFO_MASK);
|
||||
if (xqspi->mode == GQSPI_MODE_DMA) {
|
||||
zynqmp_gqspi_write
|
||||
(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
|
||||
GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
|
||||
} else {
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
||||
GQSPI_IER_GENFIFOEMPTY_MASK |
|
||||
GQSPI_IER_RXNEMPTY_MASK |
|
||||
GQSPI_IER_RXEMPTY_MASK);
|
||||
}
|
||||
}
|
||||
if (!wait_for_completion_interruptible_timeout
|
||||
(&xqspi->data_completion, msecs_to_jiffies(1000)))
|
||||
err = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return_err:
|
||||
|
||||
zynqmp_qspi_chipselect(mem->spi, true);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
|
||||
zynqmp_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
|
||||
};
|
||||
|
||||
static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
|
||||
.exec_op = zynqmp_qspi_exec_op,
|
||||
};
|
||||
|
||||
/**
|
||||
* zynqmp_qspi_probe - Probe method for the QSPI driver
|
||||
* @pdev: Pointer to the platform_device structure
|
||||
|
|
@ -1011,17 +1109,18 @@ static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
|
|||
static int zynqmp_qspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *ctlr;
|
||||
struct zynqmp_qspi *xqspi;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
|
||||
if (!master)
|
||||
ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
||||
xqspi = spi_master_get_devdata(master);
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
platform_set_drvdata(pdev, master);
|
||||
xqspi = spi_controller_get_devdata(ctlr);
|
||||
xqspi->dev = dev;
|
||||
platform_set_drvdata(pdev, xqspi);
|
||||
|
||||
xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(xqspi->regs)) {
|
||||
|
|
@ -1029,7 +1128,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
goto remove_master;
|
||||
}
|
||||
|
||||
xqspi->dev = dev;
|
||||
xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(xqspi->pclk)) {
|
||||
dev_err(dev, "pclk clock not found.\n");
|
||||
|
|
@ -1037,11 +1135,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xqspi->pclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to enable APB clock.\n");
|
||||
goto remove_master;
|
||||
}
|
||||
init_completion(&xqspi->data_completion);
|
||||
|
||||
xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
|
||||
if (IS_ERR(xqspi->refclk)) {
|
||||
|
|
@ -1050,6 +1144,12 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
goto clk_dis_pclk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xqspi->pclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to enable APB clock.\n");
|
||||
goto remove_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(xqspi->refclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to enable device clock.\n");
|
||||
|
|
@ -1071,32 +1171,28 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
goto clk_dis_all;
|
||||
}
|
||||
ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
|
||||
0, pdev->name, master);
|
||||
0, pdev->name, xqspi);
|
||||
if (ret != 0) {
|
||||
ret = -ENXIO;
|
||||
dev_err(dev, "request_irq failed\n");
|
||||
goto clk_dis_all;
|
||||
}
|
||||
|
||||
master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
|
||||
|
||||
master->setup = zynqmp_qspi_setup;
|
||||
master->set_cs = zynqmp_qspi_chipselect;
|
||||
master->transfer_one = zynqmp_qspi_start_transfer;
|
||||
master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
|
||||
master->unprepare_transfer_hardware =
|
||||
zynqmp_unprepare_transfer_hardware;
|
||||
master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
|
||||
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
|
||||
ctlr->mem_ops = &zynqmp_qspi_mem_ops;
|
||||
ctlr->setup = zynqmp_qspi_setup_op;
|
||||
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
|
||||
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
|
||||
SPI_TX_DUAL | SPI_TX_QUAD;
|
||||
ctlr->dev.of_node = np;
|
||||
|
||||
if (master->dev.parent == NULL)
|
||||
master->dev.parent = &master->dev;
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret)
|
||||
ret = devm_spi_register_controller(&pdev->dev, ctlr);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "spi_register_controller failed\n");
|
||||
goto clk_dis_all;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -1107,7 +1203,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
clk_dis_pclk:
|
||||
clk_disable_unprepare(xqspi->pclk);
|
||||
remove_master:
|
||||
spi_master_put(master);
|
||||
spi_controller_put(ctlr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1124,8 +1220,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|||
*/
|
||||
static int zynqmp_qspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
|
||||
struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
|
||||
|
||||
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
|
||||
clk_disable_unprepare(xqspi->refclk);
|
||||
|
|
@ -1133,8 +1228,6 @@ static int zynqmp_qspi_remove(struct platform_device *pdev)
|
|||
pm_runtime_set_suspended(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
spi_unregister_master(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue