mirror of https://gitee.com/openkylin/linux.git
tg3: Implement set/get_eee handlers
Reviewed-by: Ben Li <benli@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -13618,6 +13618,57 @@ static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
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return 0;
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}
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static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
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{
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struct tg3 *tp = netdev_priv(dev);
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if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
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netdev_warn(tp->dev, "Board does not support EEE!\n");
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return -EOPNOTSUPP;
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}
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if (edata->advertised != tp->eee.advertised) {
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netdev_warn(tp->dev,
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"Direct manipulation of EEE advertisement is not supported\n");
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return -EINVAL;
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}
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if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
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netdev_warn(tp->dev,
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"Maximal Tx Lpi timer supported is %#x(u)\n",
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TG3_CPMU_DBTMR1_LNKIDLE_MAX);
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return -EINVAL;
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}
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tp->eee = *edata;
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tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
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tg3_warn_mgmt_link_flap(tp);
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if (netif_running(tp->dev)) {
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tg3_full_lock(tp, 0);
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tg3_setup_eee(tp);
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tg3_phy_reset(tp);
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tg3_full_unlock(tp);
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}
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return 0;
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}
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static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
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{
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struct tg3 *tp = netdev_priv(dev);
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if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
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netdev_warn(tp->dev,
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"Board does not support EEE!\n");
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return -EOPNOTSUPP;
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}
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*edata = tp->eee;
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return 0;
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}
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static const struct ethtool_ops tg3_ethtool_ops = {
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.get_settings = tg3_get_settings,
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.set_settings = tg3_set_settings,
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@ -13651,6 +13702,8 @@ static const struct ethtool_ops tg3_ethtool_ops = {
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.get_channels = tg3_get_channels,
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.set_channels = tg3_set_channels,
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.get_ts_info = tg3_get_ts_info,
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.get_eee = tg3_get_eee,
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.set_eee = tg3_set_eee,
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};
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static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
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@ -1175,6 +1175,7 @@
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#define TG3_CPMU_EEE_DBTMR1 0x000036b4
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#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
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#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
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#define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff
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#define TG3_CPMU_EEE_DBTMR2 0x000036b8
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#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
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#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
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