mirror of https://gitee.com/openkylin/linux.git
[ARM] tegra: SMP support
Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
This commit is contained in:
Colin Cross
Erik Gilling
parent
d861196163
commit
1cea7326b3
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@ -1112,10 +1112,11 @@ config SMP
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bool "Symmetric Multi-Processing (EXPERIMENTAL)"
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depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
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MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
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ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
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ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_TEGRA)
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depends on GENERIC_CLOCKEVENTS
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select USE_GENERIC_SMP_HELPERS
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select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
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select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || \
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ARCH_VEXPRESS_CA9X4 || ARCH_TEGRA)
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help
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, like most personal computers, say N. If
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@ -1185,9 +1186,10 @@ config LOCAL_TIMERS
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bool "Use local timer interrupts"
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depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
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REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
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ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
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ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_TEGRA)
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default y
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select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
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select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || \\
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ARCH_U8500 || ARCH_TEGRA
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help
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Enable support for local timers on SMP platforms, rather then the
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legacy IPI broadcast method. Local timers allows the system
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@ -3,3 +3,5 @@ obj-y += io.o
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obj-y += irq.o
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obj-y += clock.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
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obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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@ -0,0 +1,61 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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__CPUINIT
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/*
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* Tegra specific entry point for secondary CPUs.
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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ENTRY(tegra_secondary_startup)
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msr cpsr_fsxc, #0xd3
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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ldr r1, =0x6000f100
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str r0, [r1]
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1: ldr r2, [r1]
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cmp r0, r2
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beq 1b
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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@ -0,0 +1,140 @@
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/*
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* linux/arch/arm/mach-realview/hotplug.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <linux/completion.h>
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#include <asm/cacheflush.h>
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static DECLARE_COMPLETION(cpu_killed);
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static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, #0x04\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "r" (0)
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: "cc");
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}
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static inline void cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile(
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"mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, #0x04\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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:
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: "cc");
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}
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static inline void platform_do_lowpower(unsigned int cpu)
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{
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/*
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* there is no power-control hardware on this platform, so all
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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for (;;) {
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/*
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* here's the WFI
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*/
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asm(".word 0xe320f003\n"
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:
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:
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: "memory", "cc");
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/*if (pen_release == cpu) {*/
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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/*}*/
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/*
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* getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* The trouble is, letting people know about this is not really
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* possible, since we are currently running incoherently, and
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* therefore cannot safely call printk() or anything else
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*/
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#ifdef DEBUG
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printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
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#endif
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}
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}
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int platform_cpu_kill(unsigned int cpu)
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{
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return wait_for_completion_timeout(&cpu_killed, 5000);
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void platform_cpu_die(unsigned int cpu)
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{
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#ifdef DEBUG
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unsigned int this_cpu = hard_smp_processor_id();
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if (cpu != this_cpu) {
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printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
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this_cpu, cpu);
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BUG();
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}
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#endif
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printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
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complete(&cpu_killed);
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/*
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* we're ready for shutdown now, so do it
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*/
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cpu_enter_lowpower();
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platform_do_lowpower(cpu);
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/*
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* bring this CPU back into the world of cache
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* coherency, and then restore interrupts
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*/
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cpu_leave_lowpower();
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}
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int platform_cpu_disable(unsigned int cpu)
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{
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/*
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* we don't allow CPU 0 to be shutdown (it is still too special
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* e.g. clock tick interrupts)
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*/
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return cpu == 0 ? -EPERM : 0;
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}
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@ -0,0 +1,30 @@
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#ifndef ASMARM_ARCH_SMP_H
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#define ASMARM_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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#define hard_smp_processor_id() \
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({ \
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unsigned int cpunum; \
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__asm__("mrc p15, 0, %0, c0, c0, 5" \
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: "=r" (cpunum)); \
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cpunum &= 0x0F; \
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})
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask)
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{
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gic_raise_softirq(mask, 1);
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}
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/*
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* Do nothing on MPcore.
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*/
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static inline void smp_cross_call_done(cpumask_t callmap)
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{
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}
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#endif
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@ -0,0 +1,25 @@
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/*
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* arch/arm/mach-tegra/localtimer.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/smp_twd.h>
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#include <asm/localtimer.h>
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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evt->irq = IRQ_LOCALTIMER;
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twd_timer_setup(evt);
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}
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@ -0,0 +1,156 @@
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/*
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* linux/arch/arm/mach-tegra/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* Copyright (C) 2009 Palm
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/localtimer.h>
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#include <asm/smp_scu.h>
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#include <mach/iomap.h>
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extern void tegra_secondary_startup(void);
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static DEFINE_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
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#define EVP_CPU_RESET_VECTOR \
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(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
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#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
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(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
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#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
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(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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trace_hardirqs_off();
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long old_boot_vector;
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unsigned long boot_vector;
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unsigned long timeout;
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u32 reg;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/* set the reset vector to point to the secondary_startup routine */
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boot_vector = virt_to_phys(tegra_secondary_startup);
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old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
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writel(boot_vector, EVP_CPU_RESET_VECTOR);
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/* enable cpu clock on cpu1 */
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reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
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writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
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reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
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writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
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smp_wmb();
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flush_cache_all();
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/* unhalt the cpu */
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writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
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break;
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udelay(10);
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}
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/* put the old boot vector back */
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writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores = scu_get_core_count(scu_base);
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for (i = 0; i < ncores; i++)
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cpu_set(i, cpu_possible_map);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int ncores = scu_get_core_count(scu_base);
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unsigned int cpu = smp_processor_id();
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int i;
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smp_store_cpu_info(cpu);
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/*
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* are we trying to boot more cores than exist?
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*/
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if (max_cpus > ncores)
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max_cpus = ncores;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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/*
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* Initialise the SCU if there are more than one CPU and let
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* them know where to start. Note that, on modern versions of
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* MILO, the "poke" doesn't actually do anything until each
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* individual core is sent a soft interrupt to get it out of
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* WFI
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*/
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if (max_cpus > 1) {
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percpu_timer_setup();
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scu_enable(scu_base);
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}
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}
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