mirror of https://gitee.com/openkylin/linux.git
powerpc/64s: introduce different functions to return from SRR vs HSRR interrupts
This makes no real difference yet except that HSRR type interrupts will use hrfid to return. This is important for the next patch. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210617155116.2167984-4-npiggin@gmail.com
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arch/powerpc/kernel
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@ -635,51 +635,57 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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* touched, no exit work created, then this can be used.
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* touched, no exit work created, then this can be used.
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*/
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*/
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.balign IFETCH_ALIGN_BYTES
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.balign IFETCH_ALIGN_BYTES
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.globl fast_interrupt_return
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.globl fast_interrupt_return_srr
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fast_interrupt_return:
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fast_interrupt_return_srr:
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_ASM_NOKPROBE_SYMBOL(fast_interrupt_return)
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_ASM_NOKPROBE_SYMBOL(fast_interrupt_return_srr)
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kuap_check_amr r3, r4
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kuap_check_amr r3, r4
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ld r5,_MSR(r1)
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ld r5,_MSR(r1)
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andi. r0,r5,MSR_PR
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andi. r0,r5,MSR_PR
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#ifdef CONFIG_PPC_BOOK3S
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#ifdef CONFIG_PPC_BOOK3S
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bne .Lfast_user_interrupt_return_amr
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bne .Lfast_user_interrupt_return_amr_srr
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kuap_kernel_restore r3, r4
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kuap_kernel_restore r3, r4
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andi. r0,r5,MSR_RI
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andi. r0,r5,MSR_RI
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li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
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li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
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bne+ .Lfast_kernel_interrupt_return
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bne+ .Lfast_kernel_interrupt_return_srr
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl unrecoverable_exception
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bl unrecoverable_exception
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b . /* should not get here */
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b . /* should not get here */
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#else
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#else
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bne .Lfast_user_interrupt_return
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bne .Lfast_user_interrupt_return_srr
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b .Lfast_kernel_interrupt_return
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b .Lfast_kernel_interrupt_return_srr
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#endif
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#endif
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.macro interrupt_return_macro srr
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.balign IFETCH_ALIGN_BYTES
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.balign IFETCH_ALIGN_BYTES
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.globl interrupt_return
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.globl interrupt_return_\srr
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interrupt_return:
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interrupt_return_\srr\():
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_ASM_NOKPROBE_SYMBOL(interrupt_return)
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_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\())
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ld r4,_MSR(r1)
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ld r4,_MSR(r1)
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andi. r0,r4,MSR_PR
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andi. r0,r4,MSR_PR
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beq .Lkernel_interrupt_return
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beq .Lkernel_interrupt_return_\srr
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl interrupt_exit_user_prepare
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bl interrupt_exit_user_prepare
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cmpdi r3,0
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cmpdi r3,0
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bne- .Lrestore_nvgprs
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bne- .Lrestore_nvgprs_\srr
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#ifdef CONFIG_PPC_BOOK3S
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#ifdef CONFIG_PPC_BOOK3S
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.Lfast_user_interrupt_return_amr:
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.Lfast_user_interrupt_return_amr_\srr\():
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kuap_user_restore r3, r4
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kuap_user_restore r3, r4
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#endif
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#endif
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.Lfast_user_interrupt_return:
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.Lfast_user_interrupt_return_\srr\():
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ld r11,_NIP(r1)
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ld r11,_NIP(r1)
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ld r12,_MSR(r1)
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ld r12,_MSR(r1)
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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION
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ld r10,_PPR(r1)
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ld r10,_PPR(r1)
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mtspr SPRN_PPR,r10
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mtspr SPRN_PPR,r10
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END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
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END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
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.ifc \srr,srr
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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mtspr SPRN_SRR1,r12
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.else
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mtspr SPRN_HSRR0,r11
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mtspr SPRN_HSRR1,r12
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.endif
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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION
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stdcx. r0,0,r1 /* to clear the reservation */
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stdcx. r0,0,r1 /* to clear the reservation */
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@ -706,24 +712,33 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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REST_GPR(6, r1)
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REST_GPR(6, r1)
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REST_GPR(0, r1)
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REST_GPR(0, r1)
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REST_GPR(1, r1)
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REST_GPR(1, r1)
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.ifc \srr,srr
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RFI_TO_USER
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RFI_TO_USER
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.else
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HRFI_TO_USER
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.endif
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b . /* prevent speculative execution */
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b . /* prevent speculative execution */
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.Lrestore_nvgprs:
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.Lrestore_nvgprs_\srr\():
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REST_NVGPRS(r1)
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REST_NVGPRS(r1)
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b .Lfast_user_interrupt_return
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b .Lfast_user_interrupt_return_\srr
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.balign IFETCH_ALIGN_BYTES
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.balign IFETCH_ALIGN_BYTES
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.Lkernel_interrupt_return:
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.Lkernel_interrupt_return_\srr\():
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl interrupt_exit_kernel_prepare
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bl interrupt_exit_kernel_prepare
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.Lfast_kernel_interrupt_return:
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.Lfast_kernel_interrupt_return_\srr\():
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cmpdi cr1,r3,0
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cmpdi cr1,r3,0
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ld r11,_NIP(r1)
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ld r11,_NIP(r1)
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ld r12,_MSR(r1)
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ld r12,_MSR(r1)
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.ifc \srr,srr
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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mtspr SPRN_SRR1,r12
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.else
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mtspr SPRN_HSRR0,r11
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mtspr SPRN_HSRR1,r12
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.endif
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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION
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stdcx. r0,0,r1 /* to clear the reservation */
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stdcx. r0,0,r1 /* to clear the reservation */
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@ -757,7 +772,11 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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REST_GPR(6, r1)
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REST_GPR(6, r1)
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REST_GPR(0, r1)
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REST_GPR(0, r1)
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REST_GPR(1, r1)
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REST_GPR(1, r1)
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.ifc \srr,srr
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RFI_TO_KERNEL
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RFI_TO_KERNEL
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.else
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HRFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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b . /* prevent speculative execution */
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1: /*
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1: /*
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@ -777,8 +796,18 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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std r9,0(r1) /* perform store component of stdu */
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std r9,0(r1) /* perform store component of stdu */
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ld r9,PACA_EXGEN+0(r13)
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ld r9,PACA_EXGEN+0(r13)
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.ifc \srr,srr
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RFI_TO_KERNEL
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RFI_TO_KERNEL
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.else
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HRFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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b . /* prevent speculative execution */
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.endm
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interrupt_return_macro srr
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#ifdef CONFIG_PPC_BOOK3S
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interrupt_return_macro hsrr
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#endif
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#ifdef CONFIG_PPC_RTAS
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#ifdef CONFIG_PPC_RTAS
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/*
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/*
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@ -26,6 +26,10 @@
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#include <asm/feature-fixups.h>
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#include <asm/feature-fixups.h>
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#include <asm/context_tracking.h>
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#include <asm/context_tracking.h>
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/* 64e interrupt returns always use SRR registers */
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#define fast_interrupt_return fast_interrupt_return_srr
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#define interrupt_return interrupt_return_srr
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/* XXX This will ultimately add space for a special exception save
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/* XXX This will ultimately add space for a special exception save
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* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
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* structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
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* when taking special interrupts. For now we don't support that,
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* when taking special interrupts. For now we don't support that,
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@ -1149,7 +1149,7 @@ EXC_COMMON_BEGIN(machine_check_common)
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mtmsrd r10,1
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mtmsrd r10,1
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_exception
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bl machine_check_exception
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b interrupt_return
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b interrupt_return_srr
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#ifdef CONFIG_PPC_P7_NAP
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#ifdef CONFIG_PPC_P7_NAP
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@ -1275,7 +1275,7 @@ BEGIN_MMU_FTR_SECTION
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MMU_FTR_SECTION_ELSE
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MMU_FTR_SECTION_ELSE
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bl do_page_fault
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bl do_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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b interrupt_return
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b interrupt_return_srr
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1: bl do_break
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1: bl do_break
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/*
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/*
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@ -1283,7 +1283,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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* If so, we need to restore them with their updated values.
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* If so, we need to restore them with their updated values.
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*/
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*/
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REST_NVGPRS(r1)
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REST_NVGPRS(r1)
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1323,7 +1323,7 @@ BEGIN_MMU_FTR_SECTION
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bl do_slb_fault
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bl do_slb_fault
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cmpdi r3,0
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cmpdi r3,0
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bne- 1f
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bne- 1f
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b fast_interrupt_return
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b fast_interrupt_return_srr
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1: /* Error case */
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1: /* Error case */
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MMU_FTR_SECTION_ELSE
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MMU_FTR_SECTION_ELSE
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/* Radix case, access is outside page table range */
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/* Radix case, access is outside page table range */
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@ -1332,7 +1332,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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std r3,RESULT(r1)
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std r3,RESULT(r1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl do_bad_slb_fault
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bl do_bad_slb_fault
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1368,7 +1368,7 @@ BEGIN_MMU_FTR_SECTION
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MMU_FTR_SECTION_ELSE
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MMU_FTR_SECTION_ELSE
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bl do_page_fault
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bl do_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1403,7 +1403,7 @@ BEGIN_MMU_FTR_SECTION
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bl do_slb_fault
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bl do_slb_fault
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cmpdi r3,0
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cmpdi r3,0
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bne- 1f
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bne- 1f
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b fast_interrupt_return
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b fast_interrupt_return_srr
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1: /* Error case */
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1: /* Error case */
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MMU_FTR_SECTION_ELSE
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MMU_FTR_SECTION_ELSE
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/* Radix case, access is outside page table range */
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/* Radix case, access is outside page table range */
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@ -1412,7 +1412,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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std r3,RESULT(r1)
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std r3,RESULT(r1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl do_bad_slb_fault
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bl do_bad_slb_fault
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1456,7 +1456,11 @@ EXC_COMMON_BEGIN(hardware_interrupt_common)
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GEN_COMMON hardware_interrupt
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GEN_COMMON hardware_interrupt
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl do_IRQ
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bl do_IRQ
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b interrupt_return
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BEGIN_FTR_SECTION
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b interrupt_return_hsrr
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FTR_SECTION_ELSE
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b interrupt_return_srr
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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/**
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/**
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@ -1483,7 +1487,7 @@ EXC_COMMON_BEGIN(alignment_common)
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl alignment_exception
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bl alignment_exception
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REST_NVGPRS(r1) /* instruction emulation may change GPRs */
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REST_NVGPRS(r1) /* instruction emulation may change GPRs */
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1590,7 +1594,7 @@ EXC_COMMON_BEGIN(program_check_common)
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl program_check_exception
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bl program_check_exception
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REST_NVGPRS(r1) /* instruction emulation may change GPRs */
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REST_NVGPRS(r1) /* instruction emulation may change GPRs */
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b interrupt_return
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b interrupt_return_srr
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/*
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/*
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@ -1633,12 +1637,12 @@ BEGIN_FTR_SECTION
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END_FTR_SECTION_IFSET(CPU_FTR_TM)
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END_FTR_SECTION_IFSET(CPU_FTR_TM)
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#endif
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#endif
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bl load_up_fpu
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bl load_up_fpu
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b fast_interrupt_return
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b fast_interrupt_return_srr
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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2: /* User process was in a transaction */
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2: /* User process was in a transaction */
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl fp_unavailable_tm
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bl fp_unavailable_tm
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b interrupt_return
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b interrupt_return_srr
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#endif
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#endif
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@ -1677,7 +1681,7 @@ EXC_COMMON_BEGIN(decrementer_common)
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GEN_COMMON decrementer
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GEN_COMMON decrementer
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl timer_interrupt
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bl timer_interrupt
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1761,7 +1765,7 @@ EXC_COMMON_BEGIN(doorbell_super_common)
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#else
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#else
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bl unknown_async_exception
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bl unknown_async_exception
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#endif
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#endif
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b interrupt_return
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b interrupt_return_srr
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EXC_REAL_NONE(0xb00, 0x100)
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EXC_REAL_NONE(0xb00, 0x100)
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@ -1925,7 +1929,7 @@ EXC_COMMON_BEGIN(single_step_common)
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GEN_COMMON single_step
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GEN_COMMON single_step
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl single_step_exception
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bl single_step_exception
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b interrupt_return
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b interrupt_return_srr
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/**
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/**
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@ -1963,7 +1967,7 @@ BEGIN_MMU_FTR_SECTION
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MMU_FTR_SECTION_ELSE
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MMU_FTR_SECTION_ELSE
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bl unknown_exception
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bl unknown_exception
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
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b interrupt_return
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b interrupt_return_hsrr
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/**
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/**
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@ -1988,7 +1992,7 @@ EXC_COMMON_BEGIN(h_instr_storage_common)
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GEN_COMMON h_instr_storage
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GEN_COMMON h_instr_storage
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addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl unknown_exception
|
bl unknown_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2012,7 +2016,7 @@ EXC_COMMON_BEGIN(emulation_assist_common)
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl emulation_assist_interrupt
|
bl emulation_assist_interrupt
|
||||||
REST_NVGPRS(r1) /* instruction emulation may change GPRs */
|
REST_NVGPRS(r1) /* instruction emulation may change GPRs */
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2089,7 +2093,7 @@ EXC_COMMON_BEGIN(hmi_exception_common)
|
||||||
GEN_COMMON hmi_exception
|
GEN_COMMON hmi_exception
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl handle_hmi_exception
|
bl handle_hmi_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2119,7 +2123,7 @@ EXC_COMMON_BEGIN(h_doorbell_common)
|
||||||
#else
|
#else
|
||||||
bl unknown_async_exception
|
bl unknown_async_exception
|
||||||
#endif
|
#endif
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2145,7 +2149,7 @@ EXC_COMMON_BEGIN(h_virt_irq_common)
|
||||||
GEN_COMMON h_virt_irq
|
GEN_COMMON h_virt_irq
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl do_IRQ
|
bl do_IRQ
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
EXC_REAL_NONE(0xec0, 0x20)
|
EXC_REAL_NONE(0xec0, 0x20)
|
||||||
|
@ -2188,7 +2192,7 @@ EXC_COMMON_BEGIN(performance_monitor_common)
|
||||||
GEN_COMMON performance_monitor
|
GEN_COMMON performance_monitor
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl performance_monitor_exception
|
bl performance_monitor_exception
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2225,19 +2229,19 @@ BEGIN_FTR_SECTION
|
||||||
END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
|
END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
|
||||||
#endif
|
#endif
|
||||||
bl load_up_altivec
|
bl load_up_altivec
|
||||||
b fast_interrupt_return
|
b fast_interrupt_return_srr
|
||||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||||
2: /* User process was in a transaction */
|
2: /* User process was in a transaction */
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl altivec_unavailable_tm
|
bl altivec_unavailable_tm
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
#endif
|
#endif
|
||||||
1:
|
1:
|
||||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||||
#endif
|
#endif
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl altivec_unavailable_exception
|
bl altivec_unavailable_exception
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2278,14 +2282,14 @@ BEGIN_FTR_SECTION
|
||||||
2: /* User process was in a transaction */
|
2: /* User process was in a transaction */
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl vsx_unavailable_tm
|
bl vsx_unavailable_tm
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
#endif
|
#endif
|
||||||
1:
|
1:
|
||||||
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
||||||
#endif
|
#endif
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl vsx_unavailable_exception
|
bl vsx_unavailable_exception
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2313,7 +2317,7 @@ EXC_COMMON_BEGIN(facility_unavailable_common)
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl facility_unavailable_exception
|
bl facility_unavailable_exception
|
||||||
REST_NVGPRS(r1) /* instruction emulation may change GPRs */
|
REST_NVGPRS(r1) /* instruction emulation may change GPRs */
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2341,7 +2345,7 @@ EXC_COMMON_BEGIN(h_facility_unavailable_common)
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl facility_unavailable_exception
|
bl facility_unavailable_exception
|
||||||
REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
|
REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
EXC_REAL_NONE(0xfa0, 0x20)
|
EXC_REAL_NONE(0xfa0, 0x20)
|
||||||
|
@ -2370,7 +2374,7 @@ EXC_COMMON_BEGIN(cbe_system_error_common)
|
||||||
GEN_COMMON cbe_system_error
|
GEN_COMMON cbe_system_error
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl cbe_system_error_exception
|
bl cbe_system_error_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
#else /* CONFIG_CBE_RAS */
|
#else /* CONFIG_CBE_RAS */
|
||||||
EXC_REAL_NONE(0x1200, 0x100)
|
EXC_REAL_NONE(0x1200, 0x100)
|
||||||
|
@ -2401,7 +2405,7 @@ EXC_COMMON_BEGIN(instruction_breakpoint_common)
|
||||||
GEN_COMMON instruction_breakpoint
|
GEN_COMMON instruction_breakpoint
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl instruction_breakpoint_exception
|
bl instruction_breakpoint_exception
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
EXC_REAL_NONE(0x1400, 0x100)
|
EXC_REAL_NONE(0x1400, 0x100)
|
||||||
|
@ -2521,7 +2525,7 @@ EXC_COMMON_BEGIN(denorm_exception_common)
|
||||||
GEN_COMMON denorm_exception
|
GEN_COMMON denorm_exception
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl unknown_exception
|
bl unknown_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_CBE_RAS
|
#ifdef CONFIG_CBE_RAS
|
||||||
|
@ -2538,7 +2542,7 @@ EXC_COMMON_BEGIN(cbe_maintenance_common)
|
||||||
GEN_COMMON cbe_maintenance
|
GEN_COMMON cbe_maintenance
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl cbe_maintenance_exception
|
bl cbe_maintenance_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
#else /* CONFIG_CBE_RAS */
|
#else /* CONFIG_CBE_RAS */
|
||||||
EXC_REAL_NONE(0x1600, 0x100)
|
EXC_REAL_NONE(0x1600, 0x100)
|
||||||
|
@ -2568,7 +2572,7 @@ EXC_COMMON_BEGIN(altivec_assist_common)
|
||||||
#else
|
#else
|
||||||
bl unknown_exception
|
bl unknown_exception
|
||||||
#endif
|
#endif
|
||||||
b interrupt_return
|
b interrupt_return_srr
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_CBE_RAS
|
#ifdef CONFIG_CBE_RAS
|
||||||
|
@ -2585,7 +2589,7 @@ EXC_COMMON_BEGIN(cbe_thermal_common)
|
||||||
GEN_COMMON cbe_thermal
|
GEN_COMMON cbe_thermal
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||||
bl cbe_thermal_exception
|
bl cbe_thermal_exception
|
||||||
b interrupt_return
|
b interrupt_return_hsrr
|
||||||
|
|
||||||
#else /* CONFIG_CBE_RAS */
|
#else /* CONFIG_CBE_RAS */
|
||||||
EXC_REAL_NONE(0x1800, 0x100)
|
EXC_REAL_NONE(0x1800, 0x100)
|
||||||
|
|
|
@ -131,7 +131,7 @@ _GLOBAL(load_up_vsx)
|
||||||
/* enable use of VSX after return */
|
/* enable use of VSX after return */
|
||||||
oris r12,r12,MSR_VSX@h
|
oris r12,r12,MSR_VSX@h
|
||||||
std r12,_MSR(r1)
|
std r12,_MSR(r1)
|
||||||
b fast_interrupt_return
|
b fast_interrupt_return_srr
|
||||||
|
|
||||||
#endif /* CONFIG_VSX */
|
#endif /* CONFIG_VSX */
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue