mirror of https://gitee.com/openkylin/linux.git
KVM: x86: fix deadline tsc interrupt injection
The check in kvm_set_lapic_tscdeadline_msr() was trying to prevent a situation where we lose a pending deadline timer in a MSR write. Losing it is fine, because it effectively occurs before the timer fired, so we should be able to cancel or postpone it. Another problem comes from interaction with QEMU, or other userspace that can set deadline MSR without a good reason, when timer is already pending: one guest's deadline request results in more than one interrupt because one is injected immediately on MSR write from userspace and one through hrtimer later. The solution is to remove the injection when replacing a pending timer and to improve the usual QEMU path, we inject without a hrtimer when the deadline has already passed. Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reported-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -1132,9 +1132,10 @@ static void start_apic_timer(struct kvm_lapic *apic)
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if (likely(tscdeadline > guest_tsc)) {
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ns = (tscdeadline - guest_tsc) * 1000000ULL;
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do_div(ns, this_tsc_khz);
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}
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hrtimer_start(&apic->lapic_timer.timer,
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ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
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hrtimer_start(&apic->lapic_timer.timer,
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ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
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} else
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apic_timer_expired(apic);
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local_irq_restore(flags);
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}
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@ -1391,9 +1392,6 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
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return;
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hrtimer_cancel(&apic->lapic_timer.timer);
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/* Inject here so clearing tscdeadline won't override new value */
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if (apic_has_pending_timer(vcpu))
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kvm_inject_apic_timer_irqs(vcpu);
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apic->lapic_timer.tscdeadline = data;
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start_apic_timer(apic);
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}
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