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qed: Add support for hardware offloaded FCoE. 

This adds the backbone required for the various HW initalizations
which are necessary for the FCoE driver (qedf) for QLogic FastLinQ
4xxxx line of adapters - FW notification, resource initializations, etc.

Signed-off-by: Arun Easi <arun.easi@cavium.com>
Signed-off-by: Yuval Mintz <yuval.mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arun Easi 2017-02-15 06:28:22 -08:00 committed by David S. Miller
parent f787d1debf
commit 1e128c8129
25 changed files with 3211 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/qlogic/Kconfig
View File

@ -114,4 +114,7 @@ config QED_RDMA
config QED_ISCSI
bool
config QED_FCOE
bool
endif # NET_VENDOR_QLOGIC

1
drivers/net/ethernet/qlogic/qed/Makefile
View File

@ -7,3 +7,4 @@ qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o
qed-$(CONFIG_QED_LL2) += qed_ll2.o
qed-$(CONFIG_QED_RDMA) += qed_roce.o
qed-$(CONFIG_QED_ISCSI) += qed_iscsi.o qed_ooo.o
qed-$(CONFIG_QED_FCOE) += qed_fcoe.o

11
drivers/net/ethernet/qlogic/qed/qed.h
View File

@ -60,6 +60,7 @@ extern const struct qed_common_ops qed_common_ops_pass;
#define QED_WFQ_UNIT 100
#define ISCSI_BDQ_ID(_port_id) (_port_id)
#define FCOE_BDQ_ID(_port_id) ((_port_id) + 2)
#define QED_WID_SIZE (1024)
#define QED_PF_DEMS_SIZE (4)
@ -167,6 +168,7 @@ struct qed_tunn_update_params {
*/
enum qed_pci_personality {
QED_PCI_ETH,
QED_PCI_FCOE,
QED_PCI_ISCSI,
QED_PCI_ETH_ROCE,
QED_PCI_DEFAULT /* default in shmem */
@ -204,6 +206,7 @@ enum QED_FEATURE {
QED_VF,
QED_RDMA_CNQ,
QED_VF_L2_QUE,
QED_FCOE_CQ,
QED_MAX_FEATURES,
};
@ -221,6 +224,7 @@ enum QED_PORT_MODE {
enum qed_dev_cap {
QED_DEV_CAP_ETH,
QED_DEV_CAP_FCOE,
QED_DEV_CAP_ISCSI,
QED_DEV_CAP_ROCE,
};
@ -255,6 +259,10 @@ struct qed_hw_info {
u32 part_num[4];
unsigned char hw_mac_addr[ETH_ALEN];
u64 node_wwn;
u64 port_wwn;
u16 num_fcoe_conns;
struct qed_igu_info *p_igu_info;
@ -410,6 +418,7 @@ struct qed_hwfn {
struct qed_ooo_info *p_ooo_info;
struct qed_rdma_info *p_rdma_info;
struct qed_iscsi_info *p_iscsi_info;
struct qed_fcoe_info *p_fcoe_info;
struct qed_pf_params pf_params;
bool b_rdma_enabled_in_prs;
@ -620,11 +629,13 @@ struct qed_dev {
u8 protocol;
#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
/* Callbacks to protocol driver */
union {
struct qed_common_cb_ops *common;
struct qed_eth_cb_ops *eth;
struct qed_fcoe_cb_ops *fcoe;
struct qed_iscsi_cb_ops *iscsi;
} protocol_ops;
void *ops_cookie;

98
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View File

@ -90,12 +90,14 @@ union conn_context {
struct core_conn_context core_ctx;
struct eth_conn_context eth_ctx;
struct iscsi_conn_context iscsi_ctx;
struct fcoe_conn_context fcoe_ctx;
struct roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI */
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
struct iscsi_task_context iscsi_ctx;
struct fcoe_task_context fcoe_ctx;
};
/* TYPE-1 task context - ROCE */
@ -240,15 +242,22 @@ struct qed_cxt_mngr {
static bool src_proto(enum protocol_type type)
{
return type == PROTOCOLID_ISCSI ||
type == PROTOCOLID_FCOE ||
type == PROTOCOLID_ROCE;
}
static bool tm_cid_proto(enum protocol_type type)
{
return type == PROTOCOLID_ISCSI ||
type == PROTOCOLID_FCOE ||
type == PROTOCOLID_ROCE;
}
static bool tm_tid_proto(enum protocol_type type)
{
return type == PROTOCOLID_FCOE;
}
/* counts the iids for the CDU/CDUC ILT client configuration */
struct qed_cdu_iids {
u32 pf_cids;
@ -307,6 +316,22 @@ static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
iids->pf_cids += p_cfg->cid_count;
iids->per_vf_cids += p_cfg->cids_per_vf;
}
if (tm_tid_proto(i)) {
struct qed_tid_seg *segs = p_cfg->tid_seg;
/* for each segment there is at most one
* protocol for which count is not 0.
*/
for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
iids->pf_tids[j] += segs[j].count;
/* The last array elelment is for the VFs. As for PF
* segments there can be only one protocol for
* which this value is not 0.
*/
iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
}
}
iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
@ -1694,9 +1719,42 @@ static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
/* @@@TBD how to enable the scan for the VFs */
}
static void qed_prs_init_common(struct qed_hwfn *p_hwfn)
{
if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) &&
p_hwfn->pf_params.fcoe_pf_params.is_target)
STORE_RT_REG(p_hwfn,
PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
}
static void qed_prs_init_pf(struct qed_hwfn *p_hwfn)
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct qed_conn_type_cfg *p_fcoe;
struct qed_tid_seg *p_tid;
p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
/* If FCoE is active set the MAX OX_ID (tid) in the Parser */
if (!p_fcoe->cid_count)
return;
p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG];
if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
STORE_RT_REG_AGG(p_hwfn,
PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
p_tid->count);
} else {
STORE_RT_REG_AGG(p_hwfn,
PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
p_tid->count);
}
}
void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
{
qed_cdu_init_common(p_hwfn);
qed_prs_init_common(p_hwfn);
}
void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
@ -1708,6 +1766,7 @@ void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
qed_ilt_init_pf(p_hwfn);
qed_src_init_pf(p_hwfn);
qed_tm_init_pf(p_hwfn);
qed_prs_init_pf(p_hwfn);
}
int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
@ -1885,6 +1944,27 @@ int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
p_params->num_cons, 1);
break;
}
case QED_PCI_FCOE:
{
struct qed_fcoe_pf_params *p_params;
p_params = &p_hwfn->pf_params.fcoe_pf_params;
if (p_params->num_cons && p_params->num_tasks) {
qed_cxt_set_proto_cid_count(p_hwfn,
PROTOCOLID_FCOE,
p_params->num_cons,
0);
qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
QED_CXT_FCOE_TID_SEG, 0,
p_params->num_tasks, true);
} else {
DP_INFO(p_hwfn->cdev,
"Fcoe personality used without setting params!\n");
}
break;
}
case QED_PCI_ISCSI:
{
struct qed_iscsi_pf_params *p_params;
@ -1927,6 +2007,10 @@ int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
/* Verify the personality */
switch (p_hwfn->hw_info.personality) {
case QED_PCI_FCOE:
proto = PROTOCOLID_FCOE;
seg = QED_CXT_FCOE_TID_SEG;
break;
case QED_PCI_ISCSI:
proto = PROTOCOLID_ISCSI;
seg = QED_CXT_ISCSI_TID_SEG;
@ -2215,15 +2299,19 @@ int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
{
struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct qed_ilt_client_cfg *p_cli;
struct qed_ilt_cli_blk *p_seg;
struct qed_tid_seg *p_seg_info;
u32 proto, seg;
u32 total_lines;
u32 tid_size, ilt_idx;
struct qed_ilt_cli_blk *p_seg;
u32 num_tids_per_block;
u32 tid_size, ilt_idx;
u32 total_lines;
u32 proto, seg;
/* Verify the personality */
switch (p_hwfn->hw_info.personality) {
case QED_PCI_FCOE:
proto = PROTOCOLID_FCOE;
seg = QED_CXT_FCOE_TID_SEG;
break;
case QED_PCI_ISCSI:
proto = PROTOCOLID_ISCSI;
seg = QED_CXT_ISCSI_TID_SEG;

3
drivers/net/ethernet/qlogic/qed/qed_cxt.h
View File

@ -91,6 +91,7 @@ int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
#define QED_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI
#define QED_CXT_ROCE_TID_SEG PROTOCOLID_ROCE
#define QED_CXT_FCOE_TID_SEG PROTOCOLID_FCOE
enum qed_cxt_elem_type {
QED_ELEM_CXT,
QED_ELEM_SRQ,
@ -204,4 +205,6 @@ int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto);
#define QED_CTX_WORKING_MEM 0
#define QED_CTX_FL_MEM 1
int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
u32 tid, u8 ctx_type, void **task_ctx);
#endif

13
drivers/net/ethernet/qlogic/qed/qed_dcbx.c
View File

@ -432,7 +432,6 @@ qed_dcbx_copy_mib(struct qed_hwfn *p_hwfn,
return rc;
}
#ifdef CONFIG_DCB
static void
qed_dcbx_get_priority_info(struct qed_hwfn *p_hwfn,
struct qed_dcbx_app_prio *p_prio,
@ -749,7 +748,6 @@ qed_dcbx_get_params(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
return 0;
}
#endif
static int
qed_dcbx_read_local_lldp_mib(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
@ -864,6 +862,15 @@ static int qed_dcbx_read_mib(struct qed_hwfn *p_hwfn,
return rc;
}
void qed_dcbx_aen(struct qed_hwfn *hwfn, u32 mib_type)
{
struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
void *cookie = hwfn->cdev->ops_cookie;
if (cookie && op->dcbx_aen)
op->dcbx_aen(cookie, &hwfn->p_dcbx_info->get, mib_type);
}
/* Read updated MIB.
* Reconfigure QM and invoke PF update ramrod command if operational MIB
* change is detected.
@ -890,6 +897,8 @@ qed_dcbx_mib_update_event(struct qed_hwfn *p_hwfn,
qed_sp_pf_update(p_hwfn);
}
}
qed_dcbx_get_params(p_hwfn, p_ptt, &p_hwfn->p_dcbx_info->get, type);
qed_dcbx_aen(p_hwfn, type);
return rc;
}

5
drivers/net/ethernet/qlogic/qed/qed_dcbx.h
View File

@ -57,7 +57,6 @@ struct qed_dcbx_app_data {
u8 tc; /* Traffic Class */
};
#ifdef CONFIG_DCB
#define QED_DCBX_VERSION_DISABLED 0
#define QED_DCBX_VERSION_IEEE 1
#define QED_DCBX_VERSION_CEE 2
@ -73,7 +72,6 @@ struct qed_dcbx_set {
struct qed_dcbx_admin_params config;
u32 ver_num;
};
#endif
struct qed_dcbx_results {
bool dcbx_enabled;
@ -97,9 +95,8 @@ struct qed_dcbx_info {
struct qed_dcbx_results results;
struct dcbx_mib operational;
struct dcbx_mib remote;
#ifdef CONFIG_DCB
struct qed_dcbx_set set;
#endif
struct qed_dcbx_get get;
u8 dcbx_cap;
};

205
drivers/net/ethernet/qlogic/qed/qed_dev.c
View File

@ -49,6 +49,7 @@
#include "qed_cxt.h"
#include "qed_dcbx.h"
#include "qed_dev_api.h"
#include "qed_fcoe.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
@ -172,6 +173,9 @@ void qed_resc_free(struct qed_dev *cdev)
#ifdef CONFIG_QED_LL2
qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
#endif
if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
@ -433,6 +437,7 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
int qed_resc_alloc(struct qed_dev *cdev)
{
struct qed_iscsi_info *p_iscsi_info;
struct qed_fcoe_info *p_fcoe_info;
struct qed_ooo_info *p_ooo_info;
#ifdef CONFIG_QED_LL2
struct qed_ll2_info *p_ll2_info;
@ -539,6 +544,14 @@ int qed_resc_alloc(struct qed_dev *cdev)
p_hwfn->p_ll2_info = p_ll2_info;
}
#endif
if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
p_fcoe_info = qed_fcoe_alloc(p_hwfn);
if (!p_fcoe_info)
goto alloc_no_mem;
p_hwfn->p_fcoe_info = p_fcoe_info;
}
if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
p_iscsi_info = qed_iscsi_alloc(p_hwfn);
if (!p_iscsi_info)
@ -602,6 +615,9 @@ void qed_resc_setup(struct qed_dev *cdev)
if (p_hwfn->using_ll2)
qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
#endif
if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
@ -994,7 +1010,8 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
/* Protocl Configuration */
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
(p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
/* Cleanup chip from previous driver if such remains exist */
@ -1026,8 +1043,16 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
/* send function start command */
rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
allow_npar_tx_switch);
if (rc)
if (rc) {
DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
return rc;
}
if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
qed_wr(p_hwfn, p_ptt,
PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
0x100);
}
}
return rc;
}
@ -1787,8 +1812,8 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
struct qed_mcp_link_params *link;
/* Read global nvm_cfg address */
@ -1934,6 +1959,9 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
__set_bit(QED_DEV_CAP_ETH,
&p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
__set_bit(QED_DEV_CAP_FCOE,
&p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
__set_bit(QED_DEV_CAP_ISCSI,
&p_hwfn->hw_info.device_capabilities);
@ -2671,6 +2699,177 @@ void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
}
int
qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port, enum qed_llh_port_filter_type_t type)
{
u32 high = 0, low = 0, en;
int i;
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
return 0;
switch (type) {
case QED_LLH_FILTER_ETHERTYPE:
high = source_port_or_eth_type;
break;
case QED_LLH_FILTER_TCP_SRC_PORT:
case QED_LLH_FILTER_UDP_SRC_PORT:
low = source_port_or_eth_type << 16;
break;
case QED_LLH_FILTER_TCP_DEST_PORT:
case QED_LLH_FILTER_UDP_DEST_PORT:
low = dest_port;
break;
case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
low = (source_port_or_eth_type << 16) | dest_port;
break;
default:
DP_NOTICE(p_hwfn,
"Non valid LLH protocol filter type %d\n", type);
return -EINVAL;
}
/* Find a free entry and utilize it */
for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
en = qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
if (en)
continue;
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
2 * i * sizeof(u32), low);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32), high);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
i * sizeof(u32), 1 << type);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
break;
}
if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
DP_NOTICE(p_hwfn,
"Failed to find an empty LLH filter to utilize\n");
return -EINVAL;
}
switch (type) {
case QED_LLH_FILTER_ETHERTYPE:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"ETH type %x is added at %d\n",
source_port_or_eth_type, i);
break;
case QED_LLH_FILTER_TCP_SRC_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"TCP src port %x is added at %d\n",
source_port_or_eth_type, i);
break;
case QED_LLH_FILTER_UDP_SRC_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"UDP src port %x is added at %d\n",
source_port_or_eth_type, i);
break;
case QED_LLH_FILTER_TCP_DEST_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"TCP dst port %x is added at %d\n", dest_port, i);
break;
case QED_LLH_FILTER_UDP_DEST_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"UDP dst port %x is added at %d\n", dest_port, i);
break;
case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"TCP src/dst ports %x/%x are added at %d\n",
source_port_or_eth_type, dest_port, i);
break;
case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"UDP src/dst ports %x/%x are added at %d\n",
source_port_or_eth_type, dest_port, i);
break;
}
return 0;
}
void
qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum qed_llh_port_filter_type_t type)
{
u32 high = 0, low = 0;
int i;
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
return;
switch (type) {
case QED_LLH_FILTER_ETHERTYPE:
high = source_port_or_eth_type;
break;
case QED_LLH_FILTER_TCP_SRC_PORT:
case QED_LLH_FILTER_UDP_SRC_PORT:
low = source_port_or_eth_type << 16;
break;
case QED_LLH_FILTER_TCP_DEST_PORT:
case QED_LLH_FILTER_UDP_DEST_PORT:
low = dest_port;
break;
case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
low = (source_port_or_eth_type << 16) | dest_port;
break;
default:
DP_NOTICE(p_hwfn,
"Non valid LLH protocol filter type %d\n", type);
return;
}
for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
if (!qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
continue;
if (!qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
continue;
if (!(qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
i * sizeof(u32)) & BIT(type)))
continue;
if (qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
2 * i * sizeof(u32)) != low)
continue;
if (qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32)) != high)
continue;
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32), 0);
break;
}
if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
}
static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u32 hw_addr, void *p_eth_qzone,
size_t eth_qzone_size, u8 timeset)

42
drivers/net/ethernet/qlogic/qed/qed_dev_api.h
View File

@ -353,6 +353,48 @@ int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_filter);
enum qed_llh_port_filter_type_t {
QED_LLH_FILTER_ETHERTYPE,
QED_LLH_FILTER_TCP_SRC_PORT,
QED_LLH_FILTER_TCP_DEST_PORT,
QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT,
QED_LLH_FILTER_UDP_SRC_PORT,
QED_LLH_FILTER_UDP_DEST_PORT,
QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT
};
/**
* @brief qed_llh_add_protocol_filter - configures a protocol filter in llh
*
* @param p_hwfn
* @param p_ptt
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*/
int
qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum qed_llh_port_filter_type_t type);
/**
* @brief qed_llh_remove_protocol_filter - remove a protocol filter in llh
*
* @param p_hwfn
* @param p_ptt
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*/
void
qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum qed_llh_port_filter_type_t type);
/**
* *@brief Cleanup of previous driver remains prior to load
*

1014
drivers/net/ethernet/qlogic/qed/qed_fcoe.c Normal file
View File

File diff suppressed because it is too large Load Diff

87
drivers/net/ethernet/qlogic/qed/qed_fcoe.h Normal file
View File

@ -0,0 +1,87 @@
/* QLogic qed NIC Driver
* Copyright (c) 2015-2017 QLogic Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and /or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _QED_FCOE_H
#define _QED_FCOE_H
#include <linux/types.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/qed/qed_fcoe_if.h>
#include <linux/qed/qed_chain.h>
#include "qed.h"
#include "qed_hsi.h"
#include "qed_mcp.h"
#include "qed_sp.h"
struct qed_fcoe_info {
spinlock_t lock; /* Connection resources. */
struct list_head free_list;
};
#if IS_ENABLED(CONFIG_QED_FCOE)
struct qed_fcoe_info *qed_fcoe_alloc(struct qed_hwfn *p_hwfn);
void qed_fcoe_setup(struct qed_hwfn *p_hwfn, struct qed_fcoe_info *p_fcoe_info);
void qed_fcoe_free(struct qed_hwfn *p_hwfn, struct qed_fcoe_info *p_fcoe_info);
void qed_get_protocol_stats_fcoe(struct qed_dev *cdev,
struct qed_mcp_fcoe_stats *stats);
#else /* CONFIG_QED_FCOE */
static inline struct qed_fcoe_info *
qed_fcoe_alloc(struct qed_hwfn *p_hwfn)
{
return NULL;
}
static inline void qed_fcoe_setup(struct qed_hwfn *p_hwfn,
struct qed_fcoe_info *p_fcoe_info)
{
}
static inline void qed_fcoe_free(struct qed_hwfn *p_hwfn,
struct qed_fcoe_info *p_fcoe_info)
{
}
static inline void qed_get_protocol_stats_fcoe(struct qed_dev *cdev,
struct qed_mcp_fcoe_stats *stats)
{
}
#endif /* CONFIG_QED_FCOE */
#ifdef CONFIG_QED_LL2
extern const struct qed_common_ops qed_common_ops_pass;
extern const struct qed_ll2_ops qed_ll2_ops_pass;
#endif
#endif /* _QED_FCOE_H */

781
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

@ -43,10 +43,12 @@
#include <linux/qed/common_hsi.h>
#include <linux/qed/storage_common.h>
#include <linux/qed/tcp_common.h>
#include <linux/qed/fcoe_common.h>
#include <linux/qed/eth_common.h>
#include <linux/qed/iscsi_common.h>
#include <linux/qed/rdma_common.h>
#include <linux/qed/roce_common.h>
#include <linux/qed/qed_fcoe_if.h>
struct qed_hwfn;
struct qed_ptt;
@ -937,7 +939,7 @@ struct mstorm_vf_zone {
enum personality_type {
BAD_PERSONALITY_TYP,
PERSONALITY_ISCSI,
PERSONALITY_RESERVED2,
PERSONALITY_FCOE,
PERSONALITY_RDMA_AND_ETH,
PERSONALITY_RESERVED3,
PERSONALITY_CORE,
@ -3473,6 +3475,10 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
(IRO[43].base + ((pf_id) * IRO[43].m1))
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
(IRO[44].base + ((pf_id) * IRO[44].m1))
static const struct iro iro_arr[47] = {
{0x0, 0x0, 0x0, 0x0, 0x8},
@ -7407,6 +7413,769 @@ struct ystorm_roce_resp_conn_ag_ctx {
__le32 reg3;
};
struct ystorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 cos;
u8 conf_version;
u8 eth_hdr_size;
__le16 stat_ram_addr;
__le16 mtu;
__le16 max_fc_payload_len;
__le16 tx_max_fc_pay_len;
u8 fcp_cmd_size;
u8 fcp_rsp_size;
__le16 mss;
struct regpair reserved;
u8 protection_info_flags;
#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
u8 dst_protection_per_mss;
u8 src_protection_per_mss;
u8 ptu_log_page_size;
u8 flags;
#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
u8 fcp_xfer_size;
u8 reserved3[2];
};
struct fcoe_vlan_fields {
__le16 fields;
#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
#define FCOE_VLAN_FIELDS_VID_SHIFT 0
#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
};
union fcoe_vlan_field_union {
struct fcoe_vlan_fields fields;
__le16 val;
};
union fcoe_vlan_vif_field_union {
union fcoe_vlan_field_union vlan;
__le16 vif;
};
struct pstorm_fcoe_eth_context_section {
u8 remote_addr_3;
u8 remote_addr_2;
u8 remote_addr_1;
u8 remote_addr_0;
u8 local_addr_1;
u8 local_addr_0;
u8 remote_addr_5;
u8 remote_addr_4;
u8 local_addr_5;
u8 local_addr_4;
u8 local_addr_3;
u8 local_addr_2;
union fcoe_vlan_vif_field_union vif_outer_vlan;
__le16 vif_outer_eth_type;
union fcoe_vlan_vif_field_union inner_vlan;
__le16 inner_eth_type;
};
struct pstorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 cos;
u8 conf_version;
u8 rsrv;
__le16 stat_ram_addr;
__le16 mss;
struct regpair abts_cleanup_addr;
struct pstorm_fcoe_eth_context_section eth;
u8 sid_2;
u8 sid_1;
u8 sid_0;
u8 flags;
#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
u8 did_2;
u8 did_1;
u8 did_0;
u8 src_mac_index;
__le16 rec_rr_tov_val;
u8 q_relative_offset;
u8 reserved1;
};
struct xstorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 src_mac_index;
u8 conf_version;
u8 cached_wqes_avail;
__le16 stat_ram_addr;
u8 flags;
#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
u8 cached_wqes_offset;
u8 reserved2;
u8 eth_hdr_size;
u8 seq_id;
u8 max_conc_seqs;
__le16 num_pages_in_pbl;
__le16 reserved;
struct regpair sq_pbl_addr;
struct regpair sq_curr_page_addr;
struct regpair sq_next_page_addr;
struct regpair xferq_pbl_addr;
struct regpair xferq_curr_page_addr;
struct regpair xferq_next_page_addr;
struct regpair respq_pbl_addr;
struct regpair respq_curr_page_addr;
struct regpair respq_next_page_addr;
__le16 mtu;
__le16 tx_max_fc_pay_len;
__le16 max_fc_payload_len;
__le16 min_frame_size;
__le16 sq_pbl_next_index;
__le16 respq_pbl_next_index;
u8 fcp_cmd_byte_credit;
u8 fcp_rsp_byte_credit;
__le16 protection_info;
#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
__le16 xferq_pbl_next_index;
__le16 page_size;
u8 mid_seq;
u8 fcp_xfer_byte_credit;
u8 reserved1[2];
struct fcoe_wqe cached_wqes[16];
};
struct xstorm_fcoe_conn_ag_ctx {
u8 reserved0;
u8 fcoe_state;
u8 flags0;
#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
u8 flags2;
#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
u8 flags7;
#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
u8 flags12;
#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
__le16 word2;
__le16 sq_cons;
__le16 sq_prod;
__le16 xferq_prod;
__le16 xferq_cons;
u8 byte3;
u8 byte4;
u8 byte5;
u8 byte6;
__le32 remain_io;
__le32 reg1;
__le32 reg2;
__le32 reg3;
__le32 reg4;
__le32 reg5;
__le32 reg6;
__le16 respq_prod;
__le16 respq_cons;
__le16 word9;
__le16 word10;
__le32 reg7;
__le32 reg8;
};
struct ustorm_fcoe_conn_st_ctx {
struct regpair respq_pbl_addr;
__le16 num_pages_in_pbl;
u8 ptu_log_page_size;
u8 log_page_size;
__le16 respq_prod;
u8 reserved[2];
};
struct tstorm_fcoe_conn_ag_ctx {
u8 reserved0;
u8 fcoe_state;
u8 flags0;
#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
u8 flags1;
#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
};
struct ustorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
__le32 reg2;
__le32 reg3;
__le16 word2;
__le16 word3;
};
struct tstorm_fcoe_conn_st_ctx {
__le16 stat_ram_addr;
__le16 rx_max_fc_payload_len;
__le16 e_d_tov_val;
u8 flags;
#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
u8 timers_cleanup_invocation_cnt;
__le32 reserved1[2];
__le32 dst_mac_address_bytes0to3;
__le16 dst_mac_address_bytes4to5;
__le16 ramrod_echo;
u8 flags1;
#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
u8 q_relative_offset;
u8 bdq_resource_id;
u8 reserved0[5];
};
struct mstorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
__le16 xfer_prod;
__le16 reserved1;
u8 protection_info;
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
u8 q_relative_offset;
u8 reserved2[2];
};
struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
__le16 conn_id;
__le16 stat_ram_addr;
__le16 num_pages_in_pbl;
u8 ptu_log_page_size;
u8 log_page_size;
__le16 unsolicited_cq_count;
__le16 cmdq_count;
u8 bdq_resource_id;
u8 reserved0[3];
struct regpair xferq_pbl_addr;
struct regpair reserved1;
struct regpair reserved2[3];
};
struct mstorm_fcoe_conn_st_ctx {
struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
};
struct fcoe_conn_context {
struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
struct regpair xstorm_ag_padding[6];
struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
struct regpair tstorm_ag_padding[2];
struct timers_context timer_context;
struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
};
struct fcoe_conn_offload_ramrod_params {
struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
};
struct fcoe_conn_terminate_ramrod_params {
struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
};
enum fcoe_event_type {
FCOE_EVENT_INIT_FUNC,
FCOE_EVENT_DESTROY_FUNC,
FCOE_EVENT_STAT_FUNC,
FCOE_EVENT_OFFLOAD_CONN,
FCOE_EVENT_TERMINATE_CONN,
FCOE_EVENT_ERROR,
MAX_FCOE_EVENT_TYPE
};
struct fcoe_init_ramrod_params {
struct fcoe_init_func_ramrod_data init_ramrod_data;
};
enum fcoe_ramrod_cmd_id {
FCOE_RAMROD_CMD_ID_INIT_FUNC,
FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
FCOE_RAMROD_CMD_ID_STAT_FUNC,
FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
MAX_FCOE_RAMROD_CMD_ID
};
struct fcoe_stat_ramrod_params {
struct fcoe_stat_ramrod_data stat_ramrod_data;
};
struct ystorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
__le32 reg0;
__le32 reg1;
__le16 word1;
__le16 word2;
__le16 word3;
__le16 word4;
__le32 reg2;
__le32 reg3;
};
struct ystorm_iscsi_conn_st_ctx {
__le32 reserved[4];
};
@ -8435,6 +9204,7 @@ struct public_func {
#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
@ -8529,6 +9299,13 @@ struct lan_stats_stc {
u32 rserved;
};
struct fcoe_stats_stc {
u64 rx_pkts;
u64 tx_pkts;
u32 fcs_err;
u32 login_failure;
};
struct ocbb_data_stc {
u32 ocbb_host_addr;
u32 ocsd_host_addr;
@ -8602,6 +9379,7 @@ union drv_union_data {
struct drv_version_stc drv_version;
struct lan_stats_stc lan_stats;
struct fcoe_stats_stc fcoe_stats;
struct ocbb_data_stc ocbb_info;
struct temperature_status_stc temp_info;
struct resource_info resource;
@ -8905,6 +9683,7 @@ struct nvm_cfg1_glob {
u32 misc_sig;
u32 device_capabilities;
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
u32 power_dissipated;

3
drivers/net/ethernet/qlogic/qed/qed_hw.c
View File

@ -841,6 +841,9 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
if (pq_id > p_hwfn->qm_info.num_pf_rls)
pq_id = p_hwfn->qm_info.offload_pq;
break;
case PROTOCOLID_FCOE:
pq_id = p_hwfn->qm_info.offload_pq;
break;
default:
pq_id = 0;
}

25
drivers/net/ethernet/qlogic/qed/qed_ll2.c
View File

@ -1130,6 +1130,9 @@ static int qed_sp_ll2_tx_queue_start(struct qed_hwfn *p_hwfn,
p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
switch (conn_type) {
case QED_LL2_TYPE_FCOE:
p_ramrod->conn_type = PROTOCOLID_FCOE;
break;
case QED_LL2_TYPE_ISCSI:
case QED_LL2_TYPE_ISCSI_OOO:
p_ramrod->conn_type = PROTOCOLID_ISCSI;
@ -1458,6 +1461,15 @@ int qed_ll2_establish_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
qed_ll2_establish_connection_ooo(p_hwfn, p_ll2_conn);
if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_FCOE) {
qed_llh_add_protocol_filter(p_hwfn, p_hwfn->p_main_ptt,
0x8906, 0,
QED_LLH_FILTER_ETHERTYPE);
qed_llh_add_protocol_filter(p_hwfn, p_hwfn->p_main_ptt,
0x8914, 0,
QED_LLH_FILTER_ETHERTYPE);
}
return rc;
}
@ -1831,6 +1843,15 @@ int qed_ll2_terminate_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_ISCSI_OOO)
qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
if (p_ll2_conn->conn.conn_type == QED_LL2_TYPE_FCOE) {
qed_llh_remove_protocol_filter(p_hwfn, p_hwfn->p_main_ptt,
0x8906, 0,
QED_LLH_FILTER_ETHERTYPE);
qed_llh_remove_protocol_filter(p_hwfn, p_hwfn->p_main_ptt,
0x8914, 0,
QED_LLH_FILTER_ETHERTYPE);
}
return rc;
}
@ -2039,6 +2060,10 @@ static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
}
switch (QED_LEADING_HWFN(cdev)->hw_info.personality) {
case QED_PCI_FCOE:
conn_type = QED_LL2_TYPE_FCOE;
gsi_enable = 0;
break;
case QED_PCI_ISCSI:
conn_type = QED_LL2_TYPE_ISCSI;
gsi_enable = 0;

2
drivers/net/ethernet/qlogic/qed/qed_ll2.h
View File

@ -54,7 +54,7 @@ enum qed_ll2_roce_flavor_type {
};
enum qed_ll2_conn_type {
QED_LL2_TYPE_RESERVED,
QED_LL2_TYPE_FCOE,
QED_LL2_TYPE_ISCSI,
QED_LL2_TYPE_TEST,
QED_LL2_TYPE_ISCSI_OOO,

7
drivers/net/ethernet/qlogic/qed/qed_main.c
View File

@ -53,9 +53,11 @@
#include "qed_sp.h"
#include "qed_dev_api.h"
#include "qed_ll2.h"
#include "qed_fcoe.h"
#include "qed_mcp.h"
#include "qed_hw.h"
#include "qed_selftest.h"
#include "qed_debug.h"
#define QED_ROCE_QPS (8192)
#define QED_ROCE_DPIS (8)
@ -1603,6 +1605,8 @@ const struct qed_common_ops qed_common_ops_pass = {
.sb_release = &qed_sb_release,
.simd_handler_config = &qed_simd_handler_config,
.simd_handler_clean = &qed_simd_handler_clean,
.dbg_grc = &qed_dbg_grc,
.dbg_grc_size = &qed_dbg_grc_size,
.can_link_change = &qed_can_link_change,
.set_link = &qed_set_link,
.get_link = &qed_get_current_link,
@ -1636,6 +1640,9 @@ void qed_get_protocol_stats(struct qed_dev *cdev,
stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts;
stats->lan_stats.fcs_err = -1;
break;
case QED_MCP_FCOE_STATS:
qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
break;
default:
DP_ERR(cdev, "Invalid protocol type = %d\n", type);
return;

3
drivers/net/ethernet/qlogic/qed/qed_mcp.c
View File

@ -1130,6 +1130,9 @@ qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
case FUNC_MF_CFG_PROTOCOL_ISCSI:
*p_proto = QED_PCI_ISCSI;
break;
case FUNC_MF_CFG_PROTOCOL_FCOE:
*p_proto = QED_PCI_FCOE;
break;
case FUNC_MF_CFG_PROTOCOL_ROCE:
DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
/* Fallthrough */

1
drivers/net/ethernet/qlogic/qed/qed_mcp.h
View File

@ -37,6 +37,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/qed/qed_fcoe_if.h>
#include "qed_hsi.h"
struct qed_mcp_link_speed_params {

8
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View File

@ -110,6 +110,8 @@
0x1e80000UL
#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
0x5011f4UL
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \
0x1f0164UL
#define PRS_REG_SEARCH_TCP \
0x1f0400UL
#define PRS_REG_SEARCH_UDP \
@ -120,6 +122,12 @@
0x1f040cUL
#define PRS_REG_SEARCH_OPENFLOW \
0x1f0434UL
#define PRS_REG_SEARCH_TAG1 \
0x1f0444UL
#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \
0x1f0a0cUL
#define PRS_REG_SEARCH_TCP_FIRST_FRAG \
0x1f0410UL
#define TM_REG_PF_ENABLE_CONN \
0x2c043cUL
#define TM_REG_PF_ENABLE_TASK \

4
drivers/net/ethernet/qlogic/qed/qed_sp.h
View File

@ -109,6 +109,10 @@ union ramrod_data {
struct rdma_srq_destroy_ramrod_data rdma_destroy_srq;
struct rdma_srq_modify_ramrod_data rdma_modify_srq;
struct roce_init_func_ramrod_data roce_init_func;
struct fcoe_init_ramrod_params fcoe_init;
struct fcoe_conn_offload_ramrod_params fcoe_conn_ofld;
struct fcoe_conn_terminate_ramrod_params fcoe_conn_terminate;
struct fcoe_stat_ramrod_params fcoe_stat;
struct iscsi_slow_path_hdr iscsi_empty;
struct iscsi_init_ramrod_params iscsi_init;

3
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
View File

@ -386,6 +386,9 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
case QED_PCI_ETH:
p_ramrod->personality = PERSONALITY_ETH;
break;
case QED_PCI_FCOE:
p_ramrod->personality = PERSONALITY_FCOE;
break;
case QED_PCI_ISCSI:
p_ramrod->personality = PERSONALITY_ISCSI;
break;

10
include/linux/qed/common_hsi.h
View File

@ -62,6 +62,7 @@
#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
#define ISCSI_CDU_TASK_SEG_TYPE 0
#define FCOE_CDU_TASK_SEG_TYPE 0
#define RDMA_CDU_TASK_SEG_TYPE 1
#define FW_ASSERT_GENERAL_ATTN_IDX 32
@ -205,6 +206,9 @@
#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
@ -261,6 +265,7 @@
#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
@ -291,6 +296,9 @@
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
/* TCM agg counter flag selection (FW) */
#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
@ -728,7 +736,7 @@ enum mf_mode {
/* Per-protocol connection types */
enum protocol_type {
PROTOCOLID_ISCSI,
PROTOCOLID_RESERVED2,
PROTOCOLID_FCOE,
PROTOCOLID_ROCE,
PROTOCOLID_CORE,
PROTOCOLID_ETH,

715
include/linux/qed/fcoe_common.h Normal file
View File

@ -0,0 +1,715 @@
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef __FCOE_COMMON__
#define __FCOE_COMMON__
/*********************/
/* FCOE FW CONSTANTS */
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
#define FCOE_MAX_SIZE_FCP_DATA_SUPER (8600)
struct fcoe_abts_pkt {
__le32 abts_rsp_fc_payload_lo;
__le16 abts_rsp_rx_id;
u8 abts_rsp_rctl;
u8 reserved2;
};
/* FCoE additional WQE (Sq/XferQ) information */
union fcoe_additional_info_union {
__le32 previous_tid;
__le32 parent_tid;
__le32 burst_length;
__le32 seq_rec_updated_offset;
};
struct fcoe_exp_ro {
__le32 data_offset;
__le32 reserved;
};
union fcoe_cleanup_addr_exp_ro_union {
struct regpair abts_rsp_fc_payload_hi;
struct fcoe_exp_ro exp_ro;
};
/* FCoE Ramrod Command IDs */
enum fcoe_completion_status {
FCOE_COMPLETION_STATUS_SUCCESS,
FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
MAX_FCOE_COMPLETION_STATUS
};
struct fc_addr_nw {
u8 addr_lo;
u8 addr_mid;
u8 addr_hi;
};
/* FCoE connection offload */
struct fcoe_conn_offload_ramrod_data {
struct regpair sq_pbl_addr;
struct regpair sq_curr_page_addr;
struct regpair sq_next_page_addr;
struct regpair xferq_pbl_addr;
struct regpair xferq_curr_page_addr;
struct regpair xferq_next_page_addr;
struct regpair respq_pbl_addr;
struct regpair respq_curr_page_addr;
struct regpair respq_next_page_addr;
__le16 dst_mac_addr_lo;
__le16 dst_mac_addr_mid;
__le16 dst_mac_addr_hi;
__le16 src_mac_addr_lo;
__le16 src_mac_addr_mid;
__le16 src_mac_addr_hi;
__le16 tx_max_fc_pay_len;
__le16 e_d_tov_timer_val;
__le16 rx_max_fc_pay_len;
__le16 vlan_tag;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
__le16 physical_q0;
__le16 rec_rr_tov_timer_val;
struct fc_addr_nw s_id;
u8 max_conc_seqs_c3;
struct fc_addr_nw d_id;
u8 flags;
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
__le16 conn_id;
u8 def_q_idx;
u8 reserved[5];
};
/* FCoE terminate connection request */
struct fcoe_conn_terminate_ramrod_data {
struct regpair terminate_params_addr;
};
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
__le16 task_reuse_cnt;
__le16 init_offset_in_first_sge;
};
struct fcoe_slow_sgl_ctx {
struct regpair base_sgl_addr;
__le16 curr_sge_off;
__le16 remainder_num_sges;
__le16 curr_sgl_index;
__le16 reserved;
};
struct fcoe_sge {
struct regpair sge_addr;
__le16 size;
__le16 reserved0;
u8 reserved1[3];
u8 is_valid_sge;
};
union fcoe_data_desc_ctx {
struct fcoe_fast_sgl_ctx fast;
struct fcoe_slow_sgl_ctx slow;
struct fcoe_sge single_sge;
};
union fcoe_dix_desc_ctx {
struct fcoe_slow_sgl_ctx dix_sgl;
struct fcoe_sge cached_dix_sge;
};
struct fcoe_fcp_cmd_payload {
__le32 opaque[8];
};
struct fcoe_fcp_rsp_payload {
__le32 opaque[6];
};
struct fcoe_fcp_xfer_payload {
__le32 opaque[3];
};
/* FCoE firmware function init */
struct fcoe_init_func_ramrod_data {
struct scsi_init_func_params func_params;
struct scsi_init_func_queues q_params;
__le16 mtu;
__le16 sq_num_pages_in_pbl;
__le32 reserved;
};
/* FCoE: Mode of the connection: Target or Initiator or both */
enum fcoe_mode_type {
FCOE_INITIATOR_MODE = 0x0,
FCOE_TARGET_MODE = 0x1,
FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
MAX_FCOE_MODE_TYPE
};
struct fcoe_mstorm_fcoe_task_st_ctx_fp {
__le16 flags;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_MASK 0x7FFF
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_SHIFT 15
__le16 difDataResidue;
__le16 parent_id;
__le16 single_sge_saved_offset;
__le32 data_2_trns_rem;
__le32 offset_in_io;
union fcoe_dix_desc_ctx dix_desc;
union fcoe_data_desc_ctx data_desc;
};
struct fcoe_mstorm_fcoe_task_st_ctx_non_fp {
__le16 flags;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_SHIFT 2
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_SHIFT 3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_MASK 0xF
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_SHIFT 4
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_SHIFT 8
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_SHIFT 10
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_SHIFT 11
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_SHIFT 12
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_SHIFT 13
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_SHIFT 14
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_SHIFT 15
u8 tx_rx_sgl_mode;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_MASK 0x7
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_MASK 0x7
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_SHIFT 3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_SHIFT 6
u8 rsrv2;
__le32 num_prm_zero_read;
struct regpair rsp_buf_addr;
};
struct fcoe_rx_stat {
struct regpair fcoe_rx_byte_cnt;
struct regpair fcoe_rx_data_pkt_cnt;
struct regpair fcoe_rx_xfer_pkt_cnt;
struct regpair fcoe_rx_other_pkt_cnt;
__le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
__le32 fcoe_silent_drop_pkt_rq_full_cnt;
__le32 fcoe_silent_drop_pkt_crc_error_cnt;
__le32 fcoe_silent_drop_pkt_task_invalid_cnt;
__le32 fcoe_silent_drop_total_pkt_cnt;
__le32 rsrv;
};
enum fcoe_sgl_mode {
FCOE_SLOW_SGL,
FCOE_SINGLE_FAST_SGE,
FCOE_2_FAST_SGE,
FCOE_3_FAST_SGE,
FCOE_4_FAST_SGE,
FCOE_MUL_FAST_SGES,
MAX_FCOE_SGL_MODE
};
struct fcoe_stat_ramrod_data {
struct regpair stat_params_addr;
};
struct protection_info_ctx {
__le16 flags;
#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
u8 dix_block_size;
u8 dst_size;
};
union protection_info_union_ctx {
struct protection_info_ctx info;
__le32 value;
};
struct fcp_rsp_payload_padded {
struct fcoe_fcp_rsp_payload rsp_payload;
__le32 reserved[2];
};
struct fcp_xfer_payload_padded {
struct fcoe_fcp_xfer_payload xfer_payload;
__le32 reserved[5];
};
struct fcoe_tx_data_params {
__le32 data_offset;
__le32 offset_in_io;
u8 flags;
#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
u8 dif_residual;
__le16 seq_cnt;
__le16 single_sge_saved_offset;
__le16 next_dif_offset;
__le16 seq_id;
__le16 reserved3;
};
struct fcoe_tx_mid_path_params {
__le32 parameter;
u8 r_ctl;
u8 type;
u8 cs_ctl;
u8 df_ctl;
__le16 rx_id;
__le16 ox_id;
};
struct fcoe_tx_params {
struct fcoe_tx_data_params data;
struct fcoe_tx_mid_path_params mid_path;
};
union fcoe_tx_info_union_ctx {
struct fcoe_fcp_cmd_payload fcp_cmd_payload;
struct fcp_rsp_payload_padded fcp_rsp_payload;
struct fcp_xfer_payload_padded fcp_xfer_payload;
struct fcoe_tx_params tx_params;
};
struct ystorm_fcoe_task_st_ctx {
u8 task_type;
u8 sgl_mode;
#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x7
#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x1F
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 3
u8 cached_dix_sge;
u8 expect_first_xfer;
__le32 num_pbf_zero_write;
union protection_info_union_ctx protection_info_union;
__le32 data_2_trns_rem;
union fcoe_tx_info_union_ctx tx_info_union;
union fcoe_dix_desc_ctx dix_desc;
union fcoe_data_desc_ctx data_desc;
__le16 ox_id;
__le16 rx_id;
__le32 task_rety_identifier;
__le32 reserved1[2];
};
struct ystorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
u8 byte4;
__le16 rx_id;
__le16 word2;
__le16 word3;
__le16 word4;
__le16 word5;
__le32 reg1;
__le32 reg2;
};
struct tstorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
u8 flags1;
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
u8 flags3;
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
u8 flags4;
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 cleanup_state;
__le16 last_sent_tid;
__le32 rec_rr_tov_exp_timeout;
u8 byte3;
u8 byte4;
__le16 word2;
__le16 word3;
__le16 word4;
__le32 data_offset_end_of_seq;
__le32 data_offset_next;
};
struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
__le16 flags;
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x7
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 3
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 4
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 5
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 6
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 7
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 8
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0x3F
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 10
__le16 seq_cnt;
u8 seq_id;
u8 ooo_rx_seq_id;
__le16 rx_id;
struct fcoe_abts_pkt abts_data;
__le32 e_d_tov_exp_timeout_val;
__le16 ooo_rx_seq_cnt;
__le16 reserved1;
};
struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
u8 task_type;
u8 dev_type;
u8 conf_supported;
u8 glbl_q_num;
__le32 cid;
__le32 fcp_cmd_trns_size;
__le32 rsrv;
};
struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
};
struct mstorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 icid;
u8 flags0;
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 cleanup_state;
__le32 received_bytes;
u8 byte3;
u8 glbl_q_num;
__le16 word1;
__le16 tid_to_xfer;
__le16 word3;
__le16 word4;
__le16 word5;
__le32 expected_bytes;
__le32 reg2;
};
struct mstorm_fcoe_task_st_ctx {
struct fcoe_mstorm_fcoe_task_st_ctx_non_fp non_fp;
struct fcoe_mstorm_fcoe_task_st_ctx_fp fp;
};
struct ustorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
u8 flags1;
#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 global_cq_num;
__le32 reg3;
__le32 reg4;
__le32 reg5;
};
struct fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct tdif_task_context tdif_context;
struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
struct tstorm_fcoe_task_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_st_ctx mstorm_st_context;
struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct rdif_task_context rdif_context;
};
struct fcoe_tx_stat {
struct regpair fcoe_tx_byte_cnt;
struct regpair fcoe_tx_data_pkt_cnt;
struct regpair fcoe_tx_xfer_pkt_cnt;
struct regpair fcoe_tx_other_pkt_cnt;
};
struct fcoe_wqe {
__le16 task_id;
__le16 flags;
#define FCOE_WQE_REQ_TYPE_MASK 0xF
#define FCOE_WQE_REQ_TYPE_SHIFT 0
#define FCOE_WQE_SGL_MODE_MASK 0x7
#define FCOE_WQE_SGL_MODE_SHIFT 4
#define FCOE_WQE_CONTINUATION_MASK 0x1
#define FCOE_WQE_CONTINUATION_SHIFT 7
#define FCOE_WQE_INVALIDATE_PTU_MASK 0x1
#define FCOE_WQE_INVALIDATE_PTU_SHIFT 8
#define FCOE_WQE_SUPER_IO_MASK 0x1
#define FCOE_WQE_SUPER_IO_SHIFT 9
#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 10
#define FCOE_WQE_RESERVED0_MASK 0x1F
#define FCOE_WQE_RESERVED0_SHIFT 11
union fcoe_additional_info_union additional_info_union;
};
struct xfrqe_prot_flags {
u8 flags;
#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
};
struct fcoe_db_data {
u8 params;
#define FCOE_DB_DATA_DEST_MASK 0x3
#define FCOE_DB_DATA_DEST_SHIFT 0
#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
#define FCOE_DB_DATA_RESERVED_MASK 0x1
#define FCOE_DB_DATA_RESERVED_SHIFT 5
#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
#endif /* __FCOE_COMMON__ */

145
include/linux/qed/qed_fcoe_if.h Normal file
View File

@ -0,0 +1,145 @@
#ifndef _QED_FCOE_IF_H
#define _QED_FCOE_IF_H
#include <linux/types.h>
#include <linux/qed/qed_if.h>
struct qed_fcoe_stats {
u64 fcoe_rx_byte_cnt;
u64 fcoe_rx_data_pkt_cnt;
u64 fcoe_rx_xfer_pkt_cnt;
u64 fcoe_rx_other_pkt_cnt;
u32 fcoe_silent_drop_pkt_cmdq_full_cnt;
u32 fcoe_silent_drop_pkt_rq_full_cnt;
u32 fcoe_silent_drop_pkt_crc_error_cnt;
u32 fcoe_silent_drop_pkt_task_invalid_cnt;
u32 fcoe_silent_drop_total_pkt_cnt;
u64 fcoe_tx_byte_cnt;
u64 fcoe_tx_data_pkt_cnt;
u64 fcoe_tx_xfer_pkt_cnt;
u64 fcoe_tx_other_pkt_cnt;
};
struct qed_dev_fcoe_info {
struct qed_dev_info common;
void __iomem *primary_dbq_rq_addr;
void __iomem *secondary_bdq_rq_addr;
};
struct qed_fcoe_params_offload {
dma_addr_t sq_pbl_addr;
dma_addr_t sq_curr_page_addr;
dma_addr_t sq_next_page_addr;
u8 src_mac[ETH_ALEN];
u8 dst_mac[ETH_ALEN];
u16 tx_max_fc_pay_len;
u16 e_d_tov_timer_val;
u16 rec_tov_timer_val;
u16 rx_max_fc_pay_len;
u16 vlan_tag;
struct fc_addr_nw s_id;
u8 max_conc_seqs_c3;
struct fc_addr_nw d_id;
u8 flags;
u8 def_q_idx;
};
#define MAX_TID_BLOCKS_FCOE (512)
struct qed_fcoe_tid {
u32 size; /* In bytes per task */
u32 num_tids_per_block;
u8 *blocks[MAX_TID_BLOCKS_FCOE];
};
struct qed_fcoe_cb_ops {
struct qed_common_cb_ops common;
u32 (*get_login_failures)(void *cookie);
};
void qed_fcoe_set_pf_params(struct qed_dev *cdev,
struct qed_fcoe_pf_params *params);
/**
* struct qed_fcoe_ops - qed FCoE operations.
* @common: common operations pointer
* @fill_dev_info: fills FCoE specific information
* @param cdev
* @param info
* @return 0 on sucesss, otherwise error value.
* @register_ops: register FCoE operations
* @param cdev
* @param ops - specified using qed_iscsi_cb_ops
* @param cookie - driver private
* @ll2: light L2 operations pointer
* @start: fcoe in FW
* @param cdev
* @param tasks - qed will fill information about tasks
* return 0 on success, otherwise error value.
* @stop: stops fcoe in FW
* @param cdev
* return 0 on success, otherwise error value.
* @acquire_conn: acquire a new fcoe connection
* @param cdev
* @param handle - qed will fill handle that should be
* used henceforth as identifier of the
* connection.
* @param p_doorbell - qed will fill the address of the
* doorbell.
* return 0 on sucesss, otherwise error value.
* @release_conn: release a previously acquired fcoe connection
* @param cdev
* @param handle - the connection handle.
* return 0 on success, otherwise error value.
* @offload_conn: configures an offloaded connection
* @param cdev
* @param handle - the connection handle.
* @param conn_info - the configuration to use for the
* offload.
* return 0 on success, otherwise error value.
* @destroy_conn: stops an offloaded connection
* @param cdev
* @param handle - the connection handle.
* @param terminate_params
* return 0 on success, otherwise error value.
* @get_stats: gets FCoE related statistics
* @param cdev
* @param stats - pointer to struck that would be filled
* we stats
* return 0 on success, error otherwise.
*/
struct qed_fcoe_ops {
const struct qed_common_ops *common;
int (*fill_dev_info)(struct qed_dev *cdev,
struct qed_dev_fcoe_info *info);
void (*register_ops)(struct qed_dev *cdev,
struct qed_fcoe_cb_ops *ops, void *cookie);
const struct qed_ll2_ops *ll2;
int (*start)(struct qed_dev *cdev, struct qed_fcoe_tid *tasks);
int (*stop)(struct qed_dev *cdev);
int (*acquire_conn)(struct qed_dev *cdev,
u32 *handle,
u32 *fw_cid, void __iomem **p_doorbell);
int (*release_conn)(struct qed_dev *cdev, u32 handle);
int (*offload_conn)(struct qed_dev *cdev,
u32 handle,
struct qed_fcoe_params_offload *conn_info);
int (*destroy_conn)(struct qed_dev *cdev,
u32 handle, dma_addr_t terminate_params);
int (*get_stats)(struct qed_dev *cdev, struct qed_fcoe_stats *stats);
};
const struct qed_fcoe_ops *qed_get_fcoe_ops(void);
void qed_put_fcoe_ops(void);
#endif

41
include/linux/qed/qed_if.h
View File

@ -59,7 +59,6 @@ enum dcbx_protocol_type {
#define QED_ROCE_PROTOCOL_INDEX (3)
#ifdef CONFIG_DCB
#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
#define QED_LLDP_PORT_ID_STAT_LEN 4
#define QED_DCBX_MAX_APP_PROTOCOL 32
@ -155,7 +154,6 @@ struct qed_dcbx_get {
struct qed_dcbx_remote_params remote;
struct qed_dcbx_admin_params local;
};
#endif
enum qed_led_mode {
QED_LED_MODE_OFF,
@ -182,6 +180,38 @@ struct qed_eth_pf_params {
u16 num_cons;
};
struct qed_fcoe_pf_params {
/* The following parameters are used during protocol-init */
u64 glbl_q_params_addr;
u64 bdq_pbl_base_addr[2];
/* The following parameters are used during HW-init
* and these parameters need to be passed as arguments
* to update_pf_params routine invoked before slowpath start
*/
u16 num_cons;
u16 num_tasks;
/* The following parameters are used during protocol-init */
u16 sq_num_pbl_pages;
u16 cq_num_entries;
u16 cmdq_num_entries;
u16 rq_buffer_log_size;
u16 mtu;
u16 dummy_icid;
u16 bdq_xoff_threshold[2];
u16 bdq_xon_threshold[2];
u16 rq_buffer_size;
u8 num_cqs; /* num of global CQs */
u8 log_page_size;
u8 gl_rq_pi;
u8 gl_cmd_pi;
u8 debug_mode;
u8 is_target;
u8 bdq_pbl_num_entries[2];
};
/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
struct qed_iscsi_pf_params {
u64 glbl_q_params_addr;
@ -245,6 +275,7 @@ struct qed_rdma_pf_params {
struct qed_pf_params {
struct qed_eth_pf_params eth_pf_params;
struct qed_fcoe_pf_params fcoe_pf_params;
struct qed_iscsi_pf_params iscsi_pf_params;
struct qed_rdma_pf_params rdma_pf_params;
};
@ -305,6 +336,7 @@ enum qed_sb_type {
enum qed_protocol {
QED_PROTOCOL_ETH,
QED_PROTOCOL_ISCSI,
QED_PROTOCOL_FCOE,
};
enum qed_link_mode_bits {
@ -391,6 +423,7 @@ struct qed_int_info {
struct qed_common_cb_ops {
void (*link_update)(void *dev,
struct qed_link_output *link);
void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
};
struct qed_selftest_ops {
@ -494,6 +527,10 @@ struct qed_common_ops {
void (*simd_handler_clean)(struct qed_dev *cdev,
int index);
int (*dbg_grc)(struct qed_dev *cdev,
void *buffer, u32 *num_dumped_bytes);
int (*dbg_grc_size)(struct qed_dev *cdev);
int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);