mirror of https://gitee.com/openkylin/linux.git
ARM: shmobile: r8a7779: Add clocks
Declare all core and MSTP clocks currently used by r8a7779-based boards. Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs. Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Simon Horman
parent
62872989bd
commit
1e8515384b
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@ -11,6 +11,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -265,4 +266,147 @@ hspi2: spi@fffc6000 {
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#size-cells = <0>;
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status = "disabled";
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@0xe6150000 {
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compatible = "renesas,r8a7779-cpg-clocks";
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reg = <0 0xffc80000 0 0x30>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "plla", "z", "zs", "s",
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"s1", "p", "b", "out";
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};
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/* Fixed factor clocks */
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i_clk: i_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "i";
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};
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s3_clk: s3_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "s3";
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};
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s4_clk: s4_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
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clock-output-names = "s4";
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};
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g_clk: g_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "g";
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};
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/* Gate clocks */
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mstp0_clks: mstp0_clks {
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compatible = "renesas,r8a7779-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xffc80030 0 4>;
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clocks = <&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7779_CLK_HSPI R8A7779_CLK_TMU2
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R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
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R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
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R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
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R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
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R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
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R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
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R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
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>;
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clock-output-names =
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"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
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"hscif0", "scif5", "scif4", "scif3", "scif2",
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"scif1", "scif0", "i2c3", "i2c2", "i2c1",
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"i2c0";
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};
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mstp1_clks: mstp1_clks {
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compatible = "renesas,r8a7779-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
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clocks = <&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_S>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7779_CLK_USB01 R8A7779_CLK_USB2
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R8A7779_CLK_DU R8A7779_CLK_VIN2
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R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
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R8A7779_CLK_ETHER R8A7779_CLK_SATA
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R8A7779_CLK_PCIE R8A7779_CLK_VIN3
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>;
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clock-output-names =
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"usb01", "usb2",
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"du", "vin2",
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"vin1", "vin0",
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"ether", "sata",
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"pcie", "vin3";
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};
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mstp3_clks: mstp3_clks {
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compatible = "renesas,r8a7779-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xffc8003c 0 4>;
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clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
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<&s4_clk>, <&s4_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
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R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
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R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
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>;
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clock-output-names =
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"sdhi3", "sdhi2", "sdhi1", "sdhi0",
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"mmc1", "mmc0";
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};
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};
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};
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