mirror of https://gitee.com/openkylin/linux.git
Merge branch 'spear/multiplatform' into spear/dma
The actual SPEAr conversion to the DMA binding depends on driver patches and the multiplatform work. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
1ef865bb45
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@ -933,16 +933,8 @@ config ARCH_NOMADIK
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|||
help
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Support for the Nomadik platform by ST-Ericsson
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config PLAT_SPEAR
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config PLAT_SPEAR_SINGLE
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bool "ST SPEAr"
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select ARCH_HAS_CPUFREQ
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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help
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||||
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
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@ -1104,7 +1096,7 @@ source "arch/arm/plat-samsung/Kconfig"
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source "arch/arm/mach-socfpga/Kconfig"
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source "arch/arm/plat-spear/Kconfig"
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source "arch/arm/mach-spear/Kconfig"
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source "arch/arm/mach-s3c24xx/Kconfig"
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|
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@ -191,9 +191,7 @@ machine-$(CONFIG_ARCH_VT8500) += vt8500
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machine-$(CONFIG_ARCH_W90X900) += w90x900
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machine-$(CONFIG_FOOTBRIDGE) += footbridge
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machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
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machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
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machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
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machine-$(CONFIG_MACH_SPEAR600) += spear6xx
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machine-$(CONFIG_PLAT_SPEAR) += spear
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machine-$(CONFIG_ARCH_VIRT) += virt
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machine-$(CONFIG_ARCH_ZYNQ) += zynq
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machine-$(CONFIG_ARCH_SUNXI) += sunxi
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@ -207,7 +205,6 @@ plat-$(CONFIG_PLAT_ORION) += orion
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plat-$(CONFIG_PLAT_PXA) += pxa
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plat-$(CONFIG_PLAT_S3C24XX) += samsung
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plat-$(CONFIG_PLAT_S5P) += samsung
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plat-$(CONFIG_PLAT_SPEAR) += spear
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plat-$(CONFIG_PLAT_VERSATILE) += versatile
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ifeq ($(CONFIG_ARCH_EBSA110),y)
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@ -10,6 +10,10 @@ CONFIG_ARCH_SUNXI=y
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# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
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CONFIG_ARCH_ZYNQ=y
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_PLAT_SPEAR=y
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CONFIG_ARCH_SPEAR13XX=y
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CONFIG_MACH_SPEAR1310=y
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CONFIG_MACH_SPEAR1340=y
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CONFIG_SMP=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_AEABI=y
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@ -23,6 +27,7 @@ CONFIG_BLK_DEV_SD=y
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CONFIG_ATA=y
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CONFIG_SATA_HIGHBANK=y
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CONFIG_SATA_MV=y
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CONFIG_SATA_AHCI_PLATFORM=y
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CONFIG_NETDEVICES=y
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CONFIG_NET_CALXEDA_XGMAC=y
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CONFIG_SMSC911X=y
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@ -31,6 +36,7 @@ CONFIG_SERIO_AMBAKMI=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_KEYBOARD_SPEAR=y
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
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CONFIG_SERIAL_OF_PLATFORM=y
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@ -40,6 +46,7 @@ CONFIG_I2C=y
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CONFIG_I2C_DESIGNWARE_PLATFORM=y
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CONFIG_SPI=y
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CONFIG_SPI_PL022=y
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CONFIG_GPIO_PL061=y
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CONFIG_FB=y
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CONFIG_FB_ARMCLCD=y
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CONFIG_FRAMEBUFFER_CONSOLE=y
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@ -50,6 +57,7 @@ CONFIG_MMC=y
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CONFIG_MMC_ARMMMCI=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MMC_SDHCI_SPEAR=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_HIGHBANK_MC=y
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@ -58,3 +66,4 @@ CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_PL031=y
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CONFIG_DMADEVICES=y
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CONFIG_PL330_DMA=y
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CONFIG_DW_DMAC=y
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@ -6,7 +6,9 @@ CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_ARCH_MULTI_V7 is not set
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CONFIG_PLAT_SPEAR=y
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CONFIG_ARCH_SPEAR3XX=y
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CONFIG_MACH_SPEAR300=y
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CONFIG_MACH_SPEAR310=y
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CONFIG_MACH_SPEAR320=y
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@ -6,6 +6,7 @@ CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_ARCH_MULTI_V7 is not set
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CONFIG_PLAT_SPEAR=y
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CONFIG_ARCH_SPEAR6XX=y
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CONFIG_BINFMT_MISC=y
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@ -0,0 +1,103 @@
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#
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# SPEAr Platform configuration file
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#
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menuconfig PLAT_SPEAR
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bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
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default PLAT_SPEAR_SINGLE
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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if PLAT_SPEAR
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config ARCH_SPEAR13XX
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bool "ST SPEAr13xx"
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depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
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select ARCH_HAVE_CPUFREQ
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select ARM_GIC
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select CPU_V7
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select GPIO_SPEAR_SPICS
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select PINCTRL
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select USE_OF
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help
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Supports for ARM's SPEAR13XX family
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if ARCH_SPEAR13XX
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config MACH_SPEAR1310
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bool "SPEAr1310 Machine support with Device Tree"
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select PINCTRL_SPEAR1310
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help
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Supports ST SPEAr1310 machine configured via the device-tree
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config MACH_SPEAR1340
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bool "SPEAr1340 Machine support with Device Tree"
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select PINCTRL_SPEAR1340
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help
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Supports ST SPEAr1340 machine configured via the device-tree
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endif #ARCH_SPEAR13XX
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config ARCH_SPEAR3XX
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bool "ST SPEAr3xx"
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depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
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depends on !ARCH_SPEAR13XX
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select ARM_VIC
|
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select CPU_ARM926T
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select PINCTRL
|
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select USE_OF
|
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help
|
||||
Supports for ARM's SPEAR3XX family
|
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if ARCH_SPEAR3XX
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config MACH_SPEAR300
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bool "SPEAr300 Machine support with Device Tree"
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select PINCTRL_SPEAR300
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help
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Supports ST SPEAr300 machine configured via the device-tree
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config MACH_SPEAR310
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bool "SPEAr310 Machine support with Device Tree"
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select PINCTRL_SPEAR310
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help
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Supports ST SPEAr310 machine configured via the device-tree
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config MACH_SPEAR320
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bool "SPEAr320 Machine support with Device Tree"
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select PINCTRL_SPEAR320
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help
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Supports ST SPEAr320 machine configured via the device-tree
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endif
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config ARCH_SPEAR6XX
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bool "ST SPEAr6XX"
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depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
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depends on !ARCH_SPEAR13XX
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select ARM_VIC
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select CPU_ARM926T
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help
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Supports for ARM's SPEAR6XX family
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config MACH_SPEAR600
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def_bool y
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depends on ARCH_SPEAR6XX
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select USE_OF
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help
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Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
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config ARCH_SPEAR_AUTO
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def_bool PLAT_SPEAR_SINGLE
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depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
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select ARCH_SPEAR3XX
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endif
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@ -0,0 +1,24 @@
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#
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# SPEAr Platform specific Makefile
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#
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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# Common support
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obj-y := restart.o time.o
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
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obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
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obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o
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obj-$(CONFIG_MACH_SPEAR300) += spear300.o
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obj-$(CONFIG_MACH_SPEAR310) += spear310.o
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obj-$(CONFIG_MACH_SPEAR320) += spear320.o
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obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
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obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
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@ -1,9 +1,8 @@
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/*
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* arch/arm/mach-spear13xx/include/mach/generic.h
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* spear machine family generic header file
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*
|
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* spear13xx machine family generic header file
|
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*
|
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* Copyright (C) 2012 ST Microelectronics
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* Copyright (C) 2009-2012 ST Microelectronics
|
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* Rajeev Kumar <rajeev-dlh.kumar@st.com>
|
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* Viresh Kumar <viresh.linux@gmail.com>
|
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*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
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@ -15,37 +14,46 @@
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#define __MACH_GENERIC_H
|
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|
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#include <linux/dmaengine.h>
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#include <linux/amba/pl08x.h>
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#include <linux/init.h>
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#include <asm/mach/time.h>
|
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|
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/* Add spear13xx structure declarations here */
|
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extern void spear13xx_timer_init(void);
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extern void spear3xx_timer_init(void);
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extern struct pl022_ssp_controller pl022_plat_data;
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extern struct pl08x_platform_data pl080_plat_data;
|
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extern struct dw_dma_platform_data dmac_plat_data;
|
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extern struct dw_dma_slave cf_dma_priv;
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extern struct dw_dma_slave nand_read_dma_priv;
|
||||
extern struct dw_dma_slave nand_write_dma_priv;
|
||||
bool dw_dma_filter(struct dma_chan *chan, void *slave);
|
||||
|
||||
/* Add spear13xx family function declarations here */
|
||||
void __init spear_setup_of_timer(void);
|
||||
void __init spear3xx_clk_init(void __iomem *misc_base,
|
||||
void __iomem *soc_config_base);
|
||||
void __init spear3xx_map_io(void);
|
||||
void __init spear3xx_dt_init_irq(void);
|
||||
void __init spear6xx_clk_init(void __iomem *misc_base);
|
||||
void __init spear13xx_map_io(void);
|
||||
void __init spear13xx_l2x0_init(void);
|
||||
bool dw_dma_filter(struct dma_chan *chan, void *slave);
|
||||
|
||||
void spear_restart(char, const char *);
|
||||
|
||||
void spear13xx_secondary_startup(void);
|
||||
void __cpuinit spear13xx_cpu_die(unsigned int cpu);
|
||||
|
||||
extern struct smp_operations spear13xx_smp_ops;
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR1310
|
||||
void __init spear1310_clk_init(void);
|
||||
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
|
||||
#else
|
||||
static inline void spear1310_clk_init(void) {}
|
||||
static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR1340
|
||||
void __init spear1340_clk_init(void);
|
||||
void __init spear1340_clk_init(void __iomem *misc_base);
|
||||
#else
|
||||
static inline void spear1340_clk_init(void) {}
|
||||
static inline void spear1340_clk_init(void __iomem *misc_base) {}
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_GENERIC_H */
|
||||
|
|
@ -1,10 +1,9 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/irqs.h
|
||||
* IRQ helper macros for spear machine family
|
||||
*
|
||||
* IRQ helper macros for SPEAr6xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
* Copyright (C) 2009-2012 ST Microelectronics
|
||||
* Rajeev Kumar <rajeev-dlh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
@ -14,6 +13,11 @@
|
|||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#ifdef CONFIG_ARCH_SPEAR3XX
|
||||
#define NR_IRQS 256
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_SPEAR6XX
|
||||
/* IRQ definitions */
|
||||
/* VIC 1 */
|
||||
#define IRQ_VIC_END 64
|
||||
|
|
@ -21,5 +25,11 @@
|
|||
/* GPIO pins virtual irqs */
|
||||
#define VIRTUAL_IRQS 24
|
||||
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
#ifdef CONFIG_ARCH_SPEAR13XX
|
||||
#define IRQ_GIC_END 160
|
||||
#define NR_IRQS IRQ_GIC_END
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
|
||||
#define MISC_BASE (VA_SPEAR_ICM3_MISC_REG_BASE)
|
||||
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
|
||||
|
||||
#endif /* __MACH_MISC_REGS_H */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* SPEAr3xx/6xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2009,2012 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SPEAR_H
|
||||
#define __MACH_SPEAR_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
|
||||
|
||||
/* ICM1 - Low speed connection */
|
||||
#define SPEAR_ICM1_2_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
|
||||
#define SPEAR_ICM1_UART_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE)
|
||||
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
|
||||
|
||||
/* ML-1, 2 - Multi Layer CPU Subsystem */
|
||||
#define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
|
||||
#define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
|
||||
|
||||
/* ICM3 - Basic Subsystem */
|
||||
#define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
|
||||
#define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
|
||||
#define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
|
||||
#define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE)
|
||||
#define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000)
|
||||
#define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE
|
||||
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE
|
||||
|
||||
/* Sysctl base for spear platform */
|
||||
#define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE
|
||||
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE
|
||||
#endif /* SPEAR3xx || SPEAR6XX */
|
||||
|
||||
/* SPEAr320 Macros */
|
||||
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
|
||||
#define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000)
|
||||
|
||||
#ifdef CONFIG_ARCH_SPEAR13XX
|
||||
|
||||
#define PERIP_GRP2_BASE UL(0xB3000000)
|
||||
#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
|
||||
#define MCIF_SDHCI_BASE UL(0xB3000000)
|
||||
#define SYSRAM0_BASE UL(0xB3800000)
|
||||
#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
|
||||
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
|
||||
|
||||
#define PERIP_GRP1_BASE UL(0xE0000000)
|
||||
#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
|
||||
#define UART_BASE UL(0xE0000000)
|
||||
#define VA_UART_BASE IOMEM(0xFD000000)
|
||||
#define SSP_BASE UL(0xE0100000)
|
||||
#define MISC_BASE UL(0xE0700000)
|
||||
#define VA_MISC_BASE IOMEM(0xFD700000)
|
||||
|
||||
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
|
||||
#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
|
||||
|
||||
#define SPEAR1310_RAS_BASE UL(0xD8400000)
|
||||
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
|
||||
|
||||
/* A9SM peripheral offsets */
|
||||
#define A9SM_PERIP_BASE UL(0xEC800000)
|
||||
#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000)
|
||||
#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
|
||||
|
||||
#define L2CC_BASE UL(0xED000000)
|
||||
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
|
||||
|
||||
/* others */
|
||||
#define DMAC0_BASE UL(0xEA800000)
|
||||
#define DMAC1_BASE UL(0xEB000000)
|
||||
#define MCIF_CF_BASE UL(0xB2800000)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE UART_BASE
|
||||
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
|
||||
|
||||
#endif /* SPEAR13XX */
|
||||
|
||||
#endif /* __MACH_SPEAR_H */
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
#include <linux/amba/sp810.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
|
||||
#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204)
|
||||
void spear_restart(char mode, const char *cmd)
|
||||
|
|
@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd)
|
|||
/* hardware reset, Use on-chip reset capability */
|
||||
#ifdef CONFIG_ARCH_SPEAR13XX
|
||||
writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
|
||||
#else
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX)
|
||||
sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
#include <linux/pata_arasan_cf_data.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* Base addresses */
|
||||
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
|
||||
#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
|
||||
#define SPEAR1310_RAS_BASE UL(0xD8400000)
|
||||
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
|
||||
|
||||
static struct arasan_cf_pdata cf_pdata = {
|
||||
.cf_if_clk = CF_IF_CLK_166M,
|
||||
|
|
@ -20,10 +20,11 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
#include "spear13xx-dma.h"
|
||||
|
||||
/* Base addresses */
|
||||
#define SPEAR1340_SATA_BASE UL(0xB1000000)
|
||||
#define SPEAR1340_UART1_BASE UL(0xB4100000)
|
||||
|
|
@ -21,10 +21,11 @@
|
|||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
#include "spear13xx-dma.h"
|
||||
|
||||
/* common dw_dma filter routine to be used by peripherals */
|
||||
bool dw_dma_filter(struct dma_chan *chan, void *slave)
|
||||
{
|
||||
|
|
@ -145,9 +146,9 @@ void __init spear13xx_map_io(void)
|
|||
static void __init spear13xx_clk_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("st,spear1310"))
|
||||
spear1310_clk_init();
|
||||
spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
|
||||
else if (of_machine_is_compatible("st,spear1340"))
|
||||
spear1340_clk_init();
|
||||
spear1340_clk_init(VA_MISC_BASE);
|
||||
else
|
||||
pr_err("%s: Unknown machine\n", __func__);
|
||||
}
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* DMAC platform data's slave info */
|
||||
|
|
@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = {
|
|||
static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
{}
|
||||
};
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define SPEAR310_UART1_BASE UL(0xB2000000)
|
||||
|
|
@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = {
|
|||
static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
|
||||
&spear310_uart_data[0]),
|
||||
|
|
@ -19,7 +19,8 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/generic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define SPEAR320_UART1_BASE UL(0xA3000000)
|
||||
|
|
@ -222,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = {
|
|||
static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
|
||||
&spear320_ssp_data[0]),
|
||||
|
|
@ -253,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = {
|
|||
|
||||
struct map_desc spear320_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR320_SOC_CONFIG_BASE,
|
||||
.virtual = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
|
|
@ -14,11 +14,14 @@
|
|||
#define pr_fmt(fmt) "SPEAr3xx: " fmt
|
||||
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/amba/pl080.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <plat/pl080.h>
|
||||
#include <mach/generic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include "pl080.h"
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
#include <mach/misc_regs.h>
|
||||
|
||||
/* ssp device registration */
|
||||
struct pl022_ssp_controller pl022_plat_data = {
|
||||
|
|
@ -65,13 +68,13 @@ struct pl08x_platform_data pl080_plat_data = {
|
|||
*/
|
||||
struct map_desc spear3xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR3XX_ICM1_2_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
|
||||
.virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
|
||||
.virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
|
|
@ -88,7 +91,7 @@ void __init spear3xx_timer_init(void)
|
|||
char pclk_name[] = "pll3_clk";
|
||||
struct clk *gpt_clk, *pclk;
|
||||
|
||||
spear3xx_clk_init();
|
||||
spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
|
||||
|
||||
/* get the system timer clock */
|
||||
gpt_clk = clk_get_sys("gpt0", NULL);
|
||||
|
|
@ -24,9 +24,10 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <plat/pl080.h>
|
||||
#include <mach/generic.h>
|
||||
#include "pl080.h"
|
||||
#include "generic.h"
|
||||
#include <mach/spear.h>
|
||||
#include <mach/misc_regs.h>
|
||||
|
||||
/* dmac device registration */
|
||||
static struct pl08x_channel_data spear600_dma_info[] = {
|
||||
|
|
@ -321,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct pl08x_platform_data pl080_plat_data = {
|
||||
static struct pl08x_platform_data spear6xx_pl080_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl_memcpy =
|
||||
|
|
@ -350,18 +351,18 @@ struct pl08x_platform_data pl080_plat_data = {
|
|||
*/
|
||||
struct map_desc spear6xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR6XX_ML_CPU_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
|
||||
.virtual = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE),
|
||||
.length = 2 * SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_ICM1_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
|
||||
.virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
|
||||
.virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
|
|
@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void)
|
|||
char pclk_name[] = "pll3_clk";
|
||||
struct clk *gpt_clk, *pclk;
|
||||
|
||||
spear6xx_clk_init();
|
||||
spear6xx_clk_init(MISC_BASE);
|
||||
|
||||
/* get the system timer clock */
|
||||
gpt_clk = clk_get_sys("gpt0", NULL);
|
||||
|
|
@ -404,8 +405,8 @@ void __init spear6xx_timer_init(void)
|
|||
|
||||
/* Add auxdata to pass platform data */
|
||||
struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
|
||||
&spear6xx_pl080_plat_data),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#include <linux/time.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/generic.h>
|
||||
#include "generic.h"
|
||||
|
||||
/*
|
||||
* We would use TIMER0 and TIMER1 as clockevent and clocksource.
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
#
|
||||
# SPEAr13XX Machine configuration file
|
||||
#
|
||||
|
||||
if ARCH_SPEAR13XX
|
||||
|
||||
menu "SPEAr13xx Implementations"
|
||||
config MACH_SPEAR1310
|
||||
bool "SPEAr1310 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR1310
|
||||
help
|
||||
Supports ST SPEAr1310 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR1340
|
||||
bool "SPEAr1340 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR1340
|
||||
help
|
||||
Supports ST SPEAr1340 machine configured via the device-tree
|
||||
endmenu
|
||||
endif #ARCH_SPEAR13XX
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#
|
||||
# Makefile for SPEAr13XX machine series
|
||||
#
|
||||
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
|
||||
obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
|
||||
obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear13xx/include/mach/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header spear13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <plat/debug-macro.S>
|
||||
|
|
@ -1 +0,0 @@
|
|||
/* empty */
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear13xx/include/mach/irqs.h
|
||||
*
|
||||
* IRQ helper macros for spear13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define IRQ_GIC_END 160
|
||||
#define NR_IRQS IRQ_GIC_END
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear13xx/include/mach/spear.h
|
||||
*
|
||||
* spear13xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SPEAR13XX_H
|
||||
#define __MACH_SPEAR13XX_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
#define PERIP_GRP2_BASE UL(0xB3000000)
|
||||
#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
|
||||
#define MCIF_SDHCI_BASE UL(0xB3000000)
|
||||
#define SYSRAM0_BASE UL(0xB3800000)
|
||||
#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
|
||||
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
|
||||
|
||||
#define PERIP_GRP1_BASE UL(0xE0000000)
|
||||
#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
|
||||
#define UART_BASE UL(0xE0000000)
|
||||
#define VA_UART_BASE IOMEM(0xFD000000)
|
||||
#define SSP_BASE UL(0xE0100000)
|
||||
#define MISC_BASE UL(0xE0700000)
|
||||
#define VA_MISC_BASE IOMEM(0xFD700000)
|
||||
|
||||
#define A9SM_AND_MPMC_BASE UL(0xEC000000)
|
||||
#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
|
||||
|
||||
/* A9SM peripheral offsets */
|
||||
#define A9SM_PERIP_BASE UL(0xEC800000)
|
||||
#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000)
|
||||
#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
|
||||
|
||||
#define L2CC_BASE UL(0xED000000)
|
||||
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
|
||||
|
||||
/* others */
|
||||
#define DMAC0_BASE UL(0xEA800000)
|
||||
#define DMAC1_BASE UL(0xEB000000)
|
||||
#define MCIF_CF_BASE UL(0xB2800000)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE UART_BASE
|
||||
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
|
||||
|
||||
#endif /* __MACH_SPEAR13XX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/timex.h
|
||||
*
|
||||
* SPEAr3XX machine family specific timex definitions
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TIMEX_H
|
||||
#define __MACH_TIMEX_H
|
||||
|
||||
#include <plat/timex.h>
|
||||
|
||||
#endif /* __MACH_TIMEX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear13xx/include/mach/uncompress.h
|
||||
*
|
||||
* Serial port stubs for kernel decompress status messages
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_UNCOMPRESS_H
|
||||
#define __MACH_UNCOMPRESS_H
|
||||
|
||||
#include <plat/uncompress.h>
|
||||
|
||||
#endif /* __MACH_UNCOMPRESS_H */
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
#
|
||||
# SPEAr3XX Machine configuration file
|
||||
#
|
||||
|
||||
if ARCH_SPEAR3XX
|
||||
|
||||
menu "SPEAr3xx Implementations"
|
||||
config MACH_SPEAR300
|
||||
bool "SPEAr300 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR300
|
||||
help
|
||||
Supports ST SPEAr300 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR310
|
||||
bool "SPEAr310 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR310
|
||||
help
|
||||
Supports ST SPEAr310 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR320
|
||||
bool "SPEAr320 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR320
|
||||
help
|
||||
Supports ST SPEAr320 machine configured via the device-tree
|
||||
endmenu
|
||||
endif #ARCH_SPEAR3XX
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
#
|
||||
# Makefile for SPEAr3XX machine series
|
||||
#
|
||||
|
||||
# common files
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
|
||||
|
||||
# spear300 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
|
||||
|
||||
# spear310 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
|
||||
|
||||
# spear320 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
zreladdr-y += 0x00008000
|
||||
params_phys-y := 0x00000100
|
||||
initrd_phys-y := 0x00800000
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header spear3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <plat/debug-macro.S>
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/generic.h
|
||||
*
|
||||
* SPEAr3XX machine family generic header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_GENERIC_H
|
||||
#define __MACH_GENERIC_H
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
/* Add spear3xx family device structure declarations here */
|
||||
extern void spear3xx_timer_init(void);
|
||||
extern struct pl022_ssp_controller pl022_plat_data;
|
||||
extern struct pl08x_platform_data pl080_plat_data;
|
||||
|
||||
/* Add spear3xx family function declarations here */
|
||||
void __init spear_setup_of_timer(void);
|
||||
void __init spear3xx_clk_init(void);
|
||||
void __init spear3xx_map_io(void);
|
||||
|
||||
void spear_restart(char, const char *);
|
||||
|
||||
#endif /* __MACH_GENERIC_H */
|
||||
|
|
@ -1 +0,0 @@
|
|||
/* empty */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/irqs.h
|
||||
*
|
||||
* IRQ helper macros for SPEAr3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/spear.h
|
||||
*
|
||||
* SPEAr3xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SPEAR3XX_H
|
||||
#define __MACH_SPEAR3XX_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
/* ICM1 - Low speed connection */
|
||||
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
|
||||
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
|
||||
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
|
||||
|
||||
/* ML1 - Multi Layer CPU Subsystem */
|
||||
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
|
||||
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
|
||||
/* ICM3 - Basic Subsystem */
|
||||
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
|
||||
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
|
||||
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
|
||||
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
|
||||
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
|
||||
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE
|
||||
|
||||
/* Sysctl base for spear platform */
|
||||
#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
|
||||
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
|
||||
|
||||
/* SPEAr320 Macros */
|
||||
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
|
||||
#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
|
||||
#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
|
||||
#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
|
||||
#define SPEAR320_UARTX_PCLK_MASK 0x1
|
||||
#define SPEAR320_UART2_PCLK_SHIFT 8
|
||||
#define SPEAR320_UART3_PCLK_SHIFT 9
|
||||
#define SPEAR320_UART4_PCLK_SHIFT 10
|
||||
#define SPEAR320_UART5_PCLK_SHIFT 11
|
||||
#define SPEAR320_UART6_PCLK_SHIFT 12
|
||||
#define SPEAR320_RS485_PCLK_SHIFT 13
|
||||
|
||||
#endif /* __MACH_SPEAR3XX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/timex.h
|
||||
*
|
||||
* SPEAr3XX machine family specific timex definitions
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TIMEX_H
|
||||
#define __MACH_TIMEX_H
|
||||
|
||||
#include <plat/timex.h>
|
||||
|
||||
#endif /* __MACH_TIMEX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/uncompress.h
|
||||
*
|
||||
* Serial port stubs for kernel decompress status messages
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_UNCOMPRESS_H
|
||||
#define __MACH_UNCOMPRESS_H
|
||||
|
||||
#include <plat/uncompress.h>
|
||||
|
||||
#endif /* __MACH_UNCOMPRESS_H */
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#
|
||||
# SPEAr6XX Machine configuration file
|
||||
#
|
||||
|
||||
config MACH_SPEAR600
|
||||
def_bool y
|
||||
depends on ARCH_SPEAR6XX
|
||||
select USE_OF
|
||||
help
|
||||
Supports ST SPEAr600 boards configured via the device-tree
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#
|
||||
# Makefile for SPEAr6XX machine series
|
||||
#
|
||||
|
||||
# common files
|
||||
obj-y += spear6xx.o
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
zreladdr-y += 0x00008000
|
||||
params_phys-y := 0x00000100
|
||||
initrd_phys-y := 0x00800000
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header for SPEAr6xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <plat/debug-macro.S>
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/generic.h
|
||||
*
|
||||
* SPEAr6XX machine family specific generic header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_GENERIC_H
|
||||
#define __MACH_GENERIC_H
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
void __init spear_setup_of_timer(void);
|
||||
void spear_restart(char, const char *);
|
||||
void __init spear6xx_clk_init(void);
|
||||
|
||||
#endif /* __MACH_GENERIC_H */
|
||||
|
|
@ -1 +0,0 @@
|
|||
/* empty */
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/misc_regs.h
|
||||
*
|
||||
* Miscellaneous registers definitions for SPEAr6xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MISC_REGS_H
|
||||
#define __MACH_MISC_REGS_H
|
||||
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
|
||||
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
|
||||
|
||||
#endif /* __MACH_MISC_REGS_H */
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/spear.h
|
||||
*
|
||||
* SPEAr6xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SPEAR6XX_H
|
||||
#define __MACH_SPEAR6XX_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
/* ICM1 - Low speed connection */
|
||||
#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
|
||||
#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
|
||||
|
||||
/* ML-1, 2 - Multi Layer CPU Subsystem */
|
||||
#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
|
||||
/* ICM3 - Basic Subsystem */
|
||||
#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
|
||||
#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
|
||||
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
|
||||
#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
|
||||
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
|
||||
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE
|
||||
|
||||
/* Sysctl base for spear platform */
|
||||
#define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE
|
||||
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE
|
||||
|
||||
#endif /* __MACH_SPEAR6XX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/timex.h
|
||||
*
|
||||
* SPEAr6XX machine family specific timex definitions
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TIMEX_H
|
||||
#define __MACH_TIMEX_H
|
||||
|
||||
#include <plat/timex.h>
|
||||
|
||||
#endif /* __MACH_TIMEX_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/uncompress.h
|
||||
*
|
||||
* Serial port stubs for kernel decompress status messages
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_UNCOMPRESS_H
|
||||
#define __MACH_UNCOMPRESS_H
|
||||
|
||||
#include <plat/uncompress.h>
|
||||
|
||||
#endif /* __MACH_UNCOMPRESS_H */
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
#
|
||||
# SPEAr Platform configuration file
|
||||
#
|
||||
|
||||
if PLAT_SPEAR
|
||||
|
||||
choice
|
||||
prompt "ST SPEAr Family"
|
||||
default ARCH_SPEAR3XX
|
||||
|
||||
config ARCH_SPEAR13XX
|
||||
bool "ST SPEAr13xx with Device Tree"
|
||||
select ARCH_HAVE_CPUFREQ
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select GPIO_SPEAR_SPICS
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select PINCTRL
|
||||
select USE_OF
|
||||
help
|
||||
Supports for ARM's SPEAR13XX family
|
||||
|
||||
config ARCH_SPEAR3XX
|
||||
bool "ST SPEAr3xx with Device Tree"
|
||||
select ARM_VIC
|
||||
select CPU_ARM926T
|
||||
select PINCTRL
|
||||
select USE_OF
|
||||
help
|
||||
Supports for ARM's SPEAR3XX family
|
||||
|
||||
config ARCH_SPEAR6XX
|
||||
bool "SPEAr6XX"
|
||||
select ARM_VIC
|
||||
select CPU_ARM926T
|
||||
help
|
||||
Supports for ARM's SPEAR6XX family
|
||||
|
||||
endchoice
|
||||
|
||||
# Adding SPEAr machine specific configuration files
|
||||
source "arch/arm/mach-spear13xx/Kconfig"
|
||||
source "arch/arm/mach-spear3xx/Kconfig"
|
||||
source "arch/arm/mach-spear6xx/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#
|
||||
# SPEAr Platform specific Makefile
|
||||
#
|
||||
|
||||
# Common support
|
||||
obj-y := restart.o time.o
|
||||
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o
|
||||
obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
|
||||
|
|
@ -17,12 +17,10 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <mach/spear.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
|
||||
/* PLL related registers and bit values */
|
||||
#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
|
||||
#define SPEAR1310_PLL_CFG (misc_base + 0x210)
|
||||
/* PLL_CFG bit values */
|
||||
#define SPEAR1310_CLCD_SYNT_CLK_MASK 1
|
||||
#define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
|
||||
|
|
@ -35,15 +33,15 @@
|
|||
#define SPEAR1310_PLL2_CLK_SHIFT 22
|
||||
#define SPEAR1310_PLL1_CLK_SHIFT 20
|
||||
|
||||
#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214)
|
||||
#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218)
|
||||
#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220)
|
||||
#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224)
|
||||
#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C)
|
||||
#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230)
|
||||
#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238)
|
||||
#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C)
|
||||
#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
|
||||
#define SPEAR1310_PLL1_CTR (misc_base + 0x214)
|
||||
#define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
|
||||
#define SPEAR1310_PLL2_CTR (misc_base + 0x220)
|
||||
#define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
|
||||
#define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
|
||||
#define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
|
||||
#define SPEAR1310_PLL4_CTR (misc_base + 0x238)
|
||||
#define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
|
||||
#define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
|
||||
/* PERIP_CLK_CFG bit values */
|
||||
#define SPEAR1310_GPT_OSC24_VAL 0
|
||||
#define SPEAR1310_GPT_APB_VAL 1
|
||||
|
|
@ -65,7 +63,7 @@
|
|||
#define SPEAR1310_C3_CLK_MASK 1
|
||||
#define SPEAR1310_C3_CLK_SHIFT 1
|
||||
|
||||
#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
|
||||
#define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248)
|
||||
#define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
|
||||
#define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
|
||||
#define SPEAR1310_GMAC_PHY_CLK_MASK 1
|
||||
|
|
@ -73,7 +71,7 @@
|
|||
#define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
|
||||
#define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
|
||||
|
||||
#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
|
||||
#define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C)
|
||||
/* I2S_CLK_CFG register mask */
|
||||
#define SPEAR1310_I2S_SCLK_X_MASK 0x1F
|
||||
#define SPEAR1310_I2S_SCLK_X_SHIFT 27
|
||||
|
|
@ -91,21 +89,21 @@
|
|||
#define SPEAR1310_I2S_SRC_CLK_MASK 2
|
||||
#define SPEAR1310_I2S_SRC_CLK_SHIFT 0
|
||||
|
||||
#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
|
||||
#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254)
|
||||
#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258)
|
||||
#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C)
|
||||
#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260)
|
||||
#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264)
|
||||
#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268)
|
||||
#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270)
|
||||
#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280)
|
||||
#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288)
|
||||
#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290)
|
||||
#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298)
|
||||
#define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250)
|
||||
#define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254)
|
||||
#define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258)
|
||||
#define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C)
|
||||
#define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260)
|
||||
#define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264)
|
||||
#define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268)
|
||||
#define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270)
|
||||
#define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280)
|
||||
#define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288)
|
||||
#define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290)
|
||||
#define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298)
|
||||
/* Check Fractional synthesizer reg masks */
|
||||
|
||||
#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300)
|
||||
#define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300)
|
||||
/* PERIP1_CLK_ENB register masks */
|
||||
#define SPEAR1310_RTC_CLK_ENB 31
|
||||
#define SPEAR1310_ADC_CLK_ENB 30
|
||||
|
|
@ -138,7 +136,7 @@
|
|||
#define SPEAR1310_SYSROM_CLK_ENB 1
|
||||
#define SPEAR1310_BUS_CLK_ENB 0
|
||||
|
||||
#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304)
|
||||
#define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304)
|
||||
/* PERIP2_CLK_ENB register masks */
|
||||
#define SPEAR1310_THSENS_CLK_ENB 8
|
||||
#define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
|
||||
|
|
@ -150,7 +148,7 @@
|
|||
#define SPEAR1310_DDR_CORE_CLK_ENB 1
|
||||
#define SPEAR1310_DDR_CTRL_CLK_ENB 0
|
||||
|
||||
#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310)
|
||||
#define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310)
|
||||
/* RAS_CLK_ENB register masks */
|
||||
#define SPEAR1310_SYNT3_CLK_ENB 17
|
||||
#define SPEAR1310_SYNT2_CLK_ENB 16
|
||||
|
|
@ -172,7 +170,7 @@
|
|||
#define SPEAR1310_ACLK_CLK_ENB 0
|
||||
|
||||
/* RAS Area Control Register */
|
||||
#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000)
|
||||
#define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000)
|
||||
#define SPEAR1310_SSP1_CLK_MASK 3
|
||||
#define SPEAR1310_SSP1_CLK_SHIFT 26
|
||||
#define SPEAR1310_TDM_CLK_MASK 1
|
||||
|
|
@ -197,12 +195,12 @@
|
|||
#define SPEAR1310_PCI_CLK_MASK 1
|
||||
#define SPEAR1310_PCI_CLK_SHIFT 0
|
||||
|
||||
#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004)
|
||||
#define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004)
|
||||
#define SPEAR1310_PHY_CLK_MASK 0x3
|
||||
#define SPEAR1310_RMII_PHY_CLK_SHIFT 0
|
||||
#define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
|
||||
|
||||
#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148)
|
||||
#define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148)
|
||||
#define SPEAR1310_CAN1_CLK_ENB 25
|
||||
#define SPEAR1310_CAN0_CLK_ENB 24
|
||||
#define SPEAR1310_GPT64_CLK_ENB 23
|
||||
|
|
@ -385,7 +383,7 @@ static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
|
|||
static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
|
||||
static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
|
||||
|
||||
void __init spear1310_clk_init(void)
|
||||
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
|
||||
{
|
||||
struct clk *clk, *clk1;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,18 +17,17 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <mach/spear.h>
|
||||
#include "clk.h"
|
||||
|
||||
/* Clock Configuration Registers */
|
||||
#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
|
||||
#define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
|
||||
#define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
|
||||
#define SPEAR1340_HCLK_SRC_SEL_MASK 1
|
||||
#define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
|
||||
#define SPEAR1340_SCLK_SRC_SEL_MASK 3
|
||||
|
||||
/* PLL related registers and bit values */
|
||||
#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
|
||||
#define SPEAR1340_PLL_CFG (misc_base + 0x210)
|
||||
/* PLL_CFG bit values */
|
||||
#define SPEAR1340_CLCD_SYNT_CLK_MASK 1
|
||||
#define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
|
||||
|
|
@ -40,15 +39,15 @@
|
|||
#define SPEAR1340_PLL2_CLK_SHIFT 22
|
||||
#define SPEAR1340_PLL1_CLK_SHIFT 20
|
||||
|
||||
#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
|
||||
#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
|
||||
#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
|
||||
#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
|
||||
#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
|
||||
#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
|
||||
#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
|
||||
#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
|
||||
#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
|
||||
#define SPEAR1340_PLL1_CTR (misc_base + 0x214)
|
||||
#define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
|
||||
#define SPEAR1340_PLL2_CTR (misc_base + 0x220)
|
||||
#define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
|
||||
#define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
|
||||
#define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
|
||||
#define SPEAR1340_PLL4_CTR (misc_base + 0x238)
|
||||
#define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
|
||||
#define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
|
||||
/* PERIP_CLK_CFG bit values */
|
||||
#define SPEAR1340_SPDIF_CLK_MASK 1
|
||||
#define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
|
||||
|
|
@ -66,13 +65,13 @@
|
|||
#define SPEAR1340_C3_CLK_MASK 1
|
||||
#define SPEAR1340_C3_CLK_SHIFT 1
|
||||
|
||||
#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
|
||||
#define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
|
||||
#define SPEAR1340_GMAC_PHY_CLK_MASK 1
|
||||
#define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
|
||||
#define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
|
||||
#define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
|
||||
|
||||
#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
|
||||
#define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
|
||||
/* I2S_CLK_CFG register mask */
|
||||
#define SPEAR1340_I2S_SCLK_X_MASK 0x1F
|
||||
#define SPEAR1340_I2S_SCLK_X_SHIFT 27
|
||||
|
|
@ -90,21 +89,21 @@
|
|||
#define SPEAR1340_I2S_SRC_CLK_MASK 2
|
||||
#define SPEAR1340_I2S_SRC_CLK_SHIFT 0
|
||||
|
||||
#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
|
||||
#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
|
||||
#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
|
||||
#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
|
||||
#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
|
||||
#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
|
||||
#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
|
||||
#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
|
||||
#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
|
||||
#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
|
||||
#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
|
||||
#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
|
||||
#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
|
||||
#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
|
||||
#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
|
||||
#define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
|
||||
#define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
|
||||
#define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
|
||||
#define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
|
||||
#define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
|
||||
#define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
|
||||
#define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
|
||||
#define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
|
||||
#define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
|
||||
#define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
|
||||
#define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
|
||||
#define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
|
||||
#define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
|
||||
#define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
|
||||
#define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
|
||||
#define SPEAR1340_RTC_CLK_ENB 31
|
||||
#define SPEAR1340_ADC_CLK_ENB 30
|
||||
#define SPEAR1340_C3_CLK_ENB 29
|
||||
|
|
@ -133,7 +132,7 @@
|
|||
#define SPEAR1340_SYSROM_CLK_ENB 1
|
||||
#define SPEAR1340_BUS_CLK_ENB 0
|
||||
|
||||
#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
|
||||
#define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
|
||||
#define SPEAR1340_THSENS_CLK_ENB 8
|
||||
#define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
|
||||
#define SPEAR1340_ACP_CLK_ENB 6
|
||||
|
|
@ -144,7 +143,7 @@
|
|||
#define SPEAR1340_DDR_CORE_CLK_ENB 1
|
||||
#define SPEAR1340_DDR_CTRL_CLK_ENB 0
|
||||
|
||||
#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
|
||||
#define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
|
||||
#define SPEAR1340_PLGPIO_CLK_ENB 18
|
||||
#define SPEAR1340_VIDEO_DEC_CLK_ENB 16
|
||||
#define SPEAR1340_VIDEO_ENC_CLK_ENB 15
|
||||
|
|
@ -441,7 +440,7 @@ static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
|
|||
static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
|
||||
"pll2_clk", };
|
||||
|
||||
void __init spear1340_clk_init(void)
|
||||
void __init spear1340_clk_init(void __iomem *misc_base)
|
||||
{
|
||||
struct clk *clk, *clk1;
|
||||
|
||||
|
|
|
|||
|
|
@ -15,21 +15,20 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <mach/misc_regs.h>
|
||||
#include "clk.h"
|
||||
|
||||
static DEFINE_SPINLOCK(_lock);
|
||||
|
||||
#define PLL1_CTR (MISC_BASE + 0x008)
|
||||
#define PLL1_FRQ (MISC_BASE + 0x00C)
|
||||
#define PLL2_CTR (MISC_BASE + 0x014)
|
||||
#define PLL2_FRQ (MISC_BASE + 0x018)
|
||||
#define PLL_CLK_CFG (MISC_BASE + 0x020)
|
||||
#define PLL1_CTR (misc_base + 0x008)
|
||||
#define PLL1_FRQ (misc_base + 0x00C)
|
||||
#define PLL2_CTR (misc_base + 0x014)
|
||||
#define PLL2_FRQ (misc_base + 0x018)
|
||||
#define PLL_CLK_CFG (misc_base + 0x020)
|
||||
/* PLL_CLK_CFG register masks */
|
||||
#define MCTR_CLK_SHIFT 28
|
||||
#define MCTR_CLK_MASK 3
|
||||
|
||||
#define CORE_CLK_CFG (MISC_BASE + 0x024)
|
||||
#define CORE_CLK_CFG (misc_base + 0x024)
|
||||
/* CORE CLK CFG register masks */
|
||||
#define GEN_SYNTH2_3_CLK_SHIFT 18
|
||||
#define GEN_SYNTH2_3_CLK_MASK 1
|
||||
|
|
@ -39,7 +38,7 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define PCLK_RATIO_SHIFT 8
|
||||
#define PCLK_RATIO_MASK 2
|
||||
|
||||
#define PERIP_CLK_CFG (MISC_BASE + 0x028)
|
||||
#define PERIP_CLK_CFG (misc_base + 0x028)
|
||||
/* PERIP_CLK_CFG register masks */
|
||||
#define UART_CLK_SHIFT 4
|
||||
#define UART_CLK_MASK 1
|
||||
|
|
@ -50,7 +49,7 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define GPT2_CLK_SHIFT 12
|
||||
#define GPT_CLK_MASK 1
|
||||
|
||||
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
|
||||
#define PERIP1_CLK_ENB (misc_base + 0x02C)
|
||||
/* PERIP1_CLK_ENB register masks */
|
||||
#define UART_CLK_ENB 3
|
||||
#define SSP_CLK_ENB 5
|
||||
|
|
@ -69,7 +68,7 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define USBH_CLK_ENB 25
|
||||
#define C3_CLK_ENB 31
|
||||
|
||||
#define RAS_CLK_ENB (MISC_BASE + 0x034)
|
||||
#define RAS_CLK_ENB (misc_base + 0x034)
|
||||
#define RAS_AHB_CLK_ENB 0
|
||||
#define RAS_PLL1_CLK_ENB 1
|
||||
#define RAS_APB_CLK_ENB 2
|
||||
|
|
@ -82,20 +81,20 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define RAS_SYNT2_CLK_ENB 10
|
||||
#define RAS_SYNT3_CLK_ENB 11
|
||||
|
||||
#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
|
||||
#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
|
||||
#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
|
||||
#define AMEM_CLK_CFG (MISC_BASE + 0x050)
|
||||
#define PRSC0_CLK_CFG (misc_base + 0x044)
|
||||
#define PRSC1_CLK_CFG (misc_base + 0x048)
|
||||
#define PRSC2_CLK_CFG (misc_base + 0x04C)
|
||||
#define AMEM_CLK_CFG (misc_base + 0x050)
|
||||
#define AMEM_CLK_ENB 0
|
||||
|
||||
#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
|
||||
#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
|
||||
#define UART_CLK_SYNT (MISC_BASE + 0x064)
|
||||
#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
|
||||
#define GEN0_CLK_SYNT (MISC_BASE + 0x06C)
|
||||
#define GEN1_CLK_SYNT (MISC_BASE + 0x070)
|
||||
#define GEN2_CLK_SYNT (MISC_BASE + 0x074)
|
||||
#define GEN3_CLK_SYNT (MISC_BASE + 0x078)
|
||||
#define CLCD_CLK_SYNT (misc_base + 0x05C)
|
||||
#define FIRDA_CLK_SYNT (misc_base + 0x060)
|
||||
#define UART_CLK_SYNT (misc_base + 0x064)
|
||||
#define GMAC_CLK_SYNT (misc_base + 0x068)
|
||||
#define GEN0_CLK_SYNT (misc_base + 0x06C)
|
||||
#define GEN1_CLK_SYNT (misc_base + 0x070)
|
||||
#define GEN2_CLK_SYNT (misc_base + 0x074)
|
||||
#define GEN3_CLK_SYNT (misc_base + 0x078)
|
||||
|
||||
/* pll rate configuration table, in ascending order of rates */
|
||||
static struct pll_rate_tbl pll_rtbl[] = {
|
||||
|
|
@ -211,6 +210,17 @@ static inline void spear310_clk_init(void) { }
|
|||
|
||||
/* array of all spear 320 clock lookups */
|
||||
#ifdef CONFIG_MACH_SPEAR320
|
||||
|
||||
#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
|
||||
#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
|
||||
|
||||
#define SPEAR320_UARTX_PCLK_MASK 0x1
|
||||
#define SPEAR320_UART2_PCLK_SHIFT 8
|
||||
#define SPEAR320_UART3_PCLK_SHIFT 9
|
||||
#define SPEAR320_UART4_PCLK_SHIFT 10
|
||||
#define SPEAR320_UART5_PCLK_SHIFT 11
|
||||
#define SPEAR320_UART6_PCLK_SHIFT 12
|
||||
#define SPEAR320_RS485_PCLK_SHIFT 13
|
||||
#define SMII_PCLK_SHIFT 18
|
||||
#define SMII_PCLK_MASK 2
|
||||
#define SMII_PCLK_VAL_PAD 0x0
|
||||
|
|
@ -235,7 +245,7 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
|
|||
"ras_syn0_gclk", };
|
||||
static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
|
||||
|
||||
static void __init spear320_clk_init(void)
|
||||
static void __init spear320_clk_init(void __iomem *soc_config_base)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
|
|
@ -362,7 +372,7 @@ static void __init spear320_clk_init(void)
|
|||
static inline void spear320_clk_init(void) { }
|
||||
#endif
|
||||
|
||||
void __init spear3xx_clk_init(void)
|
||||
void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
|
||||
{
|
||||
struct clk *clk, *clk1;
|
||||
|
||||
|
|
@ -634,5 +644,5 @@ void __init spear3xx_clk_init(void)
|
|||
else if (of_machine_is_compatible("st,spear310"))
|
||||
spear310_clk_init();
|
||||
else if (of_machine_is_compatible("st,spear320"))
|
||||
spear320_clk_init();
|
||||
spear320_clk_init(soc_config_base);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,28 +13,27 @@
|
|||
#include <linux/clkdev.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <mach/misc_regs.h>
|
||||
#include "clk.h"
|
||||
|
||||
static DEFINE_SPINLOCK(_lock);
|
||||
|
||||
#define PLL1_CTR (MISC_BASE + 0x008)
|
||||
#define PLL1_FRQ (MISC_BASE + 0x00C)
|
||||
#define PLL2_CTR (MISC_BASE + 0x014)
|
||||
#define PLL2_FRQ (MISC_BASE + 0x018)
|
||||
#define PLL_CLK_CFG (MISC_BASE + 0x020)
|
||||
#define PLL1_CTR (misc_base + 0x008)
|
||||
#define PLL1_FRQ (misc_base + 0x00C)
|
||||
#define PLL2_CTR (misc_base + 0x014)
|
||||
#define PLL2_FRQ (misc_base + 0x018)
|
||||
#define PLL_CLK_CFG (misc_base + 0x020)
|
||||
/* PLL_CLK_CFG register masks */
|
||||
#define MCTR_CLK_SHIFT 28
|
||||
#define MCTR_CLK_MASK 3
|
||||
|
||||
#define CORE_CLK_CFG (MISC_BASE + 0x024)
|
||||
#define CORE_CLK_CFG (misc_base + 0x024)
|
||||
/* CORE CLK CFG register masks */
|
||||
#define HCLK_RATIO_SHIFT 10
|
||||
#define HCLK_RATIO_MASK 2
|
||||
#define PCLK_RATIO_SHIFT 8
|
||||
#define PCLK_RATIO_MASK 2
|
||||
|
||||
#define PERIP_CLK_CFG (MISC_BASE + 0x028)
|
||||
#define PERIP_CLK_CFG (misc_base + 0x028)
|
||||
/* PERIP_CLK_CFG register masks */
|
||||
#define CLCD_CLK_SHIFT 2
|
||||
#define CLCD_CLK_MASK 2
|
||||
|
|
@ -48,7 +47,7 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define GPT3_CLK_SHIFT 12
|
||||
#define GPT_CLK_MASK 1
|
||||
|
||||
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
|
||||
#define PERIP1_CLK_ENB (misc_base + 0x02C)
|
||||
/* PERIP1_CLK_ENB register masks */
|
||||
#define UART0_CLK_ENB 3
|
||||
#define UART1_CLK_ENB 4
|
||||
|
|
@ -74,13 +73,13 @@ static DEFINE_SPINLOCK(_lock);
|
|||
#define USBH0_CLK_ENB 25
|
||||
#define USBH1_CLK_ENB 26
|
||||
|
||||
#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
|
||||
#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
|
||||
#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
|
||||
#define PRSC0_CLK_CFG (misc_base + 0x044)
|
||||
#define PRSC1_CLK_CFG (misc_base + 0x048)
|
||||
#define PRSC2_CLK_CFG (misc_base + 0x04C)
|
||||
|
||||
#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
|
||||
#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
|
||||
#define UART_CLK_SYNT (MISC_BASE + 0x064)
|
||||
#define CLCD_CLK_SYNT (misc_base + 0x05C)
|
||||
#define FIRDA_CLK_SYNT (misc_base + 0x060)
|
||||
#define UART_CLK_SYNT (misc_base + 0x064)
|
||||
|
||||
/* vco rate configuration table, in ascending order of rates */
|
||||
static struct pll_rate_tbl pll_rtbl[] = {
|
||||
|
|
@ -115,7 +114,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
|
|||
{.mscale = 1, .nscale = 0}, /* 83 MHz */
|
||||
};
|
||||
|
||||
void __init spear6xx_clk_init(void)
|
||||
void __init spear6xx_clk_init(void __iomem *misc_base)
|
||||
{
|
||||
struct clk *clk, *clk1;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue