mirror of https://gitee.com/openkylin/linux.git
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Daniel writes: Bigger -fixes pile, mostly because I've included Ajax' DP dongle stuff, as discussed on irc. Otherwise just small things: - regression fix to finally make 6bpc auto-dither on dp work (Jani) - reinstate an snb ctx w/a that accidentally got lost in a rework (Chris) - fixup the DP train sequence, logic-goof-up uncovered by Coverty (Chris) - fix set_caching locking (Ben) - fix spurious segfault on con-current gtt mmap faulting (Dimitry and Mika) - some pageflip correctness fixes (still hunting down some issues, but these are the worst offenders of confused code that we've tracked down thus far) from Chris and me - fixup swizzling settings on vlv (Jesse) - gt_mode w/a from Ben added, fixes snb gt1 rc6+hw ctx hangs. * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: Fix GT_MODE default value drm/i915: don't frob the vblank ts in finish_page_flip drm/i915: call drm_handle_vblank before finish_page_flip drm/i915: print warning if vmi915_gem_fault error is not handled drm/i915: EBUSY status handling added to i915_gem_fault(). drm/i915: Try harder to complete DP training pattern 1 drm/i915: set swizzling to none on VLV drm/dp: Make sink count DP 1.2 aware drm/dp: Document DP spec versions for various DPCD registers drm/i915/dp: Be smarter about connection sense for branch devices drm/i915/dp: Fetch downstream port info if needed during DPCD fetch drm/dp: Update DPCD defines drm: Export drm_probe_ddc() drm/i915: Flush the pending flips on the CRTC before modification drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a drm/i915: Fix set_caching locking drm/i915: use adjusted_mode instead of mode for checking the 6bpc force flag
This commit is contained in:
Dave Airlie
commit
1f31c69dac
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|
@ -395,13 +395,14 @@ drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
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* \param adapter : i2c device adaptor
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* \return 1 on success
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*/
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static bool
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bool
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drm_probe_ddc(struct i2c_adapter *adapter)
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{
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unsigned char out;
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return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
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}
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EXPORT_SYMBOL(drm_probe_ddc);
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/**
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* drm_get_edid - get EDID data, if available
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@ -1399,10 +1399,16 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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case 0:
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case -ERESTARTSYS:
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case -EINTR:
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case -EBUSY:
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/*
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* EBUSY is ok: this just means that another thread
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* already did the job.
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*/
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return VM_FAULT_NOPAGE;
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case -ENOMEM:
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return VM_FAULT_OOM;
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default:
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WARN_ON_ONCE(ret);
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return VM_FAULT_SIGBUS;
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}
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}
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@ -3217,10 +3223,6 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
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enum i915_cache_level level;
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int ret;
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ret = i915_mutex_lock_interruptible(dev);
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if (ret)
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return ret;
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switch (args->caching) {
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case I915_CACHING_NONE:
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level = I915_CACHE_NONE;
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@ -3232,6 +3234,10 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
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return -EINVAL;
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}
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ret = i915_mutex_lock_interruptible(dev);
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if (ret)
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return ret;
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obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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if (&obj->base == NULL) {
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ret = -ENOENT;
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@ -328,7 +328,7 @@ mi_set_context(struct intel_ring_buffer *ring,
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* itlb_before_ctx_switch.
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*/
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if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
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ret = ring->flush(ring, 0, 0);
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ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
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if (ret)
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return ret;
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}
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@ -91,7 +91,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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if (INTEL_INFO(dev)->gen >= 6) {
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if (IS_VALLEYVIEW(dev)) {
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else if (INTEL_INFO(dev)->gen >= 6) {
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uint32_t dimm_c0, dimm_c1;
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dimm_c0 = I915_READ(MAD_DIMM_C0);
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dimm_c1 = I915_READ(MAD_DIMM_C1);
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@ -697,12 +697,12 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
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intel_opregion_gse_intr(dev);
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for (i = 0; i < 3; i++) {
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if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
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drm_handle_vblank(dev, i);
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if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
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intel_prepare_page_flip(dev, i);
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intel_finish_page_flip_plane(dev, i);
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}
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if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
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drm_handle_vblank(dev, i);
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}
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/* check event from PCH */
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@ -784,6 +784,12 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
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if (de_iir & DE_GSE)
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intel_opregion_gse_intr(dev);
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if (de_iir & DE_PIPEA_VBLANK)
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drm_handle_vblank(dev, 0);
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if (de_iir & DE_PIPEB_VBLANK)
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drm_handle_vblank(dev, 1);
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if (de_iir & DE_PLANEA_FLIP_DONE) {
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intel_prepare_page_flip(dev, 0);
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intel_finish_page_flip_plane(dev, 0);
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@ -794,12 +800,6 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
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intel_finish_page_flip_plane(dev, 1);
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}
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if (de_iir & DE_PIPEA_VBLANK)
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drm_handle_vblank(dev, 0);
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if (de_iir & DE_PIPEB_VBLANK)
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drm_handle_vblank(dev, 1);
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/* check event from PCH */
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if (de_iir & DE_PCH_EVENT) {
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if (pch_iir & hotplug_mask)
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|
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@ -527,6 +527,9 @@
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# define VS_TIMER_DISPATCH (1 << 6)
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# define MI_FLUSH_ENABLE (1 << 12)
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#define GEN6_GT_MODE 0x20d0
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#define GEN6_GT_MODE_HI (1 << 9)
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#define GFX_MODE 0x02520
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#define GFX_MODE_GEN7 0x0229c
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#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
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|
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@ -2806,13 +2806,34 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
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udelay(100);
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}
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static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long flags;
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bool pending;
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if (atomic_read(&dev_priv->mm.wedged))
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return false;
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spin_lock_irqsave(&dev->event_lock, flags);
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pending = to_intel_crtc(crtc)->unpin_work != NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return pending;
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}
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static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (crtc->fb == NULL)
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return;
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wait_event(dev_priv->pending_flip_queue,
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!intel_crtc_has_pending_flip(crtc));
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mutex_lock(&dev->struct_mutex);
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intel_finish_fb(crtc->fb);
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mutex_unlock(&dev->struct_mutex);
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@ -4370,7 +4391,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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/* default to 8bpc */
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pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
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if (is_dp) {
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if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
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if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
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pipeconf |= PIPECONF_BPP_6 |
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PIPECONF_DITHER_EN |
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PIPECONF_DITHER_TYPE_SP;
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@ -4802,7 +4823,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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target_clock = adjusted_mode->clock;
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/* determine panel color depth */
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dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
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dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
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adjusted_mode);
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if (is_lvds && dev_priv->lvds_dither)
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dither = true;
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@ -6159,15 +6181,13 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
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struct intel_unpin_work *work;
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struct drm_i915_gem_object *obj;
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struct drm_pending_vblank_event *e;
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struct timeval tnow, tvbl;
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struct timeval tvbl;
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unsigned long flags;
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/* Ignore early vblank irqs */
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if (intel_crtc == NULL)
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return;
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do_gettimeofday(&tnow);
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spin_lock_irqsave(&dev->event_lock, flags);
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work = intel_crtc->unpin_work;
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if (work == NULL || !work->pending) {
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|
@ -6181,25 +6201,6 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
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e = work->event;
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e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
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/* Called before vblank count and timestamps have
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* been updated for the vblank interval of flip
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* completion? Need to increment vblank count and
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* add one videorefresh duration to returned timestamp
|
||||
* to account for this. We assume this happened if we
|
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* get called over 0.9 frame durations after the last
|
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* timestamped vblank.
|
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*
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||||
* This calculation can not be used with vrefresh rates
|
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* below 5Hz (10Hz to be on the safe side) without
|
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* promoting to 64 integers.
|
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*/
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if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
|
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9 * crtc->framedur_ns) {
|
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e->event.sequence++;
|
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tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
|
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crtc->framedur_ns);
|
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}
|
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|
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e->event.tv_sec = tvbl.tv_sec;
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e->event.tv_usec = tvbl.tv_usec;
|
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|
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|
|
@ -6216,9 +6217,8 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
|
|||
|
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atomic_clear_mask(1 << intel_crtc->plane,
|
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&obj->pending_flip.counter);
|
||||
if (atomic_read(&obj->pending_flip) == 0)
|
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wake_up(&dev_priv->pending_flip_queue);
|
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|
||||
wake_up(&dev_priv->pending_flip_queue);
|
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schedule_work(&work->work);
|
||||
|
||||
trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#include <drm/i915_drm.h>
|
||||
#include "i915_drv.h"
|
||||
|
||||
#define DP_RECEIVER_CAP_SIZE 0xf
|
||||
#define DP_LINK_STATUS_SIZE 6
|
||||
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
|
||||
|
||||
|
|
@ -1796,8 +1797,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
|
|||
if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
|
||||
break;
|
||||
if (i == intel_dp->lane_count && voltage_tries == 5) {
|
||||
++loop_tries;
|
||||
if (loop_tries == 5) {
|
||||
if (++loop_tries == 5) {
|
||||
DRM_DEBUG_KMS("too many full retries, give up\n");
|
||||
break;
|
||||
}
|
||||
|
|
@ -1807,15 +1807,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
|
|||
}
|
||||
|
||||
/* Check to see if we've tried the same voltage 5 times */
|
||||
if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
|
||||
++voltage_tries;
|
||||
if (voltage_tries == 5) {
|
||||
DRM_DEBUG_KMS("too many voltage retries, give up\n");
|
||||
break;
|
||||
}
|
||||
} else
|
||||
if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
|
||||
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
||||
voltage_tries = 0;
|
||||
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
||||
} else
|
||||
++voltage_tries;
|
||||
|
||||
/* Compute new intel_dp->train_set as requested by target */
|
||||
intel_get_adjust_train(intel_dp, link_status);
|
||||
|
|
@ -1963,12 +1959,25 @@ static bool
|
|||
intel_dp_get_dpcd(struct intel_dp *intel_dp)
|
||||
{
|
||||
if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
|
||||
sizeof(intel_dp->dpcd)) &&
|
||||
(intel_dp->dpcd[DP_DPCD_REV] != 0)) {
|
||||
return true;
|
||||
}
|
||||
sizeof(intel_dp->dpcd)) == 0)
|
||||
return false; /* aux transfer failed */
|
||||
|
||||
return false;
|
||||
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
|
||||
return false; /* DPCD not present */
|
||||
|
||||
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
|
||||
DP_DWN_STRM_PORT_PRESENT))
|
||||
return true; /* native DP sink */
|
||||
|
||||
if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
|
||||
return true; /* no per-port downstream info */
|
||||
|
||||
if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
|
||||
intel_dp->downstream_ports,
|
||||
DP_MAX_DOWNSTREAM_PORTS) == 0)
|
||||
return false; /* downstream port status fetch failed */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -2068,11 +2077,43 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
|
|||
}
|
||||
}
|
||||
|
||||
/* XXX this is probably wrong for multiple downstream ports */
|
||||
static enum drm_connector_status
|
||||
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
|
||||
{
|
||||
if (intel_dp_get_dpcd(intel_dp))
|
||||
uint8_t *dpcd = intel_dp->dpcd;
|
||||
bool hpd;
|
||||
uint8_t type;
|
||||
|
||||
if (!intel_dp_get_dpcd(intel_dp))
|
||||
return connector_status_disconnected;
|
||||
|
||||
/* if there's no downstream port, we're done */
|
||||
if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
|
||||
return connector_status_connected;
|
||||
|
||||
/* If we're HPD-aware, SINK_COUNT changes dynamically */
|
||||
hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
|
||||
if (hpd) {
|
||||
uint8_t reg;
|
||||
if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
|
||||
®, 1))
|
||||
return connector_status_unknown;
|
||||
return DP_GET_SINK_COUNT(reg) ? connector_status_connected
|
||||
: connector_status_disconnected;
|
||||
}
|
||||
|
||||
/* If no HPD, poke DDC gently */
|
||||
if (drm_probe_ddc(&intel_dp->adapter))
|
||||
return connector_status_connected;
|
||||
|
||||
/* Well we tried, say unknown for unreliable port types */
|
||||
type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
|
||||
if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
|
||||
return connector_status_unknown;
|
||||
|
||||
/* Anything else is out of spec, warn and ignore */
|
||||
DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
|
||||
return connector_status_disconnected;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -332,6 +332,7 @@ struct intel_hdmi {
|
|||
};
|
||||
|
||||
#define DP_RECEIVER_CAP_SIZE 0xf
|
||||
#define DP_MAX_DOWNSTREAM_PORTS 0x10
|
||||
#define DP_LINK_CONFIGURATION_SIZE 9
|
||||
|
||||
struct intel_dp {
|
||||
|
|
@ -346,6 +347,7 @@ struct intel_dp {
|
|||
uint8_t link_bw;
|
||||
uint8_t lane_count;
|
||||
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
|
||||
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_dp_aux_data algo;
|
||||
bool is_pch_edp;
|
||||
|
|
|
|||
|
|
@ -3474,6 +3474,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
|
|||
DISPPLANE_TRICKLE_FEED_DISABLE);
|
||||
intel_flush_display_plane(dev_priv, pipe);
|
||||
}
|
||||
|
||||
/* The default value should be 0x200 according to docs, but the two
|
||||
* platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
|
||||
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
|
||||
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
|
||||
}
|
||||
|
||||
static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
|
||||
|
|
|
|||
|
|
@ -878,6 +878,7 @@ extern char *drm_get_tv_subconnector_name(int val);
|
|||
extern char *drm_get_tv_select_name(int val);
|
||||
extern void drm_fb_release(struct drm_file *file_priv);
|
||||
extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
|
||||
extern bool drm_probe_ddc(struct i2c_adapter *adapter);
|
||||
extern struct edid *drm_get_edid(struct drm_connector *connector,
|
||||
struct i2c_adapter *adapter);
|
||||
extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
|
||||
|
|
|
|||
|
|
@ -26,7 +26,19 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
/* From the VESA DisplayPort spec */
|
||||
/*
|
||||
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
|
||||
* DP and DPCD versions are independent. Differences from 1.0 are not noted,
|
||||
* 1.0 devices basically don't exist in the wild.
|
||||
*
|
||||
* Abbreviations, in chronological order:
|
||||
*
|
||||
* eDP: Embedded DisplayPort version 1
|
||||
* DPI: DisplayPort Interoperability Guideline v1.1a
|
||||
* 1.2: DisplayPort 1.2
|
||||
*
|
||||
* 1.2 formally includes both eDP and DPI definitions.
|
||||
*/
|
||||
|
||||
#define AUX_NATIVE_WRITE 0x8
|
||||
#define AUX_NATIVE_READ 0x9
|
||||
|
|
@ -53,7 +65,7 @@
|
|||
|
||||
#define DP_MAX_LANE_COUNT 0x002
|
||||
# define DP_MAX_LANE_COUNT_MASK 0x1f
|
||||
# define DP_TPS3_SUPPORTED (1 << 6)
|
||||
# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
|
||||
# define DP_ENHANCED_FRAME_CAP (1 << 7)
|
||||
|
||||
#define DP_MAX_DOWNSPREAD 0x003
|
||||
|
|
@ -69,19 +81,33 @@
|
|||
/* 10b = TMDS or HDMI */
|
||||
/* 11b = Other */
|
||||
# define DP_FORMAT_CONVERSION (1 << 3)
|
||||
# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
|
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
|
||||
|
||||
#define DP_DOWN_STREAM_PORT_COUNT 0x007
|
||||
#define DP_PORT_COUNT_MASK 0x0f
|
||||
#define DP_OUI_SUPPORT (1 << 7)
|
||||
# define DP_PORT_COUNT_MASK 0x0f
|
||||
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
|
||||
# define DP_OUI_SUPPORT (1 << 7)
|
||||
|
||||
#define DP_EDP_CONFIGURATION_CAP 0x00d
|
||||
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
|
||||
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
|
||||
# define DP_I2C_SPEED_1K 0x01
|
||||
# define DP_I2C_SPEED_5K 0x02
|
||||
# define DP_I2C_SPEED_10K 0x04
|
||||
# define DP_I2C_SPEED_100K 0x08
|
||||
# define DP_I2C_SPEED_400K 0x10
|
||||
# define DP_I2C_SPEED_1M 0x20
|
||||
|
||||
#define DP_PSR_SUPPORT 0x070
|
||||
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
|
||||
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
|
||||
|
||||
/* Multiple stream transport */
|
||||
#define DP_MSTM_CAP 0x021 /* 1.2 */
|
||||
# define DP_MST_CAP (1 << 0)
|
||||
|
||||
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
|
||||
# define DP_PSR_IS_SUPPORTED 1
|
||||
#define DP_PSR_CAPS 0x071
|
||||
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
|
||||
# define DP_PSR_NO_TRAIN_ON_EXIT 1
|
||||
# define DP_PSR_SETUP_TIME_330 (0 << 1)
|
||||
# define DP_PSR_SETUP_TIME_275 (1 << 1)
|
||||
|
|
@ -93,11 +119,36 @@
|
|||
# define DP_PSR_SETUP_TIME_MASK (7 << 1)
|
||||
# define DP_PSR_SETUP_TIME_SHIFT 1
|
||||
|
||||
/*
|
||||
* 0x80-0x8f describe downstream port capabilities, but there are two layouts
|
||||
* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
|
||||
* each port's descriptor is one byte wide. If it was set, each port's is
|
||||
* four bytes wide, starting with the one byte from the base info. As of
|
||||
* DP interop v1.1a only VGA defines additional detail.
|
||||
*/
|
||||
|
||||
/* offset 0 */
|
||||
#define DP_DOWNSTREAM_PORT_0 0x80
|
||||
# define DP_DS_PORT_TYPE_MASK (7 << 0)
|
||||
# define DP_DS_PORT_TYPE_DP 0
|
||||
# define DP_DS_PORT_TYPE_VGA 1
|
||||
# define DP_DS_PORT_TYPE_DVI 2
|
||||
# define DP_DS_PORT_TYPE_HDMI 3
|
||||
# define DP_DS_PORT_TYPE_NON_EDID 4
|
||||
# define DP_DS_PORT_HPD (1 << 3)
|
||||
/* offset 1 for VGA is maximum megapixels per second / 8 */
|
||||
/* offset 2 */
|
||||
# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
|
||||
# define DP_DS_VGA_8BPC 0
|
||||
# define DP_DS_VGA_10BPC 1
|
||||
# define DP_DS_VGA_12BPC 2
|
||||
# define DP_DS_VGA_16BPC 3
|
||||
|
||||
/* link configuration */
|
||||
#define DP_LINK_BW_SET 0x100
|
||||
# define DP_LINK_BW_1_62 0x06
|
||||
# define DP_LINK_BW_2_7 0x0a
|
||||
# define DP_LINK_BW_5_4 0x14
|
||||
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
|
||||
|
||||
#define DP_LANE_COUNT_SET 0x101
|
||||
# define DP_LANE_COUNT_MASK 0x0f
|
||||
|
|
@ -107,7 +158,7 @@
|
|||
# define DP_TRAINING_PATTERN_DISABLE 0
|
||||
# define DP_TRAINING_PATTERN_1 1
|
||||
# define DP_TRAINING_PATTERN_2 2
|
||||
# define DP_TRAINING_PATTERN_3 3
|
||||
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
|
||||
# define DP_TRAINING_PATTERN_MASK 0x3
|
||||
|
||||
# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
|
||||
|
|
@ -148,24 +199,38 @@
|
|||
|
||||
#define DP_DOWNSPREAD_CTRL 0x107
|
||||
# define DP_SPREAD_AMP_0_5 (1 << 4)
|
||||
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
|
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
|
||||
# define DP_SET_ANSI_8B10B (1 << 0)
|
||||
|
||||
#define DP_PSR_EN_CFG 0x170
|
||||
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
|
||||
/* bitmask as for DP_I2C_SPEED_CAP */
|
||||
|
||||
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
|
||||
|
||||
#define DP_MSTM_CTRL 0x111 /* 1.2 */
|
||||
# define DP_MST_EN (1 << 0)
|
||||
# define DP_UP_REQ_EN (1 << 1)
|
||||
# define DP_UPSTREAM_IS_SRC (1 << 2)
|
||||
|
||||
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
|
||||
# define DP_PSR_ENABLE (1 << 0)
|
||||
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
|
||||
# define DP_PSR_CRC_VERIFICATION (1 << 2)
|
||||
# define DP_PSR_FRAME_CAPTURE (1 << 3)
|
||||
|
||||
#define DP_SINK_COUNT 0x200
|
||||
/* prior to 1.2 bit 7 was reserved mbz */
|
||||
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
|
||||
# define DP_SINK_CP_READY (1 << 6)
|
||||
|
||||
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
|
||||
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
|
||||
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
|
||||
# define DP_CP_IRQ (1 << 2)
|
||||
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
|
||||
|
||||
#define DP_EDP_CONFIGURATION_SET 0x10a
|
||||
|
||||
#define DP_LANE0_1_STATUS 0x202
|
||||
#define DP_LANE2_3_STATUS 0x203
|
||||
# define DP_LANE_CR_DONE (1 << 0)
|
||||
|
|
@ -225,14 +290,14 @@
|
|||
# define DP_SET_POWER_D0 0x1
|
||||
# define DP_SET_POWER_D3 0x2
|
||||
|
||||
#define DP_PSR_ERROR_STATUS 0x2006
|
||||
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
|
||||
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
|
||||
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
|
||||
|
||||
#define DP_PSR_ESI 0x2007
|
||||
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
|
||||
# define DP_PSR_CAPS_CHANGE (1 << 0)
|
||||
|
||||
#define DP_PSR_STATUS 0x2008
|
||||
#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
|
||||
# define DP_PSR_SINK_INACTIVE 0
|
||||
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
|
||||
# define DP_PSR_SINK_ACTIVE_RFB 2
|
||||
|
|
|
|||
Loading…
Reference in New Issue