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Merge branch 'staging-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6 

* 'staging-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6: (970 commits)
  staging: usbip: replace usbip_u{dbg,err,info} and printk with dev_ and pr_
  staging:iio: Trivial kconfig reorganization and uniformity improvements.
  staging:iio:documenation partial update.
  staging:iio: use pollfunc allocation helpers in remaining drivers.
  staging:iio:max1363 misc cleanups and use of for_each_bit_set to simplify event code spitting out.
  staging:iio: implement an iio_info structure to take some of the constant elements out of iio_dev.
  staging:iio:meter:ade7758: Use private data space from iio_allocate_device
  staging:iio:accel:lis3l02dq make write_reg_8 take value not a pointer to value.
  staging:iio: ring core cleanups + check if read_last available in lis3l02dq
  staging:iio:core cleanup: squash tiny wrappers and use dev_set_name to handle creation of event interface name.
  staging:iio: poll func allocation clean up.
  staging:iio:ad7780 trivial unused header cleanup.
  staging:iio:adc: AD7780: Use private data space from iio_allocate_device + trivial fixes
  staging:iio:adc:AD7780: Convert to new channel registration method
  staging:iio:adc: AD7606: Drop dev_data in favour of iio_priv()
  staging:iio:adc: AD7606: Consitently use indio_dev
  staging:iio: Rip out helper for software rings.
  staging:iio:adc:AD7298: Use private data space from iio_allocate_device
  staging:iio: rationalization of different buffer implementation hooks.
  staging:iio:imu:adis16400 avoid allocating rx, tx, and state separately from iio_dev.
  ...

Fix up trivial conflicts in
 - drivers/staging/intel_sst/intelmid.c: patches applied in both branches
 - drivers/staging/rt2860/common/cmm_data_{pci,usb}.c: removed vs spelling
 - drivers/staging/usbip/vhci_sysfs.c: trivial header file inclusion
This commit is contained in:
Linus Torvalds 2011-05-23 12:49:28 -07:00
parent c44dead70a 1a4b6f6628
commit 1f3a8e093f
822 changed files with 68403 additions and 171972 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/staging/Kconfig
View File

@ -67,10 +67,6 @@ source "drivers/staging/echo/Kconfig"
source "drivers/staging/brcm80211/Kconfig"
source "drivers/staging/rt2860/Kconfig"
source "drivers/staging/rt2870/Kconfig"
source "drivers/staging/comedi/Kconfig"
source "drivers/staging/olpc_dcon/Kconfig"
@ -177,5 +173,9 @@ source "drivers/staging/gma500/Kconfig"
source "drivers/staging/altera-stapl/Kconfig"
source "drivers/staging/mei/Kconfig"
source "drivers/staging/nvec/Kconfig"
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING

9
drivers/staging/Makefile
View File

@ -12,13 +12,12 @@ obj-$(CONFIG_VIDEO_CX25821) += cx25821/
obj-$(CONFIG_VIDEO_TM6000) += tm6000/
obj-$(CONFIG_DVB_CXD2099) += cxd2099/
obj-$(CONFIG_LIRC_STAGING) += lirc/
obj-$(CONFIG_USB_IP_COMMON) += usbip/
obj-$(CONFIG_USBIP_CORE) += usbip/
obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_BRCM80211) += brcm80211/
obj-$(CONFIG_RT2860) += rt2860/
obj-$(CONFIG_RT2870) += rt2870/
obj-$(CONFIG_BRCMSMAC) += brcm80211/
obj-$(CONFIG_BRCMFMAC) += brcm80211/
obj-$(CONFIG_COMEDI) += comedi/
obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
obj-$(CONFIG_ASUS_OLED) += asus_oled/
@ -70,3 +69,5 @@ obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/
obj-$(CONFIG_TOUCHSCREEN_CLEARPAD_TM1217) += cptm1217/
obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += ste_rmi4/
obj-$(CONFIG_DRM_PSB) += gma500/
obj-$(CONFIG_INTEL_MEI) += mei/
obj-$(CONFIG_MFD_NVEC) += nvec/

6
drivers/staging/ath6kl/Kconfig
View File

@ -100,12 +100,6 @@ config AR600x_BT_RESET_PIN
help
WLAN GPIO to be used for resetting BT
config ATH6KL_CFG80211
bool "CFG80211 support"
depends on ATH6K_LEGACY && CFG80211
help
Enables support for CFG80211 APIs. The default option is to use WEXT. Even with this option enabled, WEXT is not explicitly disabled and the onus of not exercising WEXT lies on the application(s) running in the user space.
config ATH6KL_HTC_RAW_INTERFACE
bool "RAW HTC support"
depends on ATH6K_LEGACY

39
drivers/staging/ath6kl/Makefile
View File

@ -29,26 +29,6 @@ ccflags-y += -I$(obj)/os
ccflags-y += -I$(obj)/bmi/include
ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
ifeq ($(CONFIG_AR600x_SD31_XXX),y)
ccflags-y += -DAR600x_SD31_XXX
endif
ifeq ($(CONFIG_AR600x_WB31_XXX),y)
ccflags-y += -DAR600x_WB31_XXX
endif
ifeq ($(CONFIG_AR600x_SD32_XXX),y)
ccflags-y += -DAR600x_SD32_XXX
endif
ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
ccflags-y += -DAR600x_CUSTOM_XXX
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
ccflags-y += -DENABLE_COEXISTENCE
endif
ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
ccflags-y += -DAR600x_DUAL_ANTENNA
endif
@ -85,11 +65,6 @@ ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
endif
ifeq ($(CONFIG_ATH6KL_CFG80211),y)
ccflags-y += -DATH6K_CONFIG_CFG80211
ath6kl-y += os/linux/cfg80211.o
endif
ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
ccflags-y += -DHTC_RAW_INTERFACE
endif
@ -115,18 +90,8 @@ ifeq ($(CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK),y)
ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
endif
ccflags-y += -DLINUX -DKERNEL_2_6
ccflags-y += -DTCMD
ccflags-y += -DSEND_EVENT_TO_APP
ccflags-y += -DUSER_KEYS
ccflags-y += -DNO_SYNC_FLUSH
ccflags-y += -DHTC_EP_STAT_PROFILING
ccflags-y += -DATH_AR6K_11N_SUPPORT
ccflags-y += -DWAPI_ENABLE
ccflags-y += -DCHECKSUM_OFFLOAD
ccflags-y += -DWLAN_HEADERS
ccflags-y += -DINIT_MODE_DRV_ENABLED
ccflags-y += -DBMIENABLE_SET
obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
ath6kl-y += htc2/AR6000/ar6k.o
@ -136,14 +101,12 @@ ath6kl-y += htc2/htc_recv.o
ath6kl-y += htc2/htc_services.o
ath6kl-y += htc2/htc.o
ath6kl-y += bmi/src/bmi.o
ath6kl-y += os/linux/cfg80211.o
ath6kl-y += os/linux/ar6000_drv.o
ath6kl-y += os/linux/ar6000_raw_if.o
ath6kl-y += os/linux/ar6000_pm.o
ath6kl-y += os/linux/netbuf.o
ath6kl-y += os/linux/wireless_ext.o
ath6kl-y += os/linux/ioctl.o
ath6kl-y += os/linux/hci_bridge.o
ath6kl-y += os/linux/ar6k_pal.o
ath6kl-y += miscdrv/common_drv.o
ath6kl-y += miscdrv/credit_dist.o
ath6kl-y += wmi/wmi.o

3
drivers/staging/ath6kl/bmi/include/bmi_internal.h
View File

@ -26,11 +26,10 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME bmi
#include "a_debug.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "hw/mbox_host_reg.h"
#include "bmi_msg.h"
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)

8
drivers/staging/ath6kl/bmi/src/bmi.c
View File

@ -95,12 +95,12 @@ void
BMICleanup(void)
{
if (pBMICmdCredits) {
A_FREE(pBMICmdCredits);
kfree(pBMICmdCredits);
pBMICmdCredits = NULL;
}
if (pBMICmdBuf) {
A_FREE(pBMICmdBuf);
kfree(pBMICmdBuf);
pBMICmdBuf = NULL;
}
}
@ -127,12 +127,12 @@ BMIDone(struct hif_device *device)
}
if (pBMICmdCredits) {
A_FREE(pBMICmdCredits);
kfree(pBMICmdCredits);
pBMICmdCredits = NULL;
}
if (pBMICmdBuf) {
A_FREE(pBMICmdBuf);
kfree(pBMICmdBuf);
pBMICmdBuf = NULL;
}

1
drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
View File

@ -27,7 +27,6 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "hif.h"
#include "../../../common/hif_sdio_common.h"

382
drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c
View File

@ -37,7 +37,7 @@
#include "hif_internal.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "hw/mbox_host_reg.h"
#if HIF_USE_DMA_BOUNCE_BUFFER
/* macro to check if DMA buffer is WORD-aligned and DMA-able. Most host controllers assume the
@ -53,62 +53,189 @@
#if defined(CONFIG_PM)
#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev)
#define to_sdio_driver(d) container_of(d, struct sdio_driver, drv)
static int hifDeviceSuspend(struct device *dev);
static int hifDeviceResume(struct device *dev);
#endif /* CONFIG_PM */
static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
static void hifDeviceRemoved(struct sdio_func *func);
static struct hif_device *addHifDevice(struct sdio_func *func);
static struct hif_device *getHifDevice(struct sdio_func *func);
static void delHifDevice(struct hif_device * device);
static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte);
static int Func0_CMD52ReadByte(struct mmc_card *card, unsigned int address, unsigned char *byte);
static int hifEnableFunc(struct hif_device *device, struct sdio_func *func);
static int hifDisableFunc(struct hif_device *device, struct sdio_func *func);
OSDRV_CALLBACKS osdrvCallbacks;
int reset_sdio_on_unload = 0;
module_param(reset_sdio_on_unload, int, 0644);
extern u32 nohifscattersupport;
static struct hif_device *ath6kl_alloc_hifdev(struct sdio_func *func)
{
struct hif_device *hifdevice;
/* ------ Static Variables ------ */
static const struct sdio_device_id ar6k_id_table[] = {
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) },
{ /* null */ },
};
MODULE_DEVICE_TABLE(sdio, ar6k_id_table);
hifdevice = kzalloc(sizeof(struct hif_device), GFP_KERNEL);
static struct sdio_driver ar6k_driver = {
.name = "ar6k_wlan",
.id_table = ar6k_id_table,
.probe = hifDeviceInserted,
.remove = hifDeviceRemoved,
#if HIF_USE_DMA_BOUNCE_BUFFER
hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
#endif
hifdevice->func = func;
hifdevice->powerConfig = HIF_DEVICE_POWER_UP;
sdio_set_drvdata(func, hifdevice);
return hifdevice;
}
static struct hif_device *ath6kl_get_hifdev(struct sdio_func *func)
{
return (struct hif_device *) sdio_get_drvdata(func);
}
static const struct sdio_device_id ath6kl_hifdev_ids[] = {
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) },
{ SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) },
{ /* null */ },
};
MODULE_DEVICE_TABLE(sdio, ath6kl_hifdev_ids);
static int ath6kl_hifdev_probe(struct sdio_func *func,
const struct sdio_device_id *id)
{
int ret;
struct hif_device *device;
int count;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("ath6kl: Function: 0x%X, Vendor ID: 0x%X, "
"Device ID: 0x%X, block size: 0x%X/0x%X\n",
func->num, func->vendor, func->device,
func->max_blksize, func->cur_blksize));
ath6kl_alloc_hifdev(func);
device = ath6kl_get_hifdev(func);
device->id = id;
device->is_disabled = true;
spin_lock_init(&device->lock);
spin_lock_init(&device->asynclock);
DL_LIST_INIT(&device->ScatterReqHead);
/* Try to allow scatter unless globally overridden */
if (!nohifscattersupport)
device->scatter_enabled = true;
A_MEMZERO(device->busRequest, sizeof(device->busRequest));
for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) {
sema_init(&device->busRequest[count].sem_req, 0);
hifFreeBusRequest(device, &device->busRequest[count]);
}
sema_init(&device->sem_async, 0);
ret = hifEnableFunc(device, func);
return ret;
}
static void ath6kl_hifdev_remove(struct sdio_func *func)
{
int status = 0;
struct hif_device *device;
device = ath6kl_get_hifdev(func);
if (device->claimedContext != NULL)
status = osdrvCallbacks.
deviceRemovedHandler(device->claimedContext, device);
if (device->is_disabled)
device->is_disabled = false;
else
status = hifDisableFunc(device, func);
CleanupHIFScatterResources(device);
delHifDevice(device);
}
#if defined(CONFIG_PM)
/* New suspend/resume based on linux-2.6.32
* Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch
* Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host
*/
static struct dev_pm_ops ar6k_device_pm_ops = {
.suspend = hifDeviceSuspend,
.resume = hifDeviceResume,
static int ath6kl_hifdev_suspend(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
int status = 0;
struct hif_device *device;
device = ath6kl_get_hifdev(func);
if (device && device->claimedContext &&
osdrvCallbacks.deviceSuspendHandler) {
/* set true first for PowerStateChangeNotify(..) */
device->is_suspend = true;
status = osdrvCallbacks.
deviceSuspendHandler(device->claimedContext);
if (status)
device->is_suspend = false;
}
CleanupHIFScatterResources(device);
switch (status) {
case 0:
return 0;
case A_EBUSY:
/* Hack for kernel in order to support deep sleep and wow */
return -EBUSY;
default:
return -1;
}
}
static int ath6kl_hifdev_resume(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
int status = 0;
struct hif_device *device;
device = ath6kl_get_hifdev(func);
if (device && device->claimedContext &&
osdrvCallbacks.deviceSuspendHandler) {
status = osdrvCallbacks.
deviceResumeHandler(device->claimedContext);
if (status == 0)
device->is_suspend = false;
}
return status;
}
static const struct dev_pm_ops ath6kl_hifdev_pmops = {
.suspend = ath6kl_hifdev_suspend,
.resume = ath6kl_hifdev_resume,
};
#endif /* CONFIG_PM */
static struct sdio_driver ath6kl_hifdev_driver = {
.name = "ath6kl_hifdev",
.id_table = ath6kl_hifdev_ids,
.probe = ath6kl_hifdev_probe,
.remove = ath6kl_hifdev_remove,
#if defined(CONFIG_PM)
.drv = {
.pm = &ath6kl_hifdev_pmops,
},
#endif
};
/* make sure we only unregister when registered. */
static int registered = 0;
OSDRV_CALLBACKS osdrvCallbacks;
extern u32 onebitmode;
extern u32 busspeedlow;
extern u32 debughif;
static void ResetAllCards(void);
static int hifDisableFunc(struct hif_device *device, struct sdio_func *func);
static int hifEnableFunc(struct hif_device *device, struct sdio_func *func);
#ifdef DEBUG
@ -125,31 +252,22 @@ ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif,
/* ------ Functions ------ */
int HIFInit(OSDRV_CALLBACKS *callbacks)
{
int status;
AR_DEBUG_ASSERT(callbacks != NULL);
int r;
AR_DEBUG_ASSERT(callbacks != NULL);
A_REGISTER_MODULE_DEBUG_INFO(hif);
A_REGISTER_MODULE_DEBUG_INFO(hif);
/* store the callback handlers */
osdrvCallbacks = *callbacks;
/* store the callback handlers */
osdrvCallbacks = *callbacks;
/* Register with bus driver core */
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n"));
registered = 1;
#if defined(CONFIG_PM)
if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) {
ar6k_driver.drv.pm = &ar6k_device_pm_ops;
}
#endif /* CONFIG_PM */
status = sdio_register_driver(&ar6k_driver);
AR_DEBUG_ASSERT(status==0);
/* Register with bus driver core */
registered = 1;
if (status != 0) {
return A_ERROR;
}
return 0;
r = sdio_register_driver(&ath6kl_hifdev_driver);
if (r < 0)
return r;
return 0;
}
static int
@ -763,7 +881,7 @@ HIFShutDownDevice(struct hif_device *device)
registered = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("AR6000: Unregistering with the bus driver\n"));
sdio_unregister_driver(&ar6k_driver);
sdio_unregister_driver(&ath6kl_hifdev_driver);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("AR6000: Unregistered\n"));
}
@ -778,7 +896,7 @@ hifIRQHandler(struct sdio_func *func)
struct hif_device *device;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n"));
device = getHifDevice(func);
device = ath6kl_get_hifdev(func);
atomic_set(&device->irqHandling, 1);
/* release the host during ints so we can pick it back up when we process cmds */
sdio_release_host(device->func);
@ -823,48 +941,6 @@ static int enable_task(void *param)
}
#endif
static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
{
int ret;
struct hif_device * device;
int count;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n",
func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize));
addHifDevice(func);
device = getHifDevice(func);
device->id = id;
device->is_disabled = true;
spin_lock_init(&device->lock);
spin_lock_init(&device->asynclock);
DL_LIST_INIT(&device->ScatterReqHead);
if (!nohifscattersupport) {
/* try to allow scatter operation on all instances,
* unless globally overridden */
device->scatter_enabled = true;
}
/* Initialize the bus requests to be used later */
A_MEMZERO(device->busRequest, sizeof(device->busRequest));
for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
sema_init(&device->busRequest[count].sem_req, 0);
hifFreeBusRequest(device, &device->busRequest[count]);
}
sema_init(&device->sem_async, 0);
ret = hifEnableFunc(device, func);
return ret;
}
void
HIFAckInterrupt(struct hif_device *device)
{
@ -955,7 +1031,7 @@ static int hifDisableFunc(struct hif_device *device, struct sdio_func *func)
int status = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDisableFunc\n"));
device = getHifDevice(func);
device = ath6kl_get_hifdev(func);
if (!IS_ERR(device->async_task)) {
init_completion(&device->async_completion);
device->async_shutdown = 1;
@ -1004,7 +1080,7 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
int ret = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifEnableFunc\n"));
device = getHifDevice(func);
device = ath6kl_get_hifdev(func);
if (device->is_disabled) {
/* enable the SDIO function */
@ -1016,7 +1092,7 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
if (ret) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret));
sdio_release_host(func);
return A_ERROR;
return ret;
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n"));
}
@ -1027,14 +1103,14 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
__FUNCTION__, ret));
sdio_release_host(func);
return A_ERROR;
return ret;
}
ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
sdio_release_host(func);
if (ret) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n",
__FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
return A_ERROR;
return ret;
}
device->is_disabled = false;
/* create async I/O thread */
@ -1045,7 +1121,7 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
"AR6K Async");
if (IS_ERR(device->async_task)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
return A_ERROR;
return -ENOMEM;
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
wake_up_process(device->async_task );
@ -1060,14 +1136,14 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
} else {
taskFunc = enable_task;
taskName = "AR6K enable";
ret = A_PENDING;
ret = -ENOMEM;
#endif /* CONFIG_PM */
}
/* create resume thread */
pTask = kthread_create(taskFunc, (void *)device, taskName);
if (IS_ERR(pTask)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create enabel task\n", __FUNCTION__));
return A_ERROR;
return -ENOMEM;
}
wake_up_process(pTask);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifEnableFunc\n"));
@ -1076,79 +1152,6 @@ static int hifEnableFunc(struct hif_device *device, struct sdio_func *func)
return ret;
}
#if defined(CONFIG_PM)
static int hifDeviceSuspend(struct device *dev)
{
struct sdio_func *func=dev_to_sdio_func(dev);
int status = 0;
struct hif_device *device;
device = getHifDevice(func);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceSuspend\n"));
if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
device->is_suspend = true; /* set true first for PowerStateChangeNotify(..) */
status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext);
if (status) {
device->is_suspend = false;
}
}
CleanupHIFScatterResources(device);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceSuspend\n"));
switch (status) {
case 0:
return 0;
case A_EBUSY:
return -EBUSY; /* Hack for kernel in order to support deep sleep and wow */
default:
return -1;
}
}
static int hifDeviceResume(struct device *dev)
{
struct sdio_func *func=dev_to_sdio_func(dev);
int status = 0;
struct hif_device *device;
device = getHifDevice(func);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceResume\n"));
if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
status = osdrvCallbacks.deviceResumeHandler(device->claimedContext);
if (status == 0) {
device->is_suspend = false;
}
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceResume\n"));
return status;
}
#endif /* CONFIG_PM */
static void hifDeviceRemoved(struct sdio_func *func)
{
int status = 0;
struct hif_device *device;
AR_DEBUG_ASSERT(func != NULL);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
device = getHifDevice(func);
if (device->claimedContext != NULL) {
status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device);
}
if (device->is_disabled) {
device->is_disabled = false;
} else {
status = hifDisableFunc(device, func);
}
CleanupHIFScatterResources(device);
delHifDevice(device);
AR_DEBUG_ASSERT(status == 0);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n"));
}
/*
* This should be moved to AR6K HTC layer.
*/
@ -1182,33 +1185,6 @@ int hifWaitForPendingRecv(struct hif_device *device)
return 0;
}
static struct hif_device *
addHifDevice(struct sdio_func *func)
{
struct hif_device *hifdevice;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n"));
AR_DEBUG_ASSERT(func != NULL);
hifdevice = kzalloc(sizeof(struct hif_device), GFP_KERNEL);
AR_DEBUG_ASSERT(hifdevice != NULL);
#if HIF_USE_DMA_BOUNCE_BUFFER
hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL);
#endif
hifdevice->func = func;
hifdevice->powerConfig = HIF_DEVICE_POWER_UP;
sdio_set_drvdata(func, hifdevice);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice));
return hifdevice;
}
static struct hif_device *
getHifDevice(struct sdio_func *func)
{
AR_DEBUG_ASSERT(func != NULL);
return (struct hif_device *)sdio_get_drvdata(func);
}
static void
delHifDevice(struct hif_device * device)
{

10
drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
View File

@ -309,7 +309,7 @@ int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_
(MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(struct hif_scatter_item)));
if (NULL == pReqPriv->pHifScatterReq) {
A_FREE(pReqPriv);
kfree(pReqPriv);
break;
}
/* just zero the main part of the scatter request */
@ -319,8 +319,8 @@ int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_
/* allocate a bus request for this scatter request */
busrequest = hifAllocateBusRequest(device);
if (NULL == busrequest) {
A_FREE(pReqPriv->pHifScatterReq);
A_FREE(pReqPriv);
kfree(pReqPriv->pHifScatterReq);
kfree(pReqPriv);
break;
}
/* assign the scatter request to this bus request */
@ -382,11 +382,11 @@ void CleanupHIFScatterResources(struct hif_device *device)
}
if (pReqPriv->pHifScatterReq != NULL) {
A_FREE(pReqPriv->pHifScatterReq);
kfree(pReqPriv->pHifScatterReq);
pReqPriv->pHifScatterReq = NULL;
}
A_FREE(pReqPriv);
kfree(pReqPriv);
}
}

5
drivers/staging/ath6kl/htc2/AR6000/ar6k.c
View File

@ -25,8 +25,7 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "hw/mbox_host_reg.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
@ -743,7 +742,7 @@ static void DevCleanupVirtualScatterSupport(struct ar6k_device *pDev)
if (NULL == pReq) {
break;
}
A_FREE(pReq);
kfree(pReq);
}
}

3
drivers/staging/ath6kl/htc2/AR6000/ar6k.h
View File

@ -42,7 +42,6 @@
//#define MBOXHW_UNIT_TEST 1
#include "athstartpack.h"
PREPACK struct ar6k_irq_proc_registers {
u8 host_int_status;
u8 cpu_int_status;
@ -69,8 +68,6 @@ PREPACK struct ar6k_gmbox_ctrl_registers {
u8 int_status_enable;
} POSTPACK;
#include "athendpack.h"
#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(struct ar6k_irq_enable_registers)
#define AR6K_REG_IO_BUFFER_SIZE 32

3
drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
View File

@ -25,8 +25,7 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "hw/mbox_host_reg.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"

1
drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c
View File

@ -24,7 +24,6 @@
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"

3
drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
View File

@ -24,7 +24,6 @@
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
@ -108,7 +107,7 @@ static void HCIUartCleanup(struct gmbox_proto_hci_uart *pProtocol)
A_MUTEX_DELETE(&pProtocol->HCIRxLock);
A_MUTEX_DELETE(&pProtocol->HCITxLock);
A_FREE(pProtocol);
kfree(pProtocol);
}
static int InitTxCreditState(struct gmbox_proto_hci_uart *pProt)

10
drivers/staging/ath6kl/htc2/htc.c
View File

@ -70,7 +70,7 @@ static void HTCCleanup(struct htc_target *target)
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
if (target->HTCControlBuffers[i].Buffer) {
A_FREE(target->HTCControlBuffers[i].Buffer);
kfree(target->HTCControlBuffers[i].Buffer);
}
}
@ -86,7 +86,7 @@ static void HTCCleanup(struct htc_target *target)
A_MUTEX_DELETE(&target->HTCTxLock);
}
/* free our instance */
A_FREE(target);
kfree(target);
}
/* registered target arrival callback from the HIF layer */
@ -448,9 +448,7 @@ static void ResetEndpointStates(struct htc_target *target)
pEndpoint->ServiceID = 0;
pEndpoint->MaxMsgLength = 0;
pEndpoint->MaxTxQueueDepth = 0;
#ifdef HTC_EP_STAT_PROFILING
A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
#endif
INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
@ -527,7 +525,6 @@ bool HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
struct htc_endpoint_stats *pStats)
{
#ifdef HTC_EP_STAT_PROFILING
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
bool clearStats = false;
bool sample = false;
@ -568,9 +565,6 @@ bool HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
UNLOCK_HTC_TX(target);
return true;
#else
return false;
#endif
}
struct ar6k_device *HTCGetAR6KDevice(void *HTCHandle)

9
drivers/staging/ath6kl/htc2/htc_internal.h
View File

@ -27,7 +27,6 @@
* processing errors, the last frame header is dump for comparison */
//#define HTC_CAPTURE_LAST_FRAME
//#define HTC_EP_STAT_PROFILING
#ifdef __cplusplus
extern "C" {
@ -37,7 +36,6 @@ extern "C" {
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "htc_debug.h"
#include "htc.h"
@ -82,17 +80,10 @@ struct htc_endpoint {
struct htc_target *target; /* back pointer to target */
u8 SeqNo; /* TX seq no (helpful) for debugging */
u32 LocalConnectionFlags; /* local connection flags */
#ifdef HTC_EP_STAT_PROFILING
struct htc_endpoint_stats EndPointStats; /* endpoint statistics */
#endif
};
#ifdef HTC_EP_STAT_PROFILING
#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
#else
#define INC_HTC_EP_STAT(p,stat,count)
#endif
#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
#define NUM_CONTROL_BUFFERS 8

6
drivers/staging/ath6kl/htc2/htc_recv.c
View File

@ -36,7 +36,6 @@
(pP)->PktInfo.AsRx.ExpectedHdr, \
(pP)->Endpoint))
#ifdef HTC_EP_STAT_PROFILING
#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads) \
{ \
INC_HTC_EP_STAT((ep), RxReceived, 1); \
@ -46,9 +45,6 @@
INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1); \
} \
}
#else
#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
#endif
static void DoRecvCompletion(struct htc_endpoint *pEndpoint,
struct htc_packet_queue *pQueueToIndicate)
@ -931,12 +927,10 @@ static void HTCAsyncRecvScatterCompletion(struct hif_scatter_req *pScatterReq)
}
if (!status) {
#ifdef HTC_EP_STAT_PROFILING
LOCK_HTC_RX(target);
HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
UNLOCK_HTC_RX(target);
#endif
if (i == (pScatterReq->ValidScatterEntries - 1)) {
/* last packet's more packets flag is set based on the lookahead */
SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket);

5
drivers/staging/ath6kl/htc2/htc_send.c
View File

@ -776,9 +776,6 @@ void HTCProcessCreditRpt(struct htc_target *target, HTC_CREDIT_REPORT *pRpt, int
AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n",
pRpt->EndpointID, pRpt->Credits));
#ifdef HTC_EP_STAT_PROFILING
INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
@ -797,8 +794,6 @@ void HTCProcessCreditRpt(struct htc_target *target, HTC_CREDIT_REPORT *pRpt, int
INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
}
#endif
if (ENDPOINT_0 == pRpt->EndpointID) {
/* always give endpoint 0 credits back */
pEndpoint->CreditDist.TxCredits += pRpt->Credits;

22
drivers/staging/ath6kl/include/a_config.h
View File

@ -26,28 +26,6 @@
#ifndef _A_CONFIG_H_
#define _A_CONFIG_H_
#ifdef UNDER_NWIFI
#include "../os/windows/include/config.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/config.h"
#endif
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/config_linux.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/config_rexos.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/win/config_win.h"
#endif
#ifdef THREADX
#include "../os/threadx/include/common/config_threadx.h"
#endif
#endif

29
drivers/staging/ath6kl/include/a_debug.h
View File

@ -27,7 +27,6 @@
extern "C" {
#endif /* __cplusplus */
#include <a_types.h>
#include <a_osapi.h>
/* standard debug print masks bits 0..7 */
@ -187,35 +186,7 @@ void a_dump_module_debug_info_by_name(char *module_name);
void a_module_debug_support_init(void);
void a_module_debug_support_cleanup(void);
#ifdef UNDER_NWIFI
#include "../os/windows/include/debug.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/debug.h"
#endif
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/debug_linux.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/debug_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/debug_win.h"
#endif
#ifdef WIN_NWF
#include <debug_win.h>
#endif
#ifdef THREADX
#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
#include "../os/threadx/include/common/debug_threadx.h"
#endif
#ifdef __cplusplus
}

22
drivers/staging/ath6kl/include/a_drv.h
View File

@ -27,28 +27,6 @@
#ifndef _A_DRV_H_
#define _A_DRV_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/athdrv_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/athdrv.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athdrv.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/athdrv_rexos.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/athdrv.h"
#endif
#ifdef THREADX
#include "../os/threadx/include/common/athdrv_threadx.h"
#endif
#endif /* _ADRV_H_ */

28
drivers/staging/ath6kl/include/a_drv_api.h
View File

@ -130,34 +130,6 @@ extern "C" {
#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \
ar6000_peer_event ((devt), (eventCode), (bssid))
#ifdef CONFIG_HOST_GPIO_SUPPORT
#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
ar6000_gpio_intr_rx((intr_mask), (input_values))
#define A_WMI_GPIO_DATA_RX(reg_id, value) \
ar6000_gpio_data_rx((reg_id), (value))
#define A_WMI_GPIO_ACK_RX() \
ar6000_gpio_ack_rx()
#endif
#ifdef SEND_EVENT_TO_APP
#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
ar6000_send_event_to_app((ar), (eventId), (datap), (len))
#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
#else
#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
#endif
#ifdef CONFIG_HOST_TCMD_SUPPORT
#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
ar6000_tcmd_rx_report_event((devt), (results), (len))

29
drivers/staging/ath6kl/include/a_osapi.h
View File

@ -27,35 +27,6 @@
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/osapi_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/osapi.h"
#include "../os/windows/include/netbuf.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/osapi.h"
#include "../os/windows/include/netbuf.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/osapi_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/osapi_win.h"
#include "../os/win_art/include/netbuf.h"
#endif
#ifdef WIN_NWF
#include <osapi_win.h>
#endif
#if defined(THREADX)
#include "../os/threadx/include/common/osapi_threadx.h"
#endif
#endif /* _OSAPI_H_ */

58
drivers/staging/ath6kl/include/a_types.h
View File

@ -1,58 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="a_types.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of the basic atheros data types.
// It is used to map the data types in atheros files to a platform specific
// type.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_TYPES_H_
#define _A_TYPES_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/athtypes_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/athtypes.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athtypes.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/athtypes_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/athtypes_win.h"
#endif
#ifdef WIN_NWF
#include <athtypes_win.h>
#endif
#ifdef THREADX
#include "../os/threadx/include/common/athtypes_threadx.h"
#endif
#endif /* _ATHTYPES_H_ */

22
drivers/staging/ath6kl/include/ar6000_api.h
View File

@ -26,29 +26,7 @@
#ifndef _AR6000_API_H_
#define _AR6000_API_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/ar6xapi_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/ar6xapi.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/ar6xapi.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/ar6xapi_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/ar6xapi_win.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/ar6xapi.h"
#endif
#endif /* _AR6000_API_H */

52
drivers/staging/ath6kl/include/athendpack.h
View File

@ -1,52 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="athendpack.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// end compiler-specific structure packing
//
// Author(s): ="Atheros"
//==============================================================================
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */
#ifdef INTEGRITY
#include "integrity/athendpack_integrity.h"
#endif /* INTEGRITY */
#ifdef NUCLEUS
#endif /* NUCLEUS */
#ifdef UNDER_NWIFI
#include "../os/windows/include/athendpack.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athendpack.h"
#endif /* WINCE */
#ifdef WIN_NWF
#include <athendpack_win.h>
#endif

55
drivers/staging/ath6kl/include/athstartpack.h
View File

@ -1,55 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="athstartpack.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// start compiler-specific structure packing
//
// Author(s): ="Atheros"
//==============================================================================
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */
#ifdef INTEGRITY
#include "integrity/athstartpack_integrity.h"
#endif /* INTEGRITY */
#ifdef NUCLEUS
#endif /* NUCLEUS */
#ifdef UNDER_NWIFI
#include "../os/windows/include/athstartpack.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athstartpack.h"
#endif /* WINCE */
#ifdef WIN_NWF
#include <athstartpack_win.h>
#endif
#ifdef THREADX
#include "../os/threadx/include/common/osapi_threadx.h"
#endif

1
drivers/staging/ath6kl/include/bmi.h
View File

@ -32,7 +32,6 @@ extern "C" {
/* Header files */
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "hif.h"
#include "a_osapi.h"
#include "bmi_msg.h"

60
drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h
View File

@ -1,60 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2006-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __AR6002_REGDUMP_H__
#define __AR6002_REGDUMP_H__
#if !defined(__ASSEMBLER__)
/*
* XTensa CPU state
* This must match the state saved by the target exception handler.
*/
struct XTensa_exception_frame_s {
u32 xt_pc;
u32 xt_ps;
u32 xt_sar;
u32 xt_vpri;
u32 xt_a2;
u32 xt_a3;
u32 xt_a4;
u32 xt_a5;
u32 xt_exccause;
u32 xt_lcount;
u32 xt_lbeg;
u32 xt_lend;
u32 epc1, epc2, epc3, epc4;
/* Extra info to simplify post-mortem stack walkback */
#define AR6002_REGDUMP_FRAMES 10
struct {
u32 a0; /* pc */
u32 a1; /* sp */
u32 a2;
u32 a3;
} wb[AR6002_REGDUMP_FRAMES];
};
typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
#define RD_SIZE sizeof(CPU_exception_frame_t)
#endif
#endif /* __AR6002_REGDUMP_H__ */

64
drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h
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#ifndef _ANALOG_INTF_REG_REG_H_
#define _ANALOG_INTF_REG_REG_H_
#define SW_OVERRIDE_ADDRESS 0x00000080
#define SW_OVERRIDE_OFFSET 0x00000080
#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
#define SW_OVERRIDE_ENABLE_MSB 0
#define SW_OVERRIDE_ENABLE_LSB 0
#define SW_OVERRIDE_ENABLE_MASK 0x00000001
#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
#define SIN_VAL_ADDRESS 0x00000084
#define SIN_VAL_OFFSET 0x00000084
#define SIN_VAL_SIN_MSB 0
#define SIN_VAL_SIN_LSB 0
#define SIN_VAL_SIN_MASK 0x00000001
#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
#define SW_SCLK_ADDRESS 0x00000088
#define SW_SCLK_OFFSET 0x00000088
#define SW_SCLK_SW_SCLK_MSB 0
#define SW_SCLK_SW_SCLK_LSB 0
#define SW_SCLK_SW_SCLK_MASK 0x00000001
#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
#define SW_CNTL_ADDRESS 0x0000008c
#define SW_CNTL_OFFSET 0x0000008c
#define SW_CNTL_SW_SCAPTURE_MSB 2
#define SW_CNTL_SW_SCAPTURE_LSB 2
#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
#define SW_CNTL_SW_SUPDATE_MSB 1
#define SW_CNTL_SW_SUPDATE_LSB 1
#define SW_CNTL_SW_SUPDATE_MASK 0x00000002
#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
#define SW_CNTL_SW_SOUT_MSB 0
#define SW_CNTL_SW_SOUT_LSB 0
#define SW_CNTL_SW_SOUT_MASK 0x00000001
#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
#ifndef __ASSEMBLER__
typedef struct analog_intf_reg_reg_s {
unsigned char pad0[128]; /* pad to 0x80 */
volatile unsigned int sw_override;
volatile unsigned int sin_val;
volatile unsigned int sw_sclk;
volatile unsigned int sw_cntl;
} analog_intf_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _ANALOG_INTF_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h
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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h
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#ifndef _APB_MAP_H_
#define _APB_MAP_H_
#define RTC_BASE_ADDRESS 0x00004000
#define VMC_BASE_ADDRESS 0x00008000
#define UART_BASE_ADDRESS 0x0000c000
#define SI_BASE_ADDRESS 0x00010000
#define GPIO_BASE_ADDRESS 0x00014000
#define MBOX_BASE_ADDRESS 0x00018000
#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define MAC_BASE_ADDRESS 0x00020000
#endif /* _APB_MAP_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h
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#ifndef _GPIO_REG_REG_H_
#define _GPIO_REG_REG_H_
#define GPIO_OUT_ADDRESS 0x00000000
#define GPIO_OUT_OFFSET 0x00000000
#define GPIO_OUT_DATA_MSB 17
#define GPIO_OUT_DATA_LSB 0
#define GPIO_OUT_DATA_MASK 0x0003ffff
#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
#define GPIO_OUT_W1TS_ADDRESS 0x00000004
#define GPIO_OUT_W1TS_OFFSET 0x00000004
#define GPIO_OUT_W1TS_DATA_MSB 17
#define GPIO_OUT_W1TS_DATA_LSB 0
#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff
#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
#define GPIO_OUT_W1TC_ADDRESS 0x00000008
#define GPIO_OUT_W1TC_OFFSET 0x00000008
#define GPIO_OUT_W1TC_DATA_MSB 17
#define GPIO_OUT_W1TC_DATA_LSB 0
#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff
#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
#define GPIO_ENABLE_ADDRESS 0x0000000c
#define GPIO_ENABLE_OFFSET 0x0000000c
#define GPIO_ENABLE_DATA_MSB 17
#define GPIO_ENABLE_DATA_LSB 0
#define GPIO_ENABLE_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010
#define GPIO_ENABLE_W1TS_OFFSET 0x00000010
#define GPIO_ENABLE_W1TS_DATA_MSB 17
#define GPIO_ENABLE_W1TS_DATA_LSB 0
#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014
#define GPIO_ENABLE_W1TC_OFFSET 0x00000014
#define GPIO_ENABLE_W1TC_DATA_MSB 17
#define GPIO_ENABLE_W1TC_DATA_LSB 0
#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
#define GPIO_IN_ADDRESS 0x00000018
#define GPIO_IN_OFFSET 0x00000018
#define GPIO_IN_DATA_MSB 17
#define GPIO_IN_DATA_LSB 0
#define GPIO_IN_DATA_MASK 0x0003ffff
#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
#define GPIO_STATUS_ADDRESS 0x0000001c
#define GPIO_STATUS_OFFSET 0x0000001c
#define GPIO_STATUS_INTERRUPT_MSB 17
#define GPIO_STATUS_INTERRUPT_LSB 0
#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
#define GPIO_STATUS_W1TS_ADDRESS 0x00000020
#define GPIO_STATUS_W1TS_OFFSET 0x00000020
#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17
#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0
#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
#define GPIO_STATUS_W1TC_ADDRESS 0x00000024
#define GPIO_STATUS_W1TC_OFFSET 0x00000024
#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17
#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0
#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
#define GPIO_PIN0_ADDRESS 0x00000028
#define GPIO_PIN0_OFFSET 0x00000028
#define GPIO_PIN0_CONFIG_MSB 12
#define GPIO_PIN0_CONFIG_LSB 11
#define GPIO_PIN0_CONFIG_MASK 0x00001800
#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
#define GPIO_PIN0_INT_TYPE_MSB 9
#define GPIO_PIN0_INT_TYPE_LSB 7
#define GPIO_PIN0_INT_TYPE_MASK 0x00000380
#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
#define GPIO_PIN0_PAD_DRIVER_MSB 2
#define GPIO_PIN0_PAD_DRIVER_LSB 2
#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
#define GPIO_PIN0_SOURCE_MSB 0
#define GPIO_PIN0_SOURCE_LSB 0
#define GPIO_PIN0_SOURCE_MASK 0x00000001
#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
#define GPIO_PIN1_ADDRESS 0x0000002c
#define GPIO_PIN1_OFFSET 0x0000002c
#define GPIO_PIN1_CONFIG_MSB 12
#define GPIO_PIN1_CONFIG_LSB 11
#define GPIO_PIN1_CONFIG_MASK 0x00001800
#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
#define GPIO_PIN1_INT_TYPE_MSB 9
#define GPIO_PIN1_INT_TYPE_LSB 7
#define GPIO_PIN1_INT_TYPE_MASK 0x00000380
#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
#define GPIO_PIN1_PAD_DRIVER_MSB 2
#define GPIO_PIN1_PAD_DRIVER_LSB 2
#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
#define GPIO_PIN1_SOURCE_MSB 0
#define GPIO_PIN1_SOURCE_LSB 0
#define GPIO_PIN1_SOURCE_MASK 0x00000001
#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
#define GPIO_PIN2_ADDRESS 0x00000030
#define GPIO_PIN2_OFFSET 0x00000030
#define GPIO_PIN2_CONFIG_MSB 12
#define GPIO_PIN2_CONFIG_LSB 11
#define GPIO_PIN2_CONFIG_MASK 0x00001800
#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
#define GPIO_PIN2_INT_TYPE_MSB 9
#define GPIO_PIN2_INT_TYPE_LSB 7
#define GPIO_PIN2_INT_TYPE_MASK 0x00000380
#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
#define GPIO_PIN2_PAD_DRIVER_MSB 2
#define GPIO_PIN2_PAD_DRIVER_LSB 2
#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
#define GPIO_PIN2_SOURCE_MSB 0
#define GPIO_PIN2_SOURCE_LSB 0
#define GPIO_PIN2_SOURCE_MASK 0x00000001
#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
#define GPIO_PIN3_ADDRESS 0x00000034
#define GPIO_PIN3_OFFSET 0x00000034
#define GPIO_PIN3_CONFIG_MSB 12
#define GPIO_PIN3_CONFIG_LSB 11
#define GPIO_PIN3_CONFIG_MASK 0x00001800
#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
#define GPIO_PIN3_INT_TYPE_MSB 9
#define GPIO_PIN3_INT_TYPE_LSB 7
#define GPIO_PIN3_INT_TYPE_MASK 0x00000380
#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
#define GPIO_PIN3_PAD_DRIVER_MSB 2
#define GPIO_PIN3_PAD_DRIVER_LSB 2
#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
#define GPIO_PIN3_SOURCE_MSB 0
#define GPIO_PIN3_SOURCE_LSB 0
#define GPIO_PIN3_SOURCE_MASK 0x00000001
#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
#define GPIO_PIN4_ADDRESS 0x00000038
#define GPIO_PIN4_OFFSET 0x00000038
#define GPIO_PIN4_CONFIG_MSB 12
#define GPIO_PIN4_CONFIG_LSB 11
#define GPIO_PIN4_CONFIG_MASK 0x00001800
#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
#define GPIO_PIN4_INT_TYPE_MSB 9
#define GPIO_PIN4_INT_TYPE_LSB 7
#define GPIO_PIN4_INT_TYPE_MASK 0x00000380
#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
#define GPIO_PIN4_PAD_DRIVER_MSB 2
#define GPIO_PIN4_PAD_DRIVER_LSB 2
#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
#define GPIO_PIN4_SOURCE_MSB 0
#define GPIO_PIN4_SOURCE_LSB 0
#define GPIO_PIN4_SOURCE_MASK 0x00000001
#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
#define GPIO_PIN5_ADDRESS 0x0000003c
#define GPIO_PIN5_OFFSET 0x0000003c
#define GPIO_PIN5_CONFIG_MSB 12
#define GPIO_PIN5_CONFIG_LSB 11
#define GPIO_PIN5_CONFIG_MASK 0x00001800
#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
#define GPIO_PIN5_INT_TYPE_MSB 9
#define GPIO_PIN5_INT_TYPE_LSB 7
#define GPIO_PIN5_INT_TYPE_MASK 0x00000380
#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
#define GPIO_PIN5_PAD_DRIVER_MSB 2
#define GPIO_PIN5_PAD_DRIVER_LSB 2
#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
#define GPIO_PIN5_SOURCE_MSB 0
#define GPIO_PIN5_SOURCE_LSB 0
#define GPIO_PIN5_SOURCE_MASK 0x00000001
#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
#define GPIO_PIN6_ADDRESS 0x00000040
#define GPIO_PIN6_OFFSET 0x00000040
#define GPIO_PIN6_CONFIG_MSB 12
#define GPIO_PIN6_CONFIG_LSB 11
#define GPIO_PIN6_CONFIG_MASK 0x00001800
#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
#define GPIO_PIN6_INT_TYPE_MSB 9
#define GPIO_PIN6_INT_TYPE_LSB 7
#define GPIO_PIN6_INT_TYPE_MASK 0x00000380
#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
#define GPIO_PIN6_PAD_DRIVER_MSB 2
#define GPIO_PIN6_PAD_DRIVER_LSB 2
#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
#define GPIO_PIN6_SOURCE_MSB 0
#define GPIO_PIN6_SOURCE_LSB 0
#define GPIO_PIN6_SOURCE_MASK 0x00000001
#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
#define GPIO_PIN7_ADDRESS 0x00000044
#define GPIO_PIN7_OFFSET 0x00000044
#define GPIO_PIN7_CONFIG_MSB 12
#define GPIO_PIN7_CONFIG_LSB 11
#define GPIO_PIN7_CONFIG_MASK 0x00001800
#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
#define GPIO_PIN7_INT_TYPE_MSB 9
#define GPIO_PIN7_INT_TYPE_LSB 7
#define GPIO_PIN7_INT_TYPE_MASK 0x00000380
#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
#define GPIO_PIN7_PAD_DRIVER_MSB 2
#define GPIO_PIN7_PAD_DRIVER_LSB 2
#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
#define GPIO_PIN7_SOURCE_MSB 0
#define GPIO_PIN7_SOURCE_LSB 0
#define GPIO_PIN7_SOURCE_MASK 0x00000001
#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
#define GPIO_PIN8_ADDRESS 0x00000048
#define GPIO_PIN8_OFFSET 0x00000048
#define GPIO_PIN8_CONFIG_MSB 12
#define GPIO_PIN8_CONFIG_LSB 11
#define GPIO_PIN8_CONFIG_MASK 0x00001800
#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
#define GPIO_PIN8_INT_TYPE_MSB 9
#define GPIO_PIN8_INT_TYPE_LSB 7
#define GPIO_PIN8_INT_TYPE_MASK 0x00000380
#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
#define GPIO_PIN8_PAD_DRIVER_MSB 2
#define GPIO_PIN8_PAD_DRIVER_LSB 2
#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
#define GPIO_PIN8_SOURCE_MSB 0
#define GPIO_PIN8_SOURCE_LSB 0
#define GPIO_PIN8_SOURCE_MASK 0x00000001
#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
#define GPIO_PIN9_ADDRESS 0x0000004c
#define GPIO_PIN9_OFFSET 0x0000004c
#define GPIO_PIN9_CONFIG_MSB 12
#define GPIO_PIN9_CONFIG_LSB 11
#define GPIO_PIN9_CONFIG_MASK 0x00001800
#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
#define GPIO_PIN9_INT_TYPE_MSB 9
#define GPIO_PIN9_INT_TYPE_LSB 7
#define GPIO_PIN9_INT_TYPE_MASK 0x00000380
#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
#define GPIO_PIN9_PAD_DRIVER_MSB 2
#define GPIO_PIN9_PAD_DRIVER_LSB 2
#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
#define GPIO_PIN9_SOURCE_MSB 0
#define GPIO_PIN9_SOURCE_LSB 0
#define GPIO_PIN9_SOURCE_MASK 0x00000001
#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
#define GPIO_PIN10_ADDRESS 0x00000050
#define GPIO_PIN10_OFFSET 0x00000050
#define GPIO_PIN10_CONFIG_MSB 12
#define GPIO_PIN10_CONFIG_LSB 11
#define GPIO_PIN10_CONFIG_MASK 0x00001800
#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
#define GPIO_PIN10_INT_TYPE_MSB 9
#define GPIO_PIN10_INT_TYPE_LSB 7
#define GPIO_PIN10_INT_TYPE_MASK 0x00000380
#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
#define GPIO_PIN10_PAD_DRIVER_MSB 2
#define GPIO_PIN10_PAD_DRIVER_LSB 2
#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
#define GPIO_PIN10_SOURCE_MSB 0
#define GPIO_PIN10_SOURCE_LSB 0
#define GPIO_PIN10_SOURCE_MASK 0x00000001
#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
#define GPIO_PIN11_ADDRESS 0x00000054
#define GPIO_PIN11_OFFSET 0x00000054
#define GPIO_PIN11_CONFIG_MSB 12
#define GPIO_PIN11_CONFIG_LSB 11
#define GPIO_PIN11_CONFIG_MASK 0x00001800
#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
#define GPIO_PIN11_INT_TYPE_MSB 9
#define GPIO_PIN11_INT_TYPE_LSB 7
#define GPIO_PIN11_INT_TYPE_MASK 0x00000380
#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
#define GPIO_PIN11_PAD_DRIVER_MSB 2
#define GPIO_PIN11_PAD_DRIVER_LSB 2
#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
#define GPIO_PIN11_SOURCE_MSB 0
#define GPIO_PIN11_SOURCE_LSB 0
#define GPIO_PIN11_SOURCE_MASK 0x00000001
#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
#define GPIO_PIN12_ADDRESS 0x00000058
#define GPIO_PIN12_OFFSET 0x00000058
#define GPIO_PIN12_CONFIG_MSB 12
#define GPIO_PIN12_CONFIG_LSB 11
#define GPIO_PIN12_CONFIG_MASK 0x00001800
#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
#define GPIO_PIN12_INT_TYPE_MSB 9
#define GPIO_PIN12_INT_TYPE_LSB 7
#define GPIO_PIN12_INT_TYPE_MASK 0x00000380
#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
#define GPIO_PIN12_PAD_DRIVER_MSB 2
#define GPIO_PIN12_PAD_DRIVER_LSB 2
#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
#define GPIO_PIN12_SOURCE_MSB 0
#define GPIO_PIN12_SOURCE_LSB 0
#define GPIO_PIN12_SOURCE_MASK 0x00000001
#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
#define GPIO_PIN13_ADDRESS 0x0000005c
#define GPIO_PIN13_OFFSET 0x0000005c
#define GPIO_PIN13_CONFIG_MSB 12
#define GPIO_PIN13_CONFIG_LSB 11
#define GPIO_PIN13_CONFIG_MASK 0x00001800
#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
#define GPIO_PIN13_INT_TYPE_MSB 9
#define GPIO_PIN13_INT_TYPE_LSB 7
#define GPIO_PIN13_INT_TYPE_MASK 0x00000380
#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
#define GPIO_PIN13_PAD_DRIVER_MSB 2
#define GPIO_PIN13_PAD_DRIVER_LSB 2
#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
#define GPIO_PIN13_SOURCE_MSB 0
#define GPIO_PIN13_SOURCE_LSB 0
#define GPIO_PIN13_SOURCE_MASK 0x00000001
#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
#define GPIO_PIN14_ADDRESS 0x00000060
#define GPIO_PIN14_OFFSET 0x00000060
#define GPIO_PIN14_CONFIG_MSB 12
#define GPIO_PIN14_CONFIG_LSB 11
#define GPIO_PIN14_CONFIG_MASK 0x00001800
#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
#define GPIO_PIN14_INT_TYPE_MSB 9
#define GPIO_PIN14_INT_TYPE_LSB 7
#define GPIO_PIN14_INT_TYPE_MASK 0x00000380
#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
#define GPIO_PIN14_PAD_DRIVER_MSB 2
#define GPIO_PIN14_PAD_DRIVER_LSB 2
#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
#define GPIO_PIN14_SOURCE_MSB 0
#define GPIO_PIN14_SOURCE_LSB 0
#define GPIO_PIN14_SOURCE_MASK 0x00000001
#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
#define GPIO_PIN15_ADDRESS 0x00000064
#define GPIO_PIN15_OFFSET 0x00000064
#define GPIO_PIN15_CONFIG_MSB 12
#define GPIO_PIN15_CONFIG_LSB 11
#define GPIO_PIN15_CONFIG_MASK 0x00001800
#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
#define GPIO_PIN15_INT_TYPE_MSB 9
#define GPIO_PIN15_INT_TYPE_LSB 7
#define GPIO_PIN15_INT_TYPE_MASK 0x00000380
#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
#define GPIO_PIN15_PAD_DRIVER_MSB 2
#define GPIO_PIN15_PAD_DRIVER_LSB 2
#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
#define GPIO_PIN15_SOURCE_MSB 0
#define GPIO_PIN15_SOURCE_LSB 0
#define GPIO_PIN15_SOURCE_MASK 0x00000001
#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
#define GPIO_PIN16_ADDRESS 0x00000068
#define GPIO_PIN16_OFFSET 0x00000068
#define GPIO_PIN16_CONFIG_MSB 12
#define GPIO_PIN16_CONFIG_LSB 11
#define GPIO_PIN16_CONFIG_MASK 0x00001800
#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
#define GPIO_PIN16_INT_TYPE_MSB 9
#define GPIO_PIN16_INT_TYPE_LSB 7
#define GPIO_PIN16_INT_TYPE_MASK 0x00000380
#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
#define GPIO_PIN16_PAD_DRIVER_MSB 2
#define GPIO_PIN16_PAD_DRIVER_LSB 2
#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
#define GPIO_PIN16_SOURCE_MSB 0
#define GPIO_PIN16_SOURCE_LSB 0
#define GPIO_PIN16_SOURCE_MASK 0x00000001
#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
#define GPIO_PIN17_ADDRESS 0x0000006c
#define GPIO_PIN17_OFFSET 0x0000006c
#define GPIO_PIN17_CONFIG_MSB 12
#define GPIO_PIN17_CONFIG_LSB 11
#define GPIO_PIN17_CONFIG_MASK 0x00001800
#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
#define GPIO_PIN17_INT_TYPE_MSB 9
#define GPIO_PIN17_INT_TYPE_LSB 7
#define GPIO_PIN17_INT_TYPE_MASK 0x00000380
#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
#define GPIO_PIN17_PAD_DRIVER_MSB 2
#define GPIO_PIN17_PAD_DRIVER_LSB 2
#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
#define GPIO_PIN17_SOURCE_MSB 0
#define GPIO_PIN17_SOURCE_LSB 0
#define GPIO_PIN17_SOURCE_MASK 0x00000001
#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
#define SDIO_PIN_ADDRESS 0x00000070
#define SDIO_PIN_OFFSET 0x00000070
#define SDIO_PIN_PAD_PULL_MSB 3
#define SDIO_PIN_PAD_PULL_LSB 2
#define SDIO_PIN_PAD_PULL_MASK 0x0000000c
#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
#define SDIO_PIN_PAD_STRENGTH_MSB 1
#define SDIO_PIN_PAD_STRENGTH_LSB 0
#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003
#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
#define CLK_REQ_PIN_ADDRESS 0x00000074
#define CLK_REQ_PIN_OFFSET 0x00000074
#define CLK_REQ_PIN_ATE_OE_L_MSB 4
#define CLK_REQ_PIN_ATE_OE_L_LSB 4
#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010
#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
#define CLK_REQ_PIN_PAD_PULL_MSB 3
#define CLK_REQ_PIN_PAD_PULL_LSB 2
#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c
#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1
#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0
#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003
#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
#define SIGMA_DELTA_ADDRESS 0x00000078
#define SIGMA_DELTA_OFFSET 0x00000078
#define SIGMA_DELTA_ENABLE_MSB 16
#define SIGMA_DELTA_ENABLE_LSB 16
#define SIGMA_DELTA_ENABLE_MASK 0x00010000
#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
#define SIGMA_DELTA_PRESCALAR_MSB 15
#define SIGMA_DELTA_PRESCALAR_LSB 8
#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
#define SIGMA_DELTA_TARGET_MSB 7
#define SIGMA_DELTA_TARGET_LSB 0
#define SIGMA_DELTA_TARGET_MASK 0x000000ff
#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
#define DEBUG_CONTROL_ADDRESS 0x0000007c
#define DEBUG_CONTROL_OFFSET 0x0000007c
#define DEBUG_CONTROL_OBS_OE_L_MSB 1
#define DEBUG_CONTROL_OBS_OE_L_LSB 1
#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002
#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
#define DEBUG_CONTROL_ENABLE_MSB 0
#define DEBUG_CONTROL_ENABLE_LSB 0
#define DEBUG_CONTROL_ENABLE_MASK 0x00000001
#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
#define DEBUG_INPUT_SEL_ADDRESS 0x00000080
#define DEBUG_INPUT_SEL_OFFSET 0x00000080
#define DEBUG_INPUT_SEL_SRC_MSB 3
#define DEBUG_INPUT_SEL_SRC_LSB 0
#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
#define DEBUG_OUT_ADDRESS 0x00000084
#define DEBUG_OUT_OFFSET 0x00000084
#define DEBUG_OUT_DATA_MSB 17
#define DEBUG_OUT_DATA_LSB 0
#define DEBUG_OUT_DATA_MASK 0x0003ffff
#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
#define LA_CONTROL_ADDRESS 0x00000088
#define LA_CONTROL_OFFSET 0x00000088
#define LA_CONTROL_RUN_MSB 1
#define LA_CONTROL_RUN_LSB 1
#define LA_CONTROL_RUN_MASK 0x00000002
#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
#define LA_CONTROL_TRIGGERED_MSB 0
#define LA_CONTROL_TRIGGERED_LSB 0
#define LA_CONTROL_TRIGGERED_MASK 0x00000001
#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
#define LA_CLOCK_ADDRESS 0x0000008c
#define LA_CLOCK_OFFSET 0x0000008c
#define LA_CLOCK_DIV_MSB 7
#define LA_CLOCK_DIV_LSB 0
#define LA_CLOCK_DIV_MASK 0x000000ff
#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
#define LA_STATUS_ADDRESS 0x00000090
#define LA_STATUS_OFFSET 0x00000090
#define LA_STATUS_INTERRUPT_MSB 0
#define LA_STATUS_INTERRUPT_LSB 0
#define LA_STATUS_INTERRUPT_MASK 0x00000001
#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094
#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094
#define LA_TRIGGER_SAMPLE_COUNT_MSB 15
#define LA_TRIGGER_SAMPLE_COUNT_LSB 0
#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff
#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
#define LA_TRIGGER_POSITION_ADDRESS 0x00000098
#define LA_TRIGGER_POSITION_OFFSET 0x00000098
#define LA_TRIGGER_POSITION_VALUE_MSB 15
#define LA_TRIGGER_POSITION_VALUE_LSB 0
#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff
#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
#define LA_PRE_TRIGGER_ADDRESS 0x0000009c
#define LA_PRE_TRIGGER_OFFSET 0x0000009c
#define LA_PRE_TRIGGER_COUNT_MSB 15
#define LA_PRE_TRIGGER_COUNT_LSB 0
#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff
#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
#define LA_POST_TRIGGER_ADDRESS 0x000000a0
#define LA_POST_TRIGGER_OFFSET 0x000000a0
#define LA_POST_TRIGGER_COUNT_MSB 15
#define LA_POST_TRIGGER_COUNT_LSB 0
#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff
#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
#define LA_FILTER_CONTROL_ADDRESS 0x000000a4
#define LA_FILTER_CONTROL_OFFSET 0x000000a4
#define LA_FILTER_CONTROL_DELTA_MSB 0
#define LA_FILTER_CONTROL_DELTA_LSB 0
#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001
#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
#define LA_FILTER_DATA_ADDRESS 0x000000a8
#define LA_FILTER_DATA_OFFSET 0x000000a8
#define LA_FILTER_DATA_MATCH_MSB 17
#define LA_FILTER_DATA_MATCH_LSB 0
#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff
#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac
#define LA_FILTER_WILDCARD_OFFSET 0x000000ac
#define LA_FILTER_WILDCARD_MATCH_MSB 17
#define LA_FILTER_WILDCARD_MATCH_LSB 0
#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0
#define LA_TRIGGERA_DATA_OFFSET 0x000000b0
#define LA_TRIGGERA_DATA_MATCH_MSB 17
#define LA_TRIGGERA_DATA_MATCH_LSB 0
#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff
#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4
#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4
#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17
#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0
#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8
#define LA_TRIGGERB_DATA_OFFSET 0x000000b8
#define LA_TRIGGERB_DATA_MATCH_MSB 17
#define LA_TRIGGERB_DATA_MATCH_LSB 0
#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff
#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc
#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc
#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17
#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0
#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
#define LA_TRIGGER_ADDRESS 0x000000c0
#define LA_TRIGGER_OFFSET 0x000000c0
#define LA_TRIGGER_EVENT_MSB 2
#define LA_TRIGGER_EVENT_LSB 0
#define LA_TRIGGER_EVENT_MASK 0x00000007
#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
#define LA_FIFO_ADDRESS 0x000000c4
#define LA_FIFO_OFFSET 0x000000c4
#define LA_FIFO_FULL_MSB 1
#define LA_FIFO_FULL_LSB 1
#define LA_FIFO_FULL_MASK 0x00000002
#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
#define LA_FIFO_EMPTY_MSB 0
#define LA_FIFO_EMPTY_LSB 0
#define LA_FIFO_EMPTY_MASK 0x00000001
#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
#define LA_ADDRESS 0x000000c8
#define LA_OFFSET 0x000000c8
#define LA_DATA_MSB 17
#define LA_DATA_LSB 0
#define LA_DATA_MASK 0x0003ffff
#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK)
#define ANT_PIN_ADDRESS 0x000000d0
#define ANT_PIN_OFFSET 0x000000d0
#define ANT_PIN_PAD_PULL_MSB 3
#define ANT_PIN_PAD_PULL_LSB 2
#define ANT_PIN_PAD_PULL_MASK 0x0000000c
#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
#define ANT_PIN_PAD_STRENGTH_MSB 1
#define ANT_PIN_PAD_STRENGTH_LSB 0
#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003
#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
#define ANTD_PIN_ADDRESS 0x000000d4
#define ANTD_PIN_OFFSET 0x000000d4
#define ANTD_PIN_PAD_PULL_MSB 1
#define ANTD_PIN_PAD_PULL_LSB 0
#define ANTD_PIN_PAD_PULL_MASK 0x00000003
#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
#define GPIO_PIN_ADDRESS 0x000000d8
#define GPIO_PIN_OFFSET 0x000000d8
#define GPIO_PIN_PAD_PULL_MSB 3
#define GPIO_PIN_PAD_PULL_LSB 2
#define GPIO_PIN_PAD_PULL_MASK 0x0000000c
#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
#define GPIO_PIN_PAD_STRENGTH_MSB 1
#define GPIO_PIN_PAD_STRENGTH_LSB 0
#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003
#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
#define GPIO_H_PIN_ADDRESS 0x000000dc
#define GPIO_H_PIN_OFFSET 0x000000dc
#define GPIO_H_PIN_PAD_PULL_MSB 1
#define GPIO_H_PIN_PAD_PULL_LSB 0
#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003
#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
#define BT_PIN_ADDRESS 0x000000e0
#define BT_PIN_OFFSET 0x000000e0
#define BT_PIN_PAD_PULL_MSB 3
#define BT_PIN_PAD_PULL_LSB 2
#define BT_PIN_PAD_PULL_MASK 0x0000000c
#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
#define BT_PIN_PAD_STRENGTH_MSB 1
#define BT_PIN_PAD_STRENGTH_LSB 0
#define BT_PIN_PAD_STRENGTH_MASK 0x00000003
#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
#define BT_WLAN_PIN_ADDRESS 0x000000e4
#define BT_WLAN_PIN_OFFSET 0x000000e4
#define BT_WLAN_PIN_PAD_PULL_MSB 1
#define BT_WLAN_PIN_PAD_PULL_LSB 0
#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003
#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
#define SI_UART_PIN_ADDRESS 0x000000e8
#define SI_UART_PIN_OFFSET 0x000000e8
#define SI_UART_PIN_PAD_PULL_MSB 3
#define SI_UART_PIN_PAD_PULL_LSB 2
#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c
#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
#define SI_UART_PIN_PAD_STRENGTH_MSB 1
#define SI_UART_PIN_PAD_STRENGTH_LSB 0
#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003
#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
#define CLK32K_PIN_ADDRESS 0x000000ec
#define CLK32K_PIN_OFFSET 0x000000ec
#define CLK32K_PIN_PAD_PULL_MSB 1
#define CLK32K_PIN_PAD_PULL_LSB 0
#define CLK32K_PIN_PAD_PULL_MASK 0x00000003
#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0
#define RESET_TUPLE_STATUS_OFFSET 0x000000f0
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
#ifndef __ASSEMBLER__
typedef struct gpio_reg_reg_s {
volatile unsigned int gpio_out;
volatile unsigned int gpio_out_w1ts;
volatile unsigned int gpio_out_w1tc;
volatile unsigned int gpio_enable;
volatile unsigned int gpio_enable_w1ts;
volatile unsigned int gpio_enable_w1tc;
volatile unsigned int gpio_in;
volatile unsigned int gpio_status;
volatile unsigned int gpio_status_w1ts;
volatile unsigned int gpio_status_w1tc;
volatile unsigned int gpio_pin0;
volatile unsigned int gpio_pin1;
volatile unsigned int gpio_pin2;
volatile unsigned int gpio_pin3;
volatile unsigned int gpio_pin4;
volatile unsigned int gpio_pin5;
volatile unsigned int gpio_pin6;
volatile unsigned int gpio_pin7;
volatile unsigned int gpio_pin8;
volatile unsigned int gpio_pin9;
volatile unsigned int gpio_pin10;
volatile unsigned int gpio_pin11;
volatile unsigned int gpio_pin12;
volatile unsigned int gpio_pin13;
volatile unsigned int gpio_pin14;
volatile unsigned int gpio_pin15;
volatile unsigned int gpio_pin16;
volatile unsigned int gpio_pin17;
volatile unsigned int sdio_pin;
volatile unsigned int clk_req_pin;
volatile unsigned int sigma_delta;
volatile unsigned int debug_control;
volatile unsigned int debug_input_sel;
volatile unsigned int debug_out;
volatile unsigned int la_control;
volatile unsigned int la_clock;
volatile unsigned int la_status;
volatile unsigned int la_trigger_sample;
volatile unsigned int la_trigger_position;
volatile unsigned int la_pre_trigger;
volatile unsigned int la_post_trigger;
volatile unsigned int la_filter_control;
volatile unsigned int la_filter_data;
volatile unsigned int la_filter_wildcard;
volatile unsigned int la_triggera_data;
volatile unsigned int la_triggera_wildcard;
volatile unsigned int la_triggerb_data;
volatile unsigned int la_triggerb_wildcard;
volatile unsigned int la_trigger;
volatile unsigned int la_fifo;
volatile unsigned int la[2];
volatile unsigned int ant_pin;
volatile unsigned int antd_pin;
volatile unsigned int gpio_pin;
volatile unsigned int gpio_h_pin;
volatile unsigned int bt_pin;
volatile unsigned int bt_wlan_pin;
volatile unsigned int si_uart_pin;
volatile unsigned int clk32k_pin;
volatile unsigned int reset_tuple_status;
} gpio_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _GPIO_REG_H_ */

386
drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h
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@ -1,386 +0,0 @@
#ifndef _MBOX_HOST_REG_REG_H_
#define _MBOX_HOST_REG_REG_H_
#define HOST_INT_STATUS_ADDRESS 0x00000400
#define HOST_INT_STATUS_OFFSET 0x00000400
#define HOST_INT_STATUS_ERROR_MSB 7
#define HOST_INT_STATUS_ERROR_LSB 7
#define HOST_INT_STATUS_ERROR_MASK 0x00000080
#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_CPU_MSB 6
#define HOST_INT_STATUS_CPU_LSB 6
#define HOST_INT_STATUS_CPU_MASK 0x00000040
#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_DRAGON_INT_MSB 5
#define HOST_INT_STATUS_DRAGON_INT_LSB 5
#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
#define HOST_INT_STATUS_COUNTER_MSB 4
#define HOST_INT_STATUS_COUNTER_LSB 4
#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_MBOX_DATA_MSB 3
#define HOST_INT_STATUS_MBOX_DATA_LSB 0
#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ADDRESS 0x00000401
#define CPU_INT_STATUS_OFFSET 0x00000401
#define CPU_INT_STATUS_BIT_MSB 7
#define CPU_INT_STATUS_BIT_LSB 0
#define CPU_INT_STATUS_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
#define ERROR_INT_STATUS_ADDRESS 0x00000402
#define ERROR_INT_STATUS_OFFSET 0x00000402
#define ERROR_INT_STATUS_SPI_MSB 3
#define ERROR_INT_STATUS_SPI_LSB 3
#define ERROR_INT_STATUS_SPI_MASK 0x00000008
#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
#define ERROR_INT_STATUS_WAKEUP_MSB 2
#define ERROR_INT_STATUS_WAKEUP_LSB 2
#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ADDRESS 0x00000403
#define COUNTER_INT_STATUS_OFFSET 0x00000403
#define COUNTER_INT_STATUS_COUNTER_MSB 7
#define COUNTER_INT_STATUS_COUNTER_LSB 0
#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
#define MBOX_FRAME_ADDRESS 0x00000404
#define MBOX_FRAME_OFFSET 0x00000404
#define MBOX_FRAME_RX_EOM_MSB 7
#define MBOX_FRAME_RX_EOM_LSB 4
#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
#define MBOX_FRAME_RX_SOM_MSB 3
#define MBOX_FRAME_RX_SOM_LSB 0
#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
#define RX_LOOKAHEAD0_ADDRESS 0x00000408
#define RX_LOOKAHEAD0_OFFSET 0x00000408
#define RX_LOOKAHEAD0_DATA_MSB 7
#define RX_LOOKAHEAD0_DATA_LSB 0
#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
#define RX_LOOKAHEAD1_OFFSET 0x0000040c
#define RX_LOOKAHEAD1_DATA_MSB 7
#define RX_LOOKAHEAD1_DATA_LSB 0
#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
#define RX_LOOKAHEAD2_ADDRESS 0x00000410
#define RX_LOOKAHEAD2_OFFSET 0x00000410
#define RX_LOOKAHEAD2_DATA_MSB 7
#define RX_LOOKAHEAD2_DATA_LSB 0
#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
#define RX_LOOKAHEAD3_ADDRESS 0x00000414
#define RX_LOOKAHEAD3_OFFSET 0x00000414
#define RX_LOOKAHEAD3_DATA_MSB 7
#define RX_LOOKAHEAD3_DATA_LSB 0
#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
#define INT_STATUS_ENABLE_ADDRESS 0x00000418
#define INT_STATUS_ENABLE_OFFSET 0x00000418
#define INT_STATUS_ENABLE_ERROR_MSB 7
#define INT_STATUS_ENABLE_ERROR_LSB 7
#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_MSB 6
#define INT_STATUS_ENABLE_CPU_LSB 6
#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
#define INT_STATUS_ENABLE_COUNTER_MSB 4
#define INT_STATUS_ENABLE_COUNTER_LSB 4
#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define COUNT_ADDRESS 0x00000420
#define COUNT_OFFSET 0x00000420
#define COUNT_VALUE_MSB 7
#define COUNT_VALUE_LSB 0
#define COUNT_VALUE_MASK 0x000000ff
#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
#define COUNT_DEC_ADDRESS 0x00000440
#define COUNT_DEC_OFFSET 0x00000440
#define COUNT_DEC_VALUE_MSB 7
#define COUNT_DEC_VALUE_LSB 0
#define COUNT_DEC_VALUE_MASK 0x000000ff
#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
#define SCRATCH_ADDRESS 0x00000460
#define SCRATCH_OFFSET 0x00000460
#define SCRATCH_VALUE_MSB 7
#define SCRATCH_VALUE_LSB 0
#define SCRATCH_VALUE_MASK 0x000000ff
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
#define FIFO_TIMEOUT_ADDRESS 0x00000468
#define FIFO_TIMEOUT_OFFSET 0x00000468
#define FIFO_TIMEOUT_VALUE_MSB 7
#define FIFO_TIMEOUT_VALUE_LSB 0
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
#define DISABLE_SLEEP_ADDRESS 0x0000046a
#define DISABLE_SLEEP_OFFSET 0x0000046a
#define DISABLE_SLEEP_FOR_INT_MSB 1
#define DISABLE_SLEEP_FOR_INT_LSB 1
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
#define DISABLE_SLEEP_ON_MSB 0
#define DISABLE_SLEEP_ON_LSB 0
#define DISABLE_SLEEP_ON_MASK 0x00000001
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
#define LOCAL_BUS_ADDRESS 0x00000470
#define LOCAL_BUS_OFFSET 0x00000470
#define LOCAL_BUS_STATE_MSB 1
#define LOCAL_BUS_STATE_LSB 0
#define LOCAL_BUS_STATE_MASK 0x00000003
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
#define INT_WLAN_ADDRESS 0x00000472
#define INT_WLAN_OFFSET 0x00000472
#define INT_WLAN_VECTOR_MSB 7
#define INT_WLAN_VECTOR_LSB 0
#define INT_WLAN_VECTOR_MASK 0x000000ff
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
#define WINDOW_DATA_ADDRESS 0x00000474
#define WINDOW_DATA_OFFSET 0x00000474
#define WINDOW_DATA_DATA_MSB 7
#define WINDOW_DATA_DATA_LSB 0
#define WINDOW_DATA_DATA_MASK 0x000000ff
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
#define WINDOW_READ_ADDR_ADDR_MSB 7
#define WINDOW_READ_ADDR_ADDR_LSB 0
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
#define SPI_CONFIG_ADDRESS 0x00000480
#define SPI_CONFIG_OFFSET 0x00000480
#define SPI_CONFIG_SPI_RESET_MSB 4
#define SPI_CONFIG_SPI_RESET_LSB 4
#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
#define SPI_CONFIG_TEST_MODE_MSB 2
#define SPI_CONFIG_TEST_MODE_LSB 2
#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
#define SPI_CONFIG_DATA_SIZE_MSB 1
#define SPI_CONFIG_DATA_SIZE_LSB 0
#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
#define SPI_STATUS_ADDRESS 0x00000481
#define SPI_STATUS_OFFSET 0x00000481
#define SPI_STATUS_ADDR_ERR_MSB 3
#define SPI_STATUS_ADDR_ERR_LSB 3
#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
#define SPI_STATUS_RD_ERR_MSB 2
#define SPI_STATUS_RD_ERR_LSB 2
#define SPI_STATUS_RD_ERR_MASK 0x00000004
#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
#define SPI_STATUS_WR_ERR_MSB 1
#define SPI_STATUS_WR_ERR_LSB 1
#define SPI_STATUS_WR_ERR_MASK 0x00000002
#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
#define SPI_STATUS_READY_MSB 0
#define SPI_STATUS_READY_LSB 0
#define SPI_STATUS_READY_MASK 0x00000001
#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
#define CIS_WINDOW_ADDRESS 0x00000600
#define CIS_WINDOW_OFFSET 0x00000600
#define CIS_WINDOW_DATA_MSB 7
#define CIS_WINDOW_DATA_LSB 0
#define CIS_WINDOW_DATA_MASK 0x000000ff
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_host_reg_reg_s {
unsigned char pad0[1024]; /* pad to 0x400 */
volatile unsigned char host_int_status;
volatile unsigned char cpu_int_status;
volatile unsigned char error_int_status;
volatile unsigned char counter_int_status;
volatile unsigned char mbox_frame;
volatile unsigned char rx_lookahead_valid;
unsigned char pad1[2]; /* pad to 0x408 */
volatile unsigned char rx_lookahead0[4];
volatile unsigned char rx_lookahead1[4];
volatile unsigned char rx_lookahead2[4];
volatile unsigned char rx_lookahead3[4];
volatile unsigned char int_status_enable;
volatile unsigned char cpu_int_status_enable;
volatile unsigned char error_status_enable;
volatile unsigned char counter_int_status_enable;
unsigned char pad2[4]; /* pad to 0x420 */
volatile unsigned char count[8];
unsigned char pad3[24]; /* pad to 0x440 */
volatile unsigned char count_dec[32];
volatile unsigned char scratch[8];
volatile unsigned char fifo_timeout;
volatile unsigned char fifo_timeout_enable;
volatile unsigned char disable_sleep;
unsigned char pad4[5]; /* pad to 0x470 */
volatile unsigned char local_bus;
unsigned char pad5[1]; /* pad to 0x472 */
volatile unsigned char int_wlan;
unsigned char pad6[1]; /* pad to 0x474 */
volatile unsigned char window_data[4];
volatile unsigned char window_write_addr[4];
volatile unsigned char window_read_addr[4];
volatile unsigned char spi_config;
volatile unsigned char spi_status;
volatile unsigned char non_assoc_sleep_en;
unsigned char pad7[381]; /* pad to 0x600 */
volatile unsigned char cis_window[512];
} mbox_host_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_HOST_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h
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@ -1,481 +0,0 @@
#ifndef _MBOX_REG_REG_H_
#define _MBOX_REG_REG_H_
#define MBOX_FIFO_ADDRESS 0x00000000
#define MBOX_FIFO_OFFSET 0x00000000
#define MBOX_FIFO_DATA_MSB 19
#define MBOX_FIFO_DATA_LSB 0
#define MBOX_FIFO_DATA_MASK 0x000fffff
#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
#define MBOX_FIFO_STATUS_ADDRESS 0x00000010
#define MBOX_FIFO_STATUS_OFFSET 0x00000010
#define MBOX_FIFO_STATUS_EMPTY_MSB 19
#define MBOX_FIFO_STATUS_EMPTY_LSB 16
#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
#define MBOX_FIFO_STATUS_FULL_MSB 15
#define MBOX_FIFO_STATUS_FULL_LSB 12
#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
#define MBOX_DMA_POLICY_ADDRESS 0x00000014
#define MBOX_DMA_POLICY_OFFSET 0x00000014
#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX0_DMA_RX_CONTROL_START_MSB 1
#define MBOX0_DMA_RX_CONTROL_START_LSB 1
#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX0_DMA_TX_CONTROL_START_MSB 1
#define MBOX0_DMA_TX_CONTROL_START_LSB 1
#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX1_DMA_RX_CONTROL_START_MSB 1
#define MBOX1_DMA_RX_CONTROL_START_LSB 1
#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX1_DMA_TX_CONTROL_START_MSB 1
#define MBOX1_DMA_TX_CONTROL_START_LSB 1
#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX2_DMA_RX_CONTROL_START_MSB 1
#define MBOX2_DMA_RX_CONTROL_START_LSB 1
#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX2_DMA_TX_CONTROL_START_MSB 1
#define MBOX2_DMA_TX_CONTROL_START_LSB 1
#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX3_DMA_RX_CONTROL_START_MSB 1
#define MBOX3_DMA_RX_CONTROL_START_LSB 1
#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX3_DMA_TX_CONTROL_START_MSB 1
#define MBOX3_DMA_TX_CONTROL_START_LSB 1
#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
#define MBOX_INT_STATUS_ADDRESS 0x00000058
#define MBOX_INT_STATUS_OFFSET 0x00000058
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define MBOX_INT_STATUS_HOST_MSB 7
#define MBOX_INT_STATUS_HOST_LSB 0
#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
#define MBOX_INT_ENABLE_ADDRESS 0x0000005c
#define MBOX_INT_ENABLE_OFFSET 0x0000005c
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define MBOX_INT_ENABLE_HOST_MSB 7
#define MBOX_INT_ENABLE_HOST_LSB 0
#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
#define INT_HOST_ADDRESS 0x00000060
#define INT_HOST_OFFSET 0x00000060
#define INT_HOST_VECTOR_MSB 7
#define INT_HOST_VECTOR_LSB 0
#define INT_HOST_VECTOR_MASK 0x000000ff
#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
#define LOCAL_COUNT_ADDRESS 0x00000080
#define LOCAL_COUNT_OFFSET 0x00000080
#define LOCAL_COUNT_VALUE_MSB 7
#define LOCAL_COUNT_VALUE_LSB 0
#define LOCAL_COUNT_VALUE_MASK 0x000000ff
#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
#define COUNT_INC_ADDRESS 0x000000a0
#define COUNT_INC_OFFSET 0x000000a0
#define COUNT_INC_VALUE_MSB 7
#define COUNT_INC_VALUE_LSB 0
#define COUNT_INC_VALUE_MASK 0x000000ff
#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
#define LOCAL_SCRATCH_ADDRESS 0x000000c0
#define LOCAL_SCRATCH_OFFSET 0x000000c0
#define LOCAL_SCRATCH_VALUE_MSB 7
#define LOCAL_SCRATCH_VALUE_LSB 0
#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
#define USE_LOCAL_BUS_ADDRESS 0x000000e0
#define USE_LOCAL_BUS_OFFSET 0x000000e0
#define USE_LOCAL_BUS_PIN_INIT_MSB 0
#define USE_LOCAL_BUS_PIN_INIT_LSB 0
#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
#define SDIO_CONFIG_ADDRESS 0x000000e4
#define SDIO_CONFIG_OFFSET 0x000000e4
#define SDIO_CONFIG_CCCR_IOR1_MSB 0
#define SDIO_CONFIG_CCCR_IOR1_LSB 0
#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
#define MBOX_DEBUG_ADDRESS 0x000000e8
#define MBOX_DEBUG_OFFSET 0x000000e8
#define MBOX_DEBUG_SEL_MSB 2
#define MBOX_DEBUG_SEL_LSB 0
#define MBOX_DEBUG_SEL_MASK 0x00000007
#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
#define MBOX_FIFO_RESET_ADDRESS 0x000000ec
#define MBOX_FIFO_RESET_OFFSET 0x000000ec
#define MBOX_FIFO_RESET_INIT_MSB 0
#define MBOX_FIFO_RESET_INIT_LSB 0
#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
#define MBOX_TXFIFO_POP_OFFSET 0x000000f0
#define MBOX_TXFIFO_POP_DATA_MSB 0
#define MBOX_TXFIFO_POP_DATA_LSB 0
#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
#define MBOX_RXFIFO_POP_ADDRESS 0x00000100
#define MBOX_RXFIFO_POP_OFFSET 0x00000100
#define MBOX_RXFIFO_POP_DATA_MSB 0
#define MBOX_RXFIFO_POP_DATA_LSB 0
#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
#define SDIO_DEBUG_ADDRESS 0x00000110
#define SDIO_DEBUG_OFFSET 0x00000110
#define SDIO_DEBUG_SEL_MSB 3
#define SDIO_DEBUG_SEL_LSB 0
#define SDIO_DEBUG_SEL_MASK 0x0000000f
#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
#define HOST_IF_WINDOW_ADDRESS 0x00002000
#define HOST_IF_WINDOW_OFFSET 0x00002000
#define HOST_IF_WINDOW_DATA_MSB 7
#define HOST_IF_WINDOW_DATA_LSB 0
#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_reg_reg_s {
volatile unsigned int mbox_fifo[4];
volatile unsigned int mbox_fifo_status;
volatile unsigned int mbox_dma_policy;
volatile unsigned int mbox0_dma_rx_descriptor_base;
volatile unsigned int mbox0_dma_rx_control;
volatile unsigned int mbox0_dma_tx_descriptor_base;
volatile unsigned int mbox0_dma_tx_control;
volatile unsigned int mbox1_dma_rx_descriptor_base;
volatile unsigned int mbox1_dma_rx_control;
volatile unsigned int mbox1_dma_tx_descriptor_base;
volatile unsigned int mbox1_dma_tx_control;
volatile unsigned int mbox2_dma_rx_descriptor_base;
volatile unsigned int mbox2_dma_rx_control;
volatile unsigned int mbox2_dma_tx_descriptor_base;
volatile unsigned int mbox2_dma_tx_control;
volatile unsigned int mbox3_dma_rx_descriptor_base;
volatile unsigned int mbox3_dma_rx_control;
volatile unsigned int mbox3_dma_tx_descriptor_base;
volatile unsigned int mbox3_dma_tx_control;
volatile unsigned int mbox_int_status;
volatile unsigned int mbox_int_enable;
volatile unsigned int int_host;
unsigned char pad0[28]; /* pad to 0x80 */
volatile unsigned int local_count[8];
volatile unsigned int count_inc[8];
volatile unsigned int local_scratch[8];
volatile unsigned int use_local_bus;
volatile unsigned int sdio_config;
volatile unsigned int mbox_debug;
volatile unsigned int mbox_fifo_reset;
volatile unsigned int mbox_txfifo_pop[4];
volatile unsigned int mbox_rxfifo_pop[4];
volatile unsigned int sdio_debug;
unsigned char pad1[7916]; /* pad to 0x2000 */
volatile unsigned int host_if_window[2048];
} mbox_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h
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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h
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@ -1,186 +0,0 @@
#ifndef _SI_REG_REG_H_
#define _SI_REG_REG_H_
#define SI_CONFIG_ADDRESS 0x00000000
#define SI_CONFIG_OFFSET 0x00000000
#define SI_CONFIG_ERR_INT_MSB 19
#define SI_CONFIG_ERR_INT_LSB 19
#define SI_CONFIG_ERR_INT_MASK 0x00080000
#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_MSB 16
#define SI_CONFIG_I2C_LSB 16
#define SI_CONFIG_I2C_MASK 0x00010000
#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_MSB 7
#define SI_CONFIG_POS_SAMPLE_LSB 7
#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_POS_DRIVE_MSB 6
#define SI_CONFIG_POS_DRIVE_LSB 6
#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
#define SI_CONFIG_INACTIVE_DATA_MSB 5
#define SI_CONFIG_INACTIVE_DATA_LSB 5
#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_INACTIVE_CLK_MSB 4
#define SI_CONFIG_INACTIVE_CLK_LSB 4
#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_DIVIDER_MSB 3
#define SI_CONFIG_DIVIDER_LSB 0
#define SI_CONFIG_DIVIDER_MASK 0x0000000f
#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_ADDRESS 0x00000004
#define SI_CS_OFFSET 0x00000004
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
#define SI_CS_DONE_ERR_MSB 10
#define SI_CS_DONE_ERR_LSB 10
#define SI_CS_DONE_ERR_MASK 0x00000400
#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MSB 9
#define SI_CS_DONE_INT_LSB 9
#define SI_CS_DONE_INT_MASK 0x00000200
#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
#define SI_CS_START_MSB 8
#define SI_CS_START_LSB 8
#define SI_CS_START_MASK 0x00000100
#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_MSB 7
#define SI_CS_RX_CNT_LSB 4
#define SI_CS_RX_CNT_MASK 0x000000f0
#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_MSB 3
#define SI_CS_TX_CNT_LSB 0
#define SI_CS_TX_CNT_MASK 0x0000000f
#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define SI_TX_DATA0_ADDRESS 0x00000008
#define SI_TX_DATA0_OFFSET 0x00000008
#define SI_TX_DATA0_DATA3_MSB 31
#define SI_TX_DATA0_DATA3_LSB 24
#define SI_TX_DATA0_DATA3_MASK 0xff000000
#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
#define SI_TX_DATA0_DATA2_MSB 23
#define SI_TX_DATA0_DATA2_LSB 16
#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
#define SI_TX_DATA0_DATA1_MSB 15
#define SI_TX_DATA0_DATA1_LSB 8
#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
#define SI_TX_DATA0_DATA0_MSB 7
#define SI_TX_DATA0_DATA0_LSB 0
#define SI_TX_DATA0_DATA0_MASK 0x000000ff
#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
#define SI_TX_DATA1_ADDRESS 0x0000000c
#define SI_TX_DATA1_OFFSET 0x0000000c
#define SI_TX_DATA1_DATA7_MSB 31
#define SI_TX_DATA1_DATA7_LSB 24
#define SI_TX_DATA1_DATA7_MASK 0xff000000
#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
#define SI_TX_DATA1_DATA6_MSB 23
#define SI_TX_DATA1_DATA6_LSB 16
#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
#define SI_TX_DATA1_DATA5_MSB 15
#define SI_TX_DATA1_DATA5_LSB 8
#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
#define SI_TX_DATA1_DATA4_MSB 7
#define SI_TX_DATA1_DATA4_LSB 0
#define SI_TX_DATA1_DATA4_MASK 0x000000ff
#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
#define SI_RX_DATA0_ADDRESS 0x00000010
#define SI_RX_DATA0_OFFSET 0x00000010
#define SI_RX_DATA0_DATA3_MSB 31
#define SI_RX_DATA0_DATA3_LSB 24
#define SI_RX_DATA0_DATA3_MASK 0xff000000
#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
#define SI_RX_DATA0_DATA2_MSB 23
#define SI_RX_DATA0_DATA2_LSB 16
#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
#define SI_RX_DATA0_DATA1_MSB 15
#define SI_RX_DATA0_DATA1_LSB 8
#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
#define SI_RX_DATA0_DATA0_MSB 7
#define SI_RX_DATA0_DATA0_LSB 0
#define SI_RX_DATA0_DATA0_MASK 0x000000ff
#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
#define SI_RX_DATA1_ADDRESS 0x00000014
#define SI_RX_DATA1_OFFSET 0x00000014
#define SI_RX_DATA1_DATA7_MSB 31
#define SI_RX_DATA1_DATA7_LSB 24
#define SI_RX_DATA1_DATA7_MASK 0xff000000
#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
#define SI_RX_DATA1_DATA6_MSB 23
#define SI_RX_DATA1_DATA6_LSB 16
#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
#define SI_RX_DATA1_DATA5_MSB 15
#define SI_RX_DATA1_DATA5_LSB 8
#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
#define SI_RX_DATA1_DATA4_MSB 7
#define SI_RX_DATA1_DATA4_LSB 0
#define SI_RX_DATA1_DATA4_MASK 0x000000ff
#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
#ifndef __ASSEMBLER__
typedef struct si_reg_reg_s {
volatile unsigned int si_config;
volatile unsigned int si_cs;
volatile unsigned int si_tx_data0;
volatile unsigned int si_tx_data1;
volatile unsigned int si_rx_data0;
volatile unsigned int si_rx_data1;
} si_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _SI_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h
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@ -1,327 +0,0 @@
#ifndef _UART_REG_REG_H_
#define _UART_REG_REG_H_
#define RBR_ADDRESS 0x00000000
#define RBR_OFFSET 0x00000000
#define RBR_RBR_MSB 7
#define RBR_RBR_LSB 0
#define RBR_RBR_MASK 0x000000ff
#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
#define THR_ADDRESS 0x00000000
#define THR_OFFSET 0x00000000
#define THR_THR_MSB 7
#define THR_THR_LSB 0
#define THR_THR_MASK 0x000000ff
#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
#define DLL_ADDRESS 0x00000000
#define DLL_OFFSET 0x00000000
#define DLL_DLL_MSB 7
#define DLL_DLL_LSB 0
#define DLL_DLL_MASK 0x000000ff
#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
#define DLH_ADDRESS 0x00000004
#define DLH_OFFSET 0x00000004
#define DLH_DLH_MSB 7
#define DLH_DLH_LSB 0
#define DLH_DLH_MASK 0x000000ff
#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
#define IER_ADDRESS 0x00000004
#define IER_OFFSET 0x00000004
#define IER_EDDSI_MSB 3
#define IER_EDDSI_LSB 3
#define IER_EDDSI_MASK 0x00000008
#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
#define IER_ELSI_MSB 2
#define IER_ELSI_LSB 2
#define IER_ELSI_MASK 0x00000004
#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
#define IER_ETBEI_MSB 1
#define IER_ETBEI_LSB 1
#define IER_ETBEI_MASK 0x00000002
#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
#define IER_ERBFI_MSB 0
#define IER_ERBFI_LSB 0
#define IER_ERBFI_MASK 0x00000001
#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
#define IIR_ADDRESS 0x00000008
#define IIR_OFFSET 0x00000008
#define IIR_FIFO_STATUS_MSB 7
#define IIR_FIFO_STATUS_LSB 6
#define IIR_FIFO_STATUS_MASK 0x000000c0
#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
#define IIR_IID_MSB 3
#define IIR_IID_LSB 0
#define IIR_IID_MASK 0x0000000f
#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
#define FCR_ADDRESS 0x00000008
#define FCR_OFFSET 0x00000008
#define FCR_RCVR_TRIG_MSB 7
#define FCR_RCVR_TRIG_LSB 6
#define FCR_RCVR_TRIG_MASK 0x000000c0
#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
#define FCR_DMA_MODE_MSB 3
#define FCR_DMA_MODE_LSB 3
#define FCR_DMA_MODE_MASK 0x00000008
#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
#define FCR_XMIT_FIFO_RST_MSB 2
#define FCR_XMIT_FIFO_RST_LSB 2
#define FCR_XMIT_FIFO_RST_MASK 0x00000004
#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
#define FCR_RCVR_FIFO_RST_MSB 1
#define FCR_RCVR_FIFO_RST_LSB 1
#define FCR_RCVR_FIFO_RST_MASK 0x00000002
#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
#define FCR_FIFO_EN_MSB 0
#define FCR_FIFO_EN_LSB 0
#define FCR_FIFO_EN_MASK 0x00000001
#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
#define LCR_ADDRESS 0x0000000c
#define LCR_OFFSET 0x0000000c
#define LCR_DLAB_MSB 7
#define LCR_DLAB_LSB 7
#define LCR_DLAB_MASK 0x00000080
#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
#define LCR_BREAK_MSB 6
#define LCR_BREAK_LSB 6
#define LCR_BREAK_MASK 0x00000040
#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
#define LCR_EPS_MSB 4
#define LCR_EPS_LSB 4
#define LCR_EPS_MASK 0x00000010
#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
#define LCR_PEN_MSB 3
#define LCR_PEN_LSB 3
#define LCR_PEN_MASK 0x00000008
#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
#define LCR_STOP_MSB 2
#define LCR_STOP_LSB 2
#define LCR_STOP_MASK 0x00000004
#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
#define LCR_CLS_MSB 1
#define LCR_CLS_LSB 0
#define LCR_CLS_MASK 0x00000003
#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
#define MCR_ADDRESS 0x00000010
#define MCR_OFFSET 0x00000010
#define MCR_LOOPBACK_MSB 5
#define MCR_LOOPBACK_LSB 5
#define MCR_LOOPBACK_MASK 0x00000020
#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
#define MCR_OUT2_MSB 3
#define MCR_OUT2_LSB 3
#define MCR_OUT2_MASK 0x00000008
#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
#define MCR_OUT1_MSB 2
#define MCR_OUT1_LSB 2
#define MCR_OUT1_MASK 0x00000004
#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
#define MCR_RTS_MSB 1
#define MCR_RTS_LSB 1
#define MCR_RTS_MASK 0x00000002
#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
#define MCR_DTR_MSB 0
#define MCR_DTR_LSB 0
#define MCR_DTR_MASK 0x00000001
#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
#define LSR_ADDRESS 0x00000014
#define LSR_OFFSET 0x00000014
#define LSR_FERR_MSB 7
#define LSR_FERR_LSB 7
#define LSR_FERR_MASK 0x00000080
#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
#define LSR_TEMT_MSB 6
#define LSR_TEMT_LSB 6
#define LSR_TEMT_MASK 0x00000040
#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
#define LSR_THRE_MSB 5
#define LSR_THRE_LSB 5
#define LSR_THRE_MASK 0x00000020
#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
#define LSR_BI_MSB 4
#define LSR_BI_LSB 4
#define LSR_BI_MASK 0x00000010
#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
#define LSR_FE_MSB 3
#define LSR_FE_LSB 3
#define LSR_FE_MASK 0x00000008
#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
#define LSR_PE_MSB 2
#define LSR_PE_LSB 2
#define LSR_PE_MASK 0x00000004
#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
#define LSR_OE_MSB 1
#define LSR_OE_LSB 1
#define LSR_OE_MASK 0x00000002
#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
#define LSR_DR_MSB 0
#define LSR_DR_LSB 0
#define LSR_DR_MASK 0x00000001
#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
#define MSR_ADDRESS 0x00000018
#define MSR_OFFSET 0x00000018
#define MSR_DCD_MSB 7
#define MSR_DCD_LSB 7
#define MSR_DCD_MASK 0x00000080
#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
#define MSR_RI_MSB 6
#define MSR_RI_LSB 6
#define MSR_RI_MASK 0x00000040
#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
#define MSR_DSR_MSB 5
#define MSR_DSR_LSB 5
#define MSR_DSR_MASK 0x00000020
#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
#define MSR_CTS_MSB 4
#define MSR_CTS_LSB 4
#define MSR_CTS_MASK 0x00000010
#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
#define MSR_DDCD_MSB 3
#define MSR_DDCD_LSB 3
#define MSR_DDCD_MASK 0x00000008
#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
#define MSR_TERI_MSB 2
#define MSR_TERI_LSB 2
#define MSR_TERI_MASK 0x00000004
#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
#define MSR_DDSR_MSB 1
#define MSR_DDSR_LSB 1
#define MSR_DDSR_MASK 0x00000002
#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
#define MSR_DCTS_MSB 0
#define MSR_DCTS_LSB 0
#define MSR_DCTS_MASK 0x00000001
#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
#define SCR_ADDRESS 0x0000001c
#define SCR_OFFSET 0x0000001c
#define SCR_SCR_MSB 7
#define SCR_SCR_LSB 0
#define SCR_SCR_MASK 0x000000ff
#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
#define SRBR_ADDRESS 0x00000020
#define SRBR_OFFSET 0x00000020
#define SRBR_SRBR_MSB 7
#define SRBR_SRBR_LSB 0
#define SRBR_SRBR_MASK 0x000000ff
#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
#define SIIR_ADDRESS 0x00000028
#define SIIR_OFFSET 0x00000028
#define SIIR_SIIR_MSB 7
#define SIIR_SIIR_LSB 0
#define SIIR_SIIR_MASK 0x000000ff
#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
#define MWR_ADDRESS 0x0000002c
#define MWR_OFFSET 0x0000002c
#define MWR_MWR_MSB 31
#define MWR_MWR_LSB 0
#define MWR_MWR_MASK 0xffffffff
#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
#define SLSR_ADDRESS 0x00000034
#define SLSR_OFFSET 0x00000034
#define SLSR_SLSR_MSB 7
#define SLSR_SLSR_LSB 0
#define SLSR_SLSR_MASK 0x000000ff
#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
#define SMSR_ADDRESS 0x00000038
#define SMSR_OFFSET 0x00000038
#define SMSR_SMSR_MSB 7
#define SMSR_SMSR_LSB 0
#define SMSR_SMSR_MASK 0x000000ff
#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
#define MRR_ADDRESS 0x0000003c
#define MRR_OFFSET 0x0000003c
#define MRR_MRR_MSB 31
#define MRR_MRR_LSB 0
#define MRR_MRR_MASK 0xffffffff
#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
#ifndef __ASSEMBLER__
typedef struct uart_reg_reg_s {
volatile unsigned int rbr;
volatile unsigned int dlh;
volatile unsigned int iir;
volatile unsigned int lcr;
volatile unsigned int mcr;
volatile unsigned int lsr;
volatile unsigned int msr;
volatile unsigned int scr;
volatile unsigned int srbr;
unsigned char pad0[4]; /* pad to 0x28 */
volatile unsigned int siir;
volatile unsigned int mwr;
unsigned char pad1[4]; /* pad to 0x34 */
volatile unsigned int slsr;
volatile unsigned int smsr;
volatile unsigned int mrr;
} uart_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UART_REG_H_ */

76
drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h
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@ -1,76 +0,0 @@
#ifndef _VMC_REG_REG_H_
#define _VMC_REG_REG_H_
#define MC_TCAM_VALID_ADDRESS 0x00000000
#define MC_TCAM_VALID_OFFSET 0x00000000
#define MC_TCAM_VALID_BIT_MSB 0
#define MC_TCAM_VALID_BIT_LSB 0
#define MC_TCAM_VALID_BIT_MASK 0x00000001
#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
#define MC_TCAM_MASK_ADDRESS 0x00000080
#define MC_TCAM_MASK_OFFSET 0x00000080
#define MC_TCAM_MASK_SIZE_MSB 2
#define MC_TCAM_MASK_SIZE_LSB 0
#define MC_TCAM_MASK_SIZE_MASK 0x00000007
#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
#define MC_TCAM_COMPARE_ADDRESS 0x00000100
#define MC_TCAM_COMPARE_OFFSET 0x00000100
#define MC_TCAM_COMPARE_KEY_MSB 21
#define MC_TCAM_COMPARE_KEY_LSB 5
#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
#define MC_TCAM_TARGET_ADDRESS 0x00000180
#define MC_TCAM_TARGET_OFFSET 0x00000180
#define MC_TCAM_TARGET_ADDR_MSB 21
#define MC_TCAM_TARGET_ADDR_LSB 5
#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
#define ADDR_ERROR_CONTROL_OFFSET 0x00000200
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
#define ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
#define ADDR_ERROR_STATUS_ADDRESS 0x00000204
#define ADDR_ERROR_STATUS_OFFSET 0x00000204
#define ADDR_ERROR_STATUS_WRITE_MSB 25
#define ADDR_ERROR_STATUS_WRITE_LSB 25
#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
#define ADDR_ERROR_STATUS_ADDRESS_MSB 24
#define ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
#ifndef __ASSEMBLER__
typedef struct vmc_reg_reg_s {
volatile unsigned int mc_tcam_valid[32];
volatile unsigned int mc_tcam_mask[32];
volatile unsigned int mc_tcam_compare[32];
volatile unsigned int mc_tcam_target[32];
volatile unsigned int addr_error_control;
volatile unsigned int addr_error_status;
} vmc_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _VMC_REG_H_ */

3291
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h
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3674
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
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37
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h
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@ -1,37 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "analog_intf_athr_wlan_reg.h"
#ifndef BT_HEADERS
#endif
#endif

8
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
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@ -21,11 +21,8 @@
//===================================================================
#ifdef WLAN_HEADERS
#include "apb_athr_wlan_map.h"
#ifndef BT_HEADERS
#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
@ -40,9 +37,4 @@
#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
#endif
#endif

7076
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h
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108
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000014
#define RD_STROBE_PW_REG_OFFSET 0x00000014
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x00000018
#define PG_STROBE_PW_REG_OFFSET 0x00000018
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define EFUSE_INTF_ADDRESS 0x00000800
#define EFUSE_INTF_OFFSET 0x00000800
#define EFUSE_INTF_R_MSB 31
#define EFUSE_INTF_R_LSB 0
#define EFUSE_INTF_R_MASK 0xffffffff
#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
unsigned char pad0[2020]; /* pad to 0x800 */
volatile unsigned int efuse_intf[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */

1253
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h
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605
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h
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// ------------------------------------------------------------------
// Copyright (c) 2002-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
/*****************************************************************************/
/* AR6003 WLAN MAC DMA register definitions */
/*****************************************************************************/
#ifndef _AR6000_DMAREG_H_
#define _AR6000_DMAREG_H_
/*
* Definitions for the Atheros AR6003 chipset.
*/
/* DMA Control and Interrupt Registers */
#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */
#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */
#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */
#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */
#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */
#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */
#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */
#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */
#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */
#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */
#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */
#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */
#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */
#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */
#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF
#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */
#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */
#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */
#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */
#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */
#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */
#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */
#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */
#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
#define MAC_DMA_FTRIG_64B 0x00000010 /* default */
#define MAC_DMA_FTRIG_128B 0x00000020
#define MAC_DMA_FTRIG_192B 0x00000030
#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */
#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */
#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */
#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */
#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */
#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */
#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */
#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */
#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */
#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */
#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */
#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
/* for which frame completions will cause */
/* a reset of the no frame xmit'd timeout */
#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */
#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */
#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */
#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */
#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */
#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */
/*
* Interrupt Status Registers
*
* Only the bits in the ISR_P register and the IMR_P registers
* control whether the MAC's INTA# output is asserted. The bits in
* the secondary interrupt status/mask registers control what bits
* are set in the primary interrupt status register; however the
* IMR_S* registers DO NOT determine whether INTA# is asserted.
* That is INTA# is asserted only when the logical AND of ISR_P
* and IMR_P is non-zero. The secondary interrupt mask/status
* registers affect what bits are set in ISR_P but they do not
* directly affect whether INTA# is asserted.
*/
#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */
#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */
#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */
#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */
#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */
#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */
#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */
#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_ISR_S2_CST_MASK 0x00400000
#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000
#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */
#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */
#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */
#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */
/*
* Interrupt Mask Registers
*
* Only the bits in the IMR control whether the MAC's INTA#
* output will be asserted. The bits in the secondary interrupt
* mask registers control what bits get set in the primary
* interrupt status register; however the IMR_S* registers
* DO NOT determine whether INTA# is asserted.
*/
#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */
#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */
#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */
#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */
#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/
#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */
#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */
#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */
#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0
#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_IMR_S2_CST_MASK 0x00400000
#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000
#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */
#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16
#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */
#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */
#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i))
#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */
/* Shadow copies with read-and-clear access */
#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */
#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */
#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */
#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */
#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */
#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */
#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */
#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */
/* QCU registers */
#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */
#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */
#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */
#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */
#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */
#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */
#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */
#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */
#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */
#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */
#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */
#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */
#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */
#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */
#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */
#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */
#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */
#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */
#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */
#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */
#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */
#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */
#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */
#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */
#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */
#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr
(empty q) */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr
(empty beacon q) */
#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */
#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */
#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */
#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */
#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */
#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */
#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */
#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */
/* DCU registers */
#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */
#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */
#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */
#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */
#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */
#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */
#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */
#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */
#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */
#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */
#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */
#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */
#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */
#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0
#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */
#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10
#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */
#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20
/*
* Note: even though this field is 8 bits wide the
* maximum supported AIFS value is 0xFc. Setting the AIFS value
* to 0xFd 0xFe, or 0xFf will not work correctly and will cause
* the DCU to hang.
*/
#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */
#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */
#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */
#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */
#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */
#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */
#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */
#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */
#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */
#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */
#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */
#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14
#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */
#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */
#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */
#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */
#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */
#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */
#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */
#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */
#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */
#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */
#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */
#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */
#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */
#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */
#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */
#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */
#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000
#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_D0_EOL_ADDRESS 0x00001180
#define MAC_DMA_D1_EOL_ADDRESS 0x00001184
#define MAC_DMA_D2_EOL_ADDRESS 0x00001188
#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C
#define MAC_DMA_D4_EOL_ADDRESS 0x00001190
#define MAC_DMA_D5_EOL_ADDRESS 0x00001194
#define MAC_DMA_D6_EOL_ADDRESS 0x00001198
#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C
#define MAC_DMA_D8_EOL_ADDRESS 0x00001200
#define MAC_DMA_D9_EOL_ADDRESS 0x00001204
#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */
#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0
#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series
station RTS/data failure
count reset policy */
#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series
CW reset policy */
#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */
#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */
#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */
#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor
setting */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision
handling policy */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */
#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */
#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */
#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */
#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */
#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */
#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */
#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */
#endif /* _AR6000_DMMAEG_H_ */

3065
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h
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File diff suppressed because it is too large Load Diff

13
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
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@ -21,17 +21,4 @@
//===================================================================
#ifdef WLAN_HEADERS
#include "mbox_wlan_host_reg.h"
#ifndef BT_HEADERS
#endif
#endif

8
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
View File

@ -21,11 +21,8 @@
//===================================================================
#ifdef WLAN_HEADERS
#include "mbox_wlan_reg.h"
#ifndef BT_HEADERS
#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
@ -552,9 +549,4 @@
#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
#endif
#endif

51
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
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@ -468,55 +468,4 @@
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_host_reg_reg_s {
unsigned char pad0[1024]; /* pad to 0x400 */
volatile unsigned char host_int_status;
volatile unsigned char cpu_int_status;
volatile unsigned char error_int_status;
volatile unsigned char counter_int_status;
volatile unsigned char mbox_frame;
volatile unsigned char rx_lookahead_valid;
volatile unsigned char host_int_status2;
volatile unsigned char gmbox_rx_avail;
volatile unsigned char rx_lookahead0[4];
volatile unsigned char rx_lookahead1[4];
volatile unsigned char rx_lookahead2[4];
volatile unsigned char rx_lookahead3[4];
volatile unsigned char int_status_enable;
volatile unsigned char cpu_int_status_enable;
volatile unsigned char error_status_enable;
volatile unsigned char counter_int_status_enable;
unsigned char pad1[4]; /* pad to 0x420 */
volatile unsigned char count[8];
unsigned char pad2[24]; /* pad to 0x440 */
volatile unsigned char count_dec[32];
volatile unsigned char scratch[8];
volatile unsigned char fifo_timeout;
volatile unsigned char fifo_timeout_enable;
volatile unsigned char disable_sleep;
unsigned char pad3[5]; /* pad to 0x470 */
volatile unsigned char local_bus;
unsigned char pad4[1]; /* pad to 0x472 */
volatile unsigned char int_wlan;
unsigned char pad5[1]; /* pad to 0x474 */
volatile unsigned char window_data[4];
volatile unsigned char window_write_addr[4];
volatile unsigned char window_read_addr[4];
volatile unsigned char host_ctrl_spi_config;
volatile unsigned char host_ctrl_spi_status;
volatile unsigned char non_assoc_sleep_en;
volatile unsigned char cpu_dbg_sel;
volatile unsigned char cpu_dbg[4];
volatile unsigned char int_status2_enable;
unsigned char pad6[7]; /* pad to 0x490 */
volatile unsigned char gmbox_rx_lookahead[8];
volatile unsigned char gmbox_rx_lookahead_mux;
unsigned char pad7[359]; /* pad to 0x600 */
volatile unsigned char cis_window[512];
} mbox_wlan_host_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_HOST_REG_H_ */

49
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
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@ -586,53 +586,4 @@
#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_reg_reg_s {
volatile unsigned int wlan_mbox_fifo[4];
volatile unsigned int wlan_mbox_fifo_status;
volatile unsigned int wlan_mbox_dma_policy;
volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_rx_control;
volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_tx_control;
volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_rx_control;
volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_tx_control;
volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_rx_control;
volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_tx_control;
volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_rx_control;
volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_tx_control;
volatile unsigned int wlan_mbox_int_status;
volatile unsigned int wlan_mbox_int_enable;
volatile unsigned int wlan_int_host;
unsigned char pad0[28]; /* pad to 0x80 */
volatile unsigned int wlan_local_count[8];
volatile unsigned int wlan_count_inc[8];
volatile unsigned int wlan_local_scratch[8];
volatile unsigned int wlan_use_local_bus;
volatile unsigned int wlan_sdio_config;
volatile unsigned int wlan_mbox_debug;
volatile unsigned int wlan_mbox_fifo_reset;
volatile unsigned int wlan_mbox_txfifo_pop[4];
volatile unsigned int wlan_mbox_rxfifo_pop[4];
volatile unsigned int wlan_sdio_debug;
volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_rx_control;
volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_tx_control;
volatile unsigned int wlan_gmbox_int_status;
volatile unsigned int wlan_gmbox_int_enable;
unsigned char pad1[7892]; /* pad to 0x2000 */
volatile unsigned int wlan_host_if_window[2048];
} mbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_REG_H_ */

564
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h
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@ -1,564 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _RDMA_REG_REG_H_
#define _RDMA_REG_REG_H_
#define DMA_CONFIG_ADDRESS 0x00000000
#define DMA_CONFIG_OFFSET 0x00000000
#define DMA_CONFIG_WLBB_PWD_EN_MSB 4
#define DMA_CONFIG_WLBB_PWD_EN_LSB 4
#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010
#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008
#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
#define DMA_CONFIG_ENABLE_RETENTION_MSB 2
#define DMA_CONFIG_ENABLE_RETENTION_LSB 2
#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004
#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
#define DMA_CONFIG_RTC_PRIORITY_MSB 1
#define DMA_CONFIG_RTC_PRIORITY_LSB 1
#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002
#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
#define DMA_CONFIG_DMA_TYPE_MSB 0
#define DMA_CONFIG_DMA_TYPE_LSB 0
#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001
#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
#define DMA_CONTROL_ADDRESS 0x00000004
#define DMA_CONTROL_OFFSET 0x00000004
#define DMA_CONTROL_START_MSB 1
#define DMA_CONTROL_START_LSB 1
#define DMA_CONTROL_START_MASK 0x00000002
#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
#define DMA_CONTROL_STOP_MSB 0
#define DMA_CONTROL_STOP_LSB 0
#define DMA_CONTROL_STOP_MASK 0x00000001
#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
#define DMA_SRC_ADDRESS 0x00000008
#define DMA_SRC_OFFSET 0x00000008
#define DMA_SRC_ADDR_MSB 31
#define DMA_SRC_ADDR_LSB 2
#define DMA_SRC_ADDR_MASK 0xfffffffc
#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
#define DMA_DEST_ADDRESS 0x0000000c
#define DMA_DEST_OFFSET 0x0000000c
#define DMA_DEST_ADDR_MSB 31
#define DMA_DEST_ADDR_LSB 2
#define DMA_DEST_ADDR_MASK 0xfffffffc
#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
#define DMA_LENGTH_ADDRESS 0x00000010
#define DMA_LENGTH_OFFSET 0x00000010
#define DMA_LENGTH_WORDS_MSB 11
#define DMA_LENGTH_WORDS_LSB 0
#define DMA_LENGTH_WORDS_MASK 0x00000fff
#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
#define VMC_BASE_ADDRESS 0x00000014
#define VMC_BASE_OFFSET 0x00000014
#define VMC_BASE_ADDR_MSB 31
#define VMC_BASE_ADDR_LSB 2
#define VMC_BASE_ADDR_MASK 0xfffffffc
#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
#define INDIRECT_REG_ADDRESS 0x00000018
#define INDIRECT_REG_OFFSET 0x00000018
#define INDIRECT_REG_ID_MSB 31
#define INDIRECT_REG_ID_LSB 2
#define INDIRECT_REG_ID_MASK 0xfffffffc
#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
#define INDIRECT_RETURN_ADDRESS 0x0000001c
#define INDIRECT_RETURN_OFFSET 0x0000001c
#define INDIRECT_RETURN_ADDR_MSB 31
#define INDIRECT_RETURN_ADDR_LSB 2
#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc
#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
#define RDMA_REGION_0__ADDRESS 0x00000020
#define RDMA_REGION_0__OFFSET 0x00000020
#define RDMA_REGION_0__ADDR_MSB 31
#define RDMA_REGION_0__ADDR_LSB 13
#define RDMA_REGION_0__ADDR_MASK 0xffffe000
#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
#define RDMA_REGION_0__LENGTH_MSB 12
#define RDMA_REGION_0__LENGTH_LSB 2
#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
#define RDMA_REGION_0__INDI_MSB 1
#define RDMA_REGION_0__INDI_LSB 1
#define RDMA_REGION_0__INDI_MASK 0x00000002
#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
#define RDMA_REGION_0__NEXT_MSB 0
#define RDMA_REGION_0__NEXT_LSB 0
#define RDMA_REGION_0__NEXT_MASK 0x00000001
#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
#define RDMA_REGION_1__ADDRESS 0x00000024
#define RDMA_REGION_1__OFFSET 0x00000024
#define RDMA_REGION_1__ADDR_MSB 31
#define RDMA_REGION_1__ADDR_LSB 13
#define RDMA_REGION_1__ADDR_MASK 0xffffe000
#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
#define RDMA_REGION_1__LENGTH_MSB 12
#define RDMA_REGION_1__LENGTH_LSB 2
#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
#define RDMA_REGION_1__INDI_MSB 1
#define RDMA_REGION_1__INDI_LSB 1
#define RDMA_REGION_1__INDI_MASK 0x00000002
#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
#define RDMA_REGION_1__NEXT_MSB 0
#define RDMA_REGION_1__NEXT_LSB 0
#define RDMA_REGION_1__NEXT_MASK 0x00000001
#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
#define RDMA_REGION_2__ADDRESS 0x00000028
#define RDMA_REGION_2__OFFSET 0x00000028
#define RDMA_REGION_2__ADDR_MSB 31
#define RDMA_REGION_2__ADDR_LSB 13
#define RDMA_REGION_2__ADDR_MASK 0xffffe000
#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
#define RDMA_REGION_2__LENGTH_MSB 12
#define RDMA_REGION_2__LENGTH_LSB 2
#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
#define RDMA_REGION_2__INDI_MSB 1
#define RDMA_REGION_2__INDI_LSB 1
#define RDMA_REGION_2__INDI_MASK 0x00000002
#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
#define RDMA_REGION_2__NEXT_MSB 0
#define RDMA_REGION_2__NEXT_LSB 0
#define RDMA_REGION_2__NEXT_MASK 0x00000001
#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
#define RDMA_REGION_3__ADDRESS 0x0000002c
#define RDMA_REGION_3__OFFSET 0x0000002c
#define RDMA_REGION_3__ADDR_MSB 31
#define RDMA_REGION_3__ADDR_LSB 13
#define RDMA_REGION_3__ADDR_MASK 0xffffe000
#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
#define RDMA_REGION_3__LENGTH_MSB 12
#define RDMA_REGION_3__LENGTH_LSB 2
#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
#define RDMA_REGION_3__INDI_MSB 1
#define RDMA_REGION_3__INDI_LSB 1
#define RDMA_REGION_3__INDI_MASK 0x00000002
#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
#define RDMA_REGION_3__NEXT_MSB 0
#define RDMA_REGION_3__NEXT_LSB 0
#define RDMA_REGION_3__NEXT_MASK 0x00000001
#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
#define RDMA_REGION_4__ADDRESS 0x00000030
#define RDMA_REGION_4__OFFSET 0x00000030
#define RDMA_REGION_4__ADDR_MSB 31
#define RDMA_REGION_4__ADDR_LSB 13
#define RDMA_REGION_4__ADDR_MASK 0xffffe000
#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
#define RDMA_REGION_4__LENGTH_MSB 12
#define RDMA_REGION_4__LENGTH_LSB 2
#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
#define RDMA_REGION_4__INDI_MSB 1
#define RDMA_REGION_4__INDI_LSB 1
#define RDMA_REGION_4__INDI_MASK 0x00000002
#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
#define RDMA_REGION_4__NEXT_MSB 0
#define RDMA_REGION_4__NEXT_LSB 0
#define RDMA_REGION_4__NEXT_MASK 0x00000001
#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
#define RDMA_REGION_5__ADDRESS 0x00000034
#define RDMA_REGION_5__OFFSET 0x00000034
#define RDMA_REGION_5__ADDR_MSB 31
#define RDMA_REGION_5__ADDR_LSB 13
#define RDMA_REGION_5__ADDR_MASK 0xffffe000
#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
#define RDMA_REGION_5__LENGTH_MSB 12
#define RDMA_REGION_5__LENGTH_LSB 2
#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
#define RDMA_REGION_5__INDI_MSB 1
#define RDMA_REGION_5__INDI_LSB 1
#define RDMA_REGION_5__INDI_MASK 0x00000002
#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
#define RDMA_REGION_5__NEXT_MSB 0
#define RDMA_REGION_5__NEXT_LSB 0
#define RDMA_REGION_5__NEXT_MASK 0x00000001
#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
#define RDMA_REGION_6__ADDRESS 0x00000038
#define RDMA_REGION_6__OFFSET 0x00000038
#define RDMA_REGION_6__ADDR_MSB 31
#define RDMA_REGION_6__ADDR_LSB 13
#define RDMA_REGION_6__ADDR_MASK 0xffffe000
#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
#define RDMA_REGION_6__LENGTH_MSB 12
#define RDMA_REGION_6__LENGTH_LSB 2
#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
#define RDMA_REGION_6__INDI_MSB 1
#define RDMA_REGION_6__INDI_LSB 1
#define RDMA_REGION_6__INDI_MASK 0x00000002
#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
#define RDMA_REGION_6__NEXT_MSB 0
#define RDMA_REGION_6__NEXT_LSB 0
#define RDMA_REGION_6__NEXT_MASK 0x00000001
#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
#define RDMA_REGION_7__ADDRESS 0x0000003c
#define RDMA_REGION_7__OFFSET 0x0000003c
#define RDMA_REGION_7__ADDR_MSB 31
#define RDMA_REGION_7__ADDR_LSB 13
#define RDMA_REGION_7__ADDR_MASK 0xffffe000
#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
#define RDMA_REGION_7__LENGTH_MSB 12
#define RDMA_REGION_7__LENGTH_LSB 2
#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
#define RDMA_REGION_7__INDI_MSB 1
#define RDMA_REGION_7__INDI_LSB 1
#define RDMA_REGION_7__INDI_MASK 0x00000002
#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
#define RDMA_REGION_7__NEXT_MSB 0
#define RDMA_REGION_7__NEXT_LSB 0
#define RDMA_REGION_7__NEXT_MASK 0x00000001
#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
#define RDMA_REGION_8__ADDRESS 0x00000040
#define RDMA_REGION_8__OFFSET 0x00000040
#define RDMA_REGION_8__ADDR_MSB 31
#define RDMA_REGION_8__ADDR_LSB 13
#define RDMA_REGION_8__ADDR_MASK 0xffffe000
#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
#define RDMA_REGION_8__LENGTH_MSB 12
#define RDMA_REGION_8__LENGTH_LSB 2
#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
#define RDMA_REGION_8__INDI_MSB 1
#define RDMA_REGION_8__INDI_LSB 1
#define RDMA_REGION_8__INDI_MASK 0x00000002
#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
#define RDMA_REGION_8__NEXT_MSB 0
#define RDMA_REGION_8__NEXT_LSB 0
#define RDMA_REGION_8__NEXT_MASK 0x00000001
#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
#define RDMA_REGION_9__ADDRESS 0x00000044
#define RDMA_REGION_9__OFFSET 0x00000044
#define RDMA_REGION_9__ADDR_MSB 31
#define RDMA_REGION_9__ADDR_LSB 13
#define RDMA_REGION_9__ADDR_MASK 0xffffe000
#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
#define RDMA_REGION_9__LENGTH_MSB 12
#define RDMA_REGION_9__LENGTH_LSB 2
#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
#define RDMA_REGION_9__INDI_MSB 1
#define RDMA_REGION_9__INDI_LSB 1
#define RDMA_REGION_9__INDI_MASK 0x00000002
#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
#define RDMA_REGION_9__NEXT_MSB 0
#define RDMA_REGION_9__NEXT_LSB 0
#define RDMA_REGION_9__NEXT_MASK 0x00000001
#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
#define RDMA_REGION_10__ADDRESS 0x00000048
#define RDMA_REGION_10__OFFSET 0x00000048
#define RDMA_REGION_10__ADDR_MSB 31
#define RDMA_REGION_10__ADDR_LSB 13
#define RDMA_REGION_10__ADDR_MASK 0xffffe000
#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
#define RDMA_REGION_10__LENGTH_MSB 12
#define RDMA_REGION_10__LENGTH_LSB 2
#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
#define RDMA_REGION_10__INDI_MSB 1
#define RDMA_REGION_10__INDI_LSB 1
#define RDMA_REGION_10__INDI_MASK 0x00000002
#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
#define RDMA_REGION_10__NEXT_MSB 0
#define RDMA_REGION_10__NEXT_LSB 0
#define RDMA_REGION_10__NEXT_MASK 0x00000001
#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
#define RDMA_REGION_11__ADDRESS 0x0000004c
#define RDMA_REGION_11__OFFSET 0x0000004c
#define RDMA_REGION_11__ADDR_MSB 31
#define RDMA_REGION_11__ADDR_LSB 13
#define RDMA_REGION_11__ADDR_MASK 0xffffe000
#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
#define RDMA_REGION_11__LENGTH_MSB 12
#define RDMA_REGION_11__LENGTH_LSB 2
#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
#define RDMA_REGION_11__INDI_MSB 1
#define RDMA_REGION_11__INDI_LSB 1
#define RDMA_REGION_11__INDI_MASK 0x00000002
#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
#define RDMA_REGION_11__NEXT_MSB 0
#define RDMA_REGION_11__NEXT_LSB 0
#define RDMA_REGION_11__NEXT_MASK 0x00000001
#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
#define RDMA_REGION_12__ADDRESS 0x00000050
#define RDMA_REGION_12__OFFSET 0x00000050
#define RDMA_REGION_12__ADDR_MSB 31
#define RDMA_REGION_12__ADDR_LSB 13
#define RDMA_REGION_12__ADDR_MASK 0xffffe000
#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
#define RDMA_REGION_12__LENGTH_MSB 12
#define RDMA_REGION_12__LENGTH_LSB 2
#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
#define RDMA_REGION_12__INDI_MSB 1
#define RDMA_REGION_12__INDI_LSB 1
#define RDMA_REGION_12__INDI_MASK 0x00000002
#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
#define RDMA_REGION_12__NEXT_MSB 0
#define RDMA_REGION_12__NEXT_LSB 0
#define RDMA_REGION_12__NEXT_MASK 0x00000001
#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
#define RDMA_REGION_13__ADDRESS 0x00000054
#define RDMA_REGION_13__OFFSET 0x00000054
#define RDMA_REGION_13__ADDR_MSB 31
#define RDMA_REGION_13__ADDR_LSB 13
#define RDMA_REGION_13__ADDR_MASK 0xffffe000
#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
#define RDMA_REGION_13__LENGTH_MSB 12
#define RDMA_REGION_13__LENGTH_LSB 2
#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
#define RDMA_REGION_13__INDI_MSB 1
#define RDMA_REGION_13__INDI_LSB 1
#define RDMA_REGION_13__INDI_MASK 0x00000002
#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
#define RDMA_REGION_13__NEXT_MSB 0
#define RDMA_REGION_13__NEXT_LSB 0
#define RDMA_REGION_13__NEXT_MASK 0x00000001
#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
#define RDMA_REGION_14__ADDRESS 0x00000058
#define RDMA_REGION_14__OFFSET 0x00000058
#define RDMA_REGION_14__ADDR_MSB 31
#define RDMA_REGION_14__ADDR_LSB 13
#define RDMA_REGION_14__ADDR_MASK 0xffffe000
#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
#define RDMA_REGION_14__LENGTH_MSB 12
#define RDMA_REGION_14__LENGTH_LSB 2
#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
#define RDMA_REGION_14__INDI_MSB 1
#define RDMA_REGION_14__INDI_LSB 1
#define RDMA_REGION_14__INDI_MASK 0x00000002
#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
#define RDMA_REGION_14__NEXT_MSB 0
#define RDMA_REGION_14__NEXT_LSB 0
#define RDMA_REGION_14__NEXT_MASK 0x00000001
#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
#define RDMA_REGION_15__ADDRESS 0x0000005c
#define RDMA_REGION_15__OFFSET 0x0000005c
#define RDMA_REGION_15__ADDR_MSB 31
#define RDMA_REGION_15__ADDR_LSB 13
#define RDMA_REGION_15__ADDR_MASK 0xffffe000
#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
#define RDMA_REGION_15__LENGTH_MSB 12
#define RDMA_REGION_15__LENGTH_LSB 2
#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
#define RDMA_REGION_15__INDI_MSB 1
#define RDMA_REGION_15__INDI_LSB 1
#define RDMA_REGION_15__INDI_MASK 0x00000002
#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
#define RDMA_REGION_15__NEXT_MSB 0
#define RDMA_REGION_15__NEXT_LSB 0
#define RDMA_REGION_15__NEXT_MASK 0x00000001
#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
#define DMA_STATUS_ADDRESS 0x00000060
#define DMA_STATUS_OFFSET 0x00000060
#define DMA_STATUS_ERROR_CODE_MSB 14
#define DMA_STATUS_ERROR_CODE_LSB 4
#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0
#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
#define DMA_STATUS_ERROR_MSB 3
#define DMA_STATUS_ERROR_LSB 3
#define DMA_STATUS_ERROR_MASK 0x00000008
#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
#define DMA_STATUS_DONE_MSB 2
#define DMA_STATUS_DONE_LSB 2
#define DMA_STATUS_DONE_MASK 0x00000004
#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
#define DMA_STATUS_STOPPED_MSB 1
#define DMA_STATUS_STOPPED_LSB 1
#define DMA_STATUS_STOPPED_MASK 0x00000002
#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
#define DMA_STATUS_RUNNING_MSB 0
#define DMA_STATUS_RUNNING_LSB 0
#define DMA_STATUS_RUNNING_MASK 0x00000001
#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
#define DMA_INT_EN_ADDRESS 0x00000064
#define DMA_INT_EN_OFFSET 0x00000064
#define DMA_INT_EN_ERROR_ENA_MSB 3
#define DMA_INT_EN_ERROR_ENA_LSB 3
#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008
#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
#define DMA_INT_EN_DONE_ENA_MSB 2
#define DMA_INT_EN_DONE_ENA_LSB 2
#define DMA_INT_EN_DONE_ENA_MASK 0x00000004
#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
#define DMA_INT_EN_STOPPED_ENA_MSB 1
#define DMA_INT_EN_STOPPED_ENA_LSB 1
#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002
#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
#ifndef __ASSEMBLER__
typedef struct rdma_reg_reg_s {
volatile unsigned int dma_config;
volatile unsigned int dma_control;
volatile unsigned int dma_src;
volatile unsigned int dma_dest;
volatile unsigned int dma_length;
volatile unsigned int vmc_base;
volatile unsigned int indirect_reg;
volatile unsigned int indirect_return;
volatile unsigned int rdma_region_0_;
volatile unsigned int rdma_region_1_;
volatile unsigned int rdma_region_2_;
volatile unsigned int rdma_region_3_;
volatile unsigned int rdma_region_4_;
volatile unsigned int rdma_region_5_;
volatile unsigned int rdma_region_6_;
volatile unsigned int rdma_region_7_;
volatile unsigned int rdma_region_8_;
volatile unsigned int rdma_region_9_;
volatile unsigned int rdma_region_10_;
volatile unsigned int rdma_region_11_;
volatile unsigned int rdma_region_12_;
volatile unsigned int rdma_region_13_;
volatile unsigned int rdma_region_14_;
volatile unsigned int rdma_region_15_;
volatile unsigned int dma_status;
volatile unsigned int dma_int_en;
} rdma_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _RDMA_REG_H_ */

788
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
View File

@ -21,11 +21,8 @@
//===================================================================
#ifdef WLAN_HEADERS
#include "rtc_wlan_reg.h"
#ifndef BT_HEADERS
#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
@ -100,95 +97,6 @@
#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
@ -215,510 +123,6 @@
#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
#define WDT_ADDRESS WLAN_WDT_ADDRESS
#define WDT_OFFSET WLAN_WDT_OFFSET
#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
@ -753,49 +157,6 @@
#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
@ -822,154 +183,5 @@
#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
#endif
#endif

1903
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
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209
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h
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@ -1,209 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _SI_REG_REG_H_
#define _SI_REG_REG_H_
#define SI_CONFIG_ADDRESS 0x00000000
#define SI_CONFIG_OFFSET 0x00000000
#define SI_CONFIG_ERR_INT_MSB 19
#define SI_CONFIG_ERR_INT_LSB 19
#define SI_CONFIG_ERR_INT_MASK 0x00080000
#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_MSB 16
#define SI_CONFIG_I2C_LSB 16
#define SI_CONFIG_I2C_MASK 0x00010000
#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_MSB 7
#define SI_CONFIG_POS_SAMPLE_LSB 7
#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_POS_DRIVE_MSB 6
#define SI_CONFIG_POS_DRIVE_LSB 6
#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
#define SI_CONFIG_INACTIVE_DATA_MSB 5
#define SI_CONFIG_INACTIVE_DATA_LSB 5
#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_INACTIVE_CLK_MSB 4
#define SI_CONFIG_INACTIVE_CLK_LSB 4
#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_DIVIDER_MSB 3
#define SI_CONFIG_DIVIDER_LSB 0
#define SI_CONFIG_DIVIDER_MASK 0x0000000f
#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_ADDRESS 0x00000004
#define SI_CS_OFFSET 0x00000004
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
#define SI_CS_DONE_ERR_MSB 10
#define SI_CS_DONE_ERR_LSB 10
#define SI_CS_DONE_ERR_MASK 0x00000400
#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MSB 9
#define SI_CS_DONE_INT_LSB 9
#define SI_CS_DONE_INT_MASK 0x00000200
#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
#define SI_CS_START_MSB 8
#define SI_CS_START_LSB 8
#define SI_CS_START_MASK 0x00000100
#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_MSB 7
#define SI_CS_RX_CNT_LSB 4
#define SI_CS_RX_CNT_MASK 0x000000f0
#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_MSB 3
#define SI_CS_TX_CNT_LSB 0
#define SI_CS_TX_CNT_MASK 0x0000000f
#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define SI_TX_DATA0_ADDRESS 0x00000008
#define SI_TX_DATA0_OFFSET 0x00000008
#define SI_TX_DATA0_DATA3_MSB 31
#define SI_TX_DATA0_DATA3_LSB 24
#define SI_TX_DATA0_DATA3_MASK 0xff000000
#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
#define SI_TX_DATA0_DATA2_MSB 23
#define SI_TX_DATA0_DATA2_LSB 16
#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
#define SI_TX_DATA0_DATA1_MSB 15
#define SI_TX_DATA0_DATA1_LSB 8
#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
#define SI_TX_DATA0_DATA0_MSB 7
#define SI_TX_DATA0_DATA0_LSB 0
#define SI_TX_DATA0_DATA0_MASK 0x000000ff
#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
#define SI_TX_DATA1_ADDRESS 0x0000000c
#define SI_TX_DATA1_OFFSET 0x0000000c
#define SI_TX_DATA1_DATA7_MSB 31
#define SI_TX_DATA1_DATA7_LSB 24
#define SI_TX_DATA1_DATA7_MASK 0xff000000
#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
#define SI_TX_DATA1_DATA6_MSB 23
#define SI_TX_DATA1_DATA6_LSB 16
#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
#define SI_TX_DATA1_DATA5_MSB 15
#define SI_TX_DATA1_DATA5_LSB 8
#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
#define SI_TX_DATA1_DATA4_MSB 7
#define SI_TX_DATA1_DATA4_LSB 0
#define SI_TX_DATA1_DATA4_MASK 0x000000ff
#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
#define SI_RX_DATA0_ADDRESS 0x00000010
#define SI_RX_DATA0_OFFSET 0x00000010
#define SI_RX_DATA0_DATA3_MSB 31
#define SI_RX_DATA0_DATA3_LSB 24
#define SI_RX_DATA0_DATA3_MASK 0xff000000
#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
#define SI_RX_DATA0_DATA2_MSB 23
#define SI_RX_DATA0_DATA2_LSB 16
#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
#define SI_RX_DATA0_DATA1_MSB 15
#define SI_RX_DATA0_DATA1_LSB 8
#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
#define SI_RX_DATA0_DATA0_MSB 7
#define SI_RX_DATA0_DATA0_LSB 0
#define SI_RX_DATA0_DATA0_MASK 0x000000ff
#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
#define SI_RX_DATA1_ADDRESS 0x00000014
#define SI_RX_DATA1_OFFSET 0x00000014
#define SI_RX_DATA1_DATA7_MSB 31
#define SI_RX_DATA1_DATA7_LSB 24
#define SI_RX_DATA1_DATA7_MASK 0xff000000
#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
#define SI_RX_DATA1_DATA6_MSB 23
#define SI_RX_DATA1_DATA6_LSB 16
#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
#define SI_RX_DATA1_DATA5_MSB 15
#define SI_RX_DATA1_DATA5_LSB 8
#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
#define SI_RX_DATA1_DATA4_MSB 7
#define SI_RX_DATA1_DATA4_LSB 0
#define SI_RX_DATA1_DATA4_MASK 0x000000ff
#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
#ifndef __ASSEMBLER__
typedef struct si_reg_reg_s {
volatile unsigned int si_config;
volatile unsigned int si_cs;
volatile unsigned int si_tx_data0;
volatile unsigned int si_tx_data1;
volatile unsigned int si_rx_data0;
volatile unsigned int si_rx_data1;
} si_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _SI_REG_H_ */

220
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
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@ -24,107 +24,6 @@
#ifndef _UART_REG_REG_H_
#define _UART_REG_REG_H_
#define UART_DATA_ADDRESS 0x00000000
#define UART_DATA_OFFSET 0x00000000
#define UART_DATA_TX_CSR_MSB 9
#define UART_DATA_TX_CSR_LSB 9
#define UART_DATA_TX_CSR_MASK 0x00000200
#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
#define UART_DATA_RX_CSR_MSB 8
#define UART_DATA_RX_CSR_LSB 8
#define UART_DATA_RX_CSR_MASK 0x00000100
#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
#define UART_DATA_TXRX_DATA_MSB 7
#define UART_DATA_TXRX_DATA_LSB 0
#define UART_DATA_TXRX_DATA_MASK 0x000000ff
#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
#define UART_CONTROL_ADDRESS 0x00000004
#define UART_CONTROL_OFFSET 0x00000004
#define UART_CONTROL_RX_BUSY_MSB 15
#define UART_CONTROL_RX_BUSY_LSB 15
#define UART_CONTROL_RX_BUSY_MASK 0x00008000
#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
#define UART_CONTROL_TX_BUSY_MSB 14
#define UART_CONTROL_TX_BUSY_LSB 14
#define UART_CONTROL_TX_BUSY_MASK 0x00004000
#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
#define UART_CONTROL_HOST_INT_ENABLE_MSB 13
#define UART_CONTROL_HOST_INT_ENABLE_LSB 13
#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000
#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
#define UART_CONTROL_HOST_INT_MSB 12
#define UART_CONTROL_HOST_INT_LSB 12
#define UART_CONTROL_HOST_INT_MASK 0x00001000
#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
#define UART_CONTROL_TX_BREAK_MSB 11
#define UART_CONTROL_TX_BREAK_LSB 11
#define UART_CONTROL_TX_BREAK_MASK 0x00000800
#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
#define UART_CONTROL_RX_BREAK_MSB 10
#define UART_CONTROL_RX_BREAK_LSB 10
#define UART_CONTROL_RX_BREAK_MASK 0x00000400
#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
#define UART_CONTROL_SERIAL_TX_READY_MSB 9
#define UART_CONTROL_SERIAL_TX_READY_LSB 9
#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200
#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
#define UART_CONTROL_TX_READY_ORIDE_MSB 8
#define UART_CONTROL_TX_READY_ORIDE_LSB 8
#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100
#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
#define UART_CONTROL_RX_READY_ORIDE_MSB 7
#define UART_CONTROL_RX_READY_ORIDE_LSB 7
#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080
#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
#define UART_CONTROL_DMA_ENABLE_MSB 6
#define UART_CONTROL_DMA_ENABLE_LSB 6
#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040
#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
#define UART_CONTROL_FLOW_ENABLE_MSB 5
#define UART_CONTROL_FLOW_ENABLE_LSB 5
#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020
#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
#define UART_CONTROL_FLOW_INVERT_MSB 4
#define UART_CONTROL_FLOW_INVERT_LSB 4
#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010
#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
#define UART_CONTROL_IFC_ENABLE_MSB 3
#define UART_CONTROL_IFC_ENABLE_LSB 3
#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008
#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
#define UART_CONTROL_IFC_DCE_MSB 2
#define UART_CONTROL_IFC_DCE_LSB 2
#define UART_CONTROL_IFC_DCE_MASK 0x00000004
#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
#define UART_CONTROL_PARITY_ENABLE_MSB 1
#define UART_CONTROL_PARITY_ENABLE_LSB 1
#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002
#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
#define UART_CONTROL_PARITY_EVEN_MSB 0
#define UART_CONTROL_PARITY_EVEN_LSB 0
#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001
#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
#define UART_CLKDIV_ADDRESS 0x00000008
#define UART_CLKDIV_OFFSET 0x00000008
#define UART_CLKDIV_CLK_SCALE_MSB 23
@ -138,123 +37,4 @@
#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
#define UART_INT_ADDRESS 0x0000000c
#define UART_INT_OFFSET 0x0000000c
#define UART_INT_TX_EMPTY_INT_MSB 9
#define UART_INT_TX_EMPTY_INT_LSB 9
#define UART_INT_TX_EMPTY_INT_MASK 0x00000200
#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
#define UART_INT_RX_FULL_INT_MSB 8
#define UART_INT_RX_FULL_INT_LSB 8
#define UART_INT_RX_FULL_INT_MASK 0x00000100
#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
#define UART_INT_RX_BREAK_OFF_INT_MSB 7
#define UART_INT_RX_BREAK_OFF_INT_LSB 7
#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080
#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
#define UART_INT_RX_BREAK_ON_INT_MSB 6
#define UART_INT_RX_BREAK_ON_INT_LSB 6
#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040
#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
#define UART_INT_RX_PARITY_ERR_INT_MSB 5
#define UART_INT_RX_PARITY_ERR_INT_LSB 5
#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020
#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
#define UART_INT_TX_OFLOW_ERR_INT_MSB 4
#define UART_INT_TX_OFLOW_ERR_INT_LSB 4
#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010
#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
#define UART_INT_RX_OFLOW_ERR_INT_MSB 3
#define UART_INT_RX_OFLOW_ERR_INT_LSB 3
#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008
#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
#define UART_INT_RX_FRAMING_ERR_INT_MSB 2
#define UART_INT_RX_FRAMING_ERR_INT_LSB 2
#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004
#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
#define UART_INT_TX_READY_INT_MSB 1
#define UART_INT_TX_READY_INT_LSB 1
#define UART_INT_TX_READY_INT_MASK 0x00000002
#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
#define UART_INT_RX_VALID_INT_MSB 0
#define UART_INT_RX_VALID_INT_LSB 0
#define UART_INT_RX_VALID_INT_MASK 0x00000001
#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
#define UART_INT_EN_ADDRESS 0x00000010
#define UART_INT_EN_OFFSET 0x00000010
#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9
#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9
#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200
#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
#define UART_INT_EN_RX_FULL_INT_EN_MSB 8
#define UART_INT_EN_RX_FULL_INT_EN_LSB 8
#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100
#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6
#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6
#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040
#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
#define UART_INT_EN_TX_READY_INT_EN_MSB 1
#define UART_INT_EN_TX_READY_INT_EN_LSB 1
#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002
#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
#define UART_INT_EN_RX_VALID_INT_EN_MSB 0
#define UART_INT_EN_RX_VALID_INT_EN_LSB 0
#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001
#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
#ifndef __ASSEMBLER__
typedef struct uart_reg_reg_s {
volatile unsigned int uart_data;
volatile unsigned int uart_control;
volatile unsigned int uart_clkdiv;
volatile unsigned int uart_int;
volatile unsigned int uart_int_en;
} uart_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UART_REG_H_ */

37
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h
View File

@ -1,37 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "umbox_wlan_reg.h"
#ifndef BT_HEADERS
#endif
#endif

322
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h
View File

@ -1,322 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _UMBOX_WLAN_REG_REG_H_
#define _UMBOX_WLAN_REG_REG_H_
#define UMBOX_FIFO_ADDRESS 0x00000000
#define UMBOX_FIFO_OFFSET 0x00000000
#define UMBOX_FIFO_DATA_MSB 8
#define UMBOX_FIFO_DATA_LSB 0
#define UMBOX_FIFO_DATA_MASK 0x000001ff
#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
#define UMBOX_FIFO_STATUS_OFFSET 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
#define UMBOX_DMA_POLICY_OFFSET 0x0000000c
#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_RX_CONTROL_START_MSB 1
#define UMBOX0_DMA_RX_CONTROL_START_LSB 1
#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_TX_CONTROL_START_MSB 1
#define UMBOX0_DMA_TX_CONTROL_START_LSB 1
#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
#define UMBOX_INT_STATUS_ADDRESS 0x00000024
#define UMBOX_INT_STATUS_OFFSET 0x00000024
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define UMBOX_INT_ENABLE_ADDRESS 0x00000028
#define UMBOX_INT_ENABLE_OFFSET 0x00000028
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define UMBOX_DEBUG_ADDRESS 0x0000002c
#define UMBOX_DEBUG_OFFSET 0x0000002c
#define UMBOX_DEBUG_SEL_MSB 2
#define UMBOX_DEBUG_SEL_LSB 0
#define UMBOX_DEBUG_SEL_MASK 0x00000007
#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
#define UMBOX_FIFO_RESET_ADDRESS 0x00000030
#define UMBOX_FIFO_RESET_OFFSET 0x00000030
#define UMBOX_FIFO_RESET_INIT_MSB 0
#define UMBOX_FIFO_RESET_INIT_LSB 0
#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
#define UMBOX_HCI_FRAMER_OFFSET 0x00000034
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
#define UMBOX_HCI_FRAMER_ENABLE_MSB 5
#define UMBOX_HCI_FRAMER_ENABLE_LSB 5
#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
#ifndef __ASSEMBLER__
typedef struct umbox_wlan_reg_reg_s {
volatile unsigned int umbox_fifo[2];
volatile unsigned int umbox_fifo_status;
volatile unsigned int umbox_dma_policy;
volatile unsigned int umbox0_dma_rx_descriptor_base;
volatile unsigned int umbox0_dma_rx_control;
volatile unsigned int umbox0_dma_tx_descriptor_base;
volatile unsigned int umbox0_dma_tx_control;
volatile unsigned int umbox_fifo_timeout;
volatile unsigned int umbox_int_status;
volatile unsigned int umbox_int_enable;
volatile unsigned int umbox_debug;
volatile unsigned int umbox_fifo_reset;
volatile unsigned int umbox_hci_framer;
} umbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UMBOX_WLAN_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "vmc_wlan_reg.h"
#ifndef BT_HEADERS
#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
#endif
#endif

195
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h
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@ -1,195 +0,0 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _VMC_WLAN_REG_REG_H_
#define _VMC_WLAN_REG_REG_H_
#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000
#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000
#define WLAN_MC_BCAM_VALID_BIT_MSB 0
#define WLAN_MC_BCAM_VALID_BIT_LSB 0
#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001
#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200
#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200
#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19
#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2
#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc
#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400
#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400
#define WLAN_MC_BCAM_TARGET_INST_MSB 31
#define WLAN_MC_BCAM_TARGET_INST_LSB 0
#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff
#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600
#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604
#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608
#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c
#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610
#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614
#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614
#define WLAN_CPU_PERF_CNT_EN_MSB 0
#define WLAN_CPU_PERF_CNT_EN_LSB 0
#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001
#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618
#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618
#define WLAN_CPU_INST_FETCH_CNT_MSB 31
#define WLAN_CPU_INST_FETCH_CNT_LSB 0
#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff
#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c
#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c
#define WLAN_CPU_DATA_FETCH_CNT_MSB 31
#define WLAN_CPU_DATA_FETCH_CNT_LSB 0
#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff
#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620
#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620
#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624
#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624
#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628
#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628
#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c
#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c
#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
#ifndef __ASSEMBLER__
typedef struct vmc_wlan_reg_reg_s {
volatile unsigned int wlan_mc_bcam_valid[128];
volatile unsigned int wlan_mc_bcam_compare[128];
volatile unsigned int wlan_mc_bcam_target[128];
volatile unsigned int wlan_apb_addr_error_control;
volatile unsigned int wlan_apb_addr_error_status;
volatile unsigned int wlan_ahb_addr_error_control;
volatile unsigned int wlan_ahb_addr_error_status;
volatile unsigned int wlan_bcam_conflict_error;
volatile unsigned int wlan_cpu_perf_cnt;
volatile unsigned int wlan_cpu_inst_fetch;
volatile unsigned int wlan_cpu_data_fetch;
volatile unsigned int wlan_cpu_ram1_conflict;
volatile unsigned int wlan_cpu_ram2_conflict;
volatile unsigned int wlan_cpu_ram3_conflict;
volatile unsigned int wlan_cpu_ram4_conflict;
} vmc_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _VMC_WLAN_REG_H_ */

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drivers/staging/ath6kl/include/common/a_hci.h
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@ -1,682 +0,0 @@
//-
// Copyright (c) 2009-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
//
#ifndef __A_HCI_H__
#define __A_HCI_H__
#define HCI_CMD_OGF_MASK 0x3F
#define HCI_CMD_OGF_SHIFT 10
#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
#define HCI_CMD_OCF_MASK 0x3FF
#define HCI_CMD_OCF_SHIFT 0
#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
(ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
/*======== HCI Opcode groups ===============*/
#define OGF_NOP 0x00
#define OGF_LINK_CONTROL 0x01
#define OGF_LINK_POLICY 0x03
#define OGF_INFO_PARAMS 0x04
#define OGF_STATUS 0x05
#define OGF_TESTING 0x06
#define OGF_BLUETOOTH 0x3E
#define OGF_VENDOR_DEBUG 0x3F
#define OCF_NOP 0x00
/*===== Link Control Commands Opcode===================*/
#define OCF_HCI_Create_Physical_Link 0x35
#define OCF_HCI_Accept_Physical_Link_Req 0x36
#define OCF_HCI_Disconnect_Physical_Link 0x37
#define OCF_HCI_Create_Logical_Link 0x38
#define OCF_HCI_Accept_Logical_Link 0x39
#define OCF_HCI_Disconnect_Logical_Link 0x3A
#define OCF_HCI_Logical_Link_Cancel 0x3B
#define OCF_HCI_Flow_Spec_Modify 0x3C
/*===== Link Policy Commands Opcode====================*/
#define OCF_HCI_Set_Event_Mask 0x01
#define OCF_HCI_Reset 0x03
#define OCF_HCI_Read_Conn_Accept_Timeout 0x15
#define OCF_HCI_Write_Conn_Accept_Timeout 0x16
#define OCF_HCI_Read_Link_Supervision_Timeout 0x36
#define OCF_HCI_Write_Link_Supervision_Timeout 0x37
#define OCF_HCI_Enhanced_Flush 0x5F
#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61
#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62
#define OCF_HCI_Set_Event_Mask_Page_2 0x63
#define OCF_HCI_Read_Location_Data 0x64
#define OCF_HCI_Write_Location_Data 0x65
#define OCF_HCI_Read_Flow_Control_Mode 0x66
#define OCF_HCI_Write_Flow_Control_Mode 0x67
#define OCF_HCI_Read_BE_Flush_Timeout 0x69
#define OCF_HCI_Write_BE_Flush_Timeout 0x6A
#define OCF_HCI_Short_Range_Mode 0x6B
/*======== Info Commands Opcode========================*/
#define OCF_HCI_Read_Local_Ver_Info 0x01
#define OCF_HCI_Read_Local_Supported_Cmds 0x02
#define OCF_HCI_Read_Data_Block_Size 0x0A
/*======== Status Commands Opcode======================*/
#define OCF_HCI_Read_Failed_Contact_Counter 0x01
#define OCF_HCI_Reset_Failed_Contact_Counter 0x02
#define OCF_HCI_Read_Link_Quality 0x03
#define OCF_HCI_Read_RSSI 0x05
#define OCF_HCI_Read_Local_AMP_Info 0x09
#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A
#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B
/*======= AMP_ASSOC Specific TLV tags =================*/
#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1
#define AMP_ASSOC_PREF_CHAN_LIST 0x2
#define AMP_ASSOC_CONNECTED_CHAN 0x3
#define AMP_ASSOC_PAL_CAPABILITIES 0x4
#define AMP_ASSOC_PAL_VERSION 0x5
/*========= PAL Events =================================*/
#define PAL_COMMAND_COMPLETE_EVENT 0x0E
#define PAL_COMMAND_STATUS_EVENT 0x0F
#define PAL_HARDWARE_ERROR_EVENT 0x10
#define PAL_FLUSH_OCCURRED_EVENT 0x11
#define PAL_LOOPBACK_EVENT 0x19
#define PAL_BUFFER_OVERFLOW_EVENT 0x1A
#define PAL_QOS_VIOLATION_EVENT 0x1E
#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39
#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40
#define PAL_CHANNEL_SELECT_EVENT 0x41
#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42
#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43
#define PAL_PHY_LINK_RECOVERY_EVENT 0x44
#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45
#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46
#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47
#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48
#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C
#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D
/*======== End of PAL events definition =================*/
/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
#define Timer_Conn_Accept_TO 0x01
#define Timer_Link_Supervision_TO 0x02
#define NUM_HCI_COMMAND_PKTS 0x1
/*====== NOP Cmd ============================*/
#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
/*===== Link Control Commands================*/
#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
/*===== Link Policy Commands ================*/
#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)
/*===== Info Commands =====================*/
#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS)
#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
/*===== Status Commands =====================*/
#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
/*====== End of cmd definitions =============*/
/*===== Timeouts(private - can't come from HCI)=================*/
#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
/*----- PAL Constants (Sec 6 of Doc)------------------------*/
#define Max80211_PAL_PDU_Size 1492
#define Max80211_AMP_ASSOC_Len 672
#define MinGUserPrio 4
#define MaxGUserPrio 7
#define BEUserPrio0 0
#define BEUserPrio1 3
#define Max80211BeaconPeriod 2000 /* in millisec */
#define ShortRangeModePowerMax 4 /* dBm */
/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
typedef enum {
ACL_DATA = 0x01,
ACTIVITY_REPORT,
SECURED_FRAMES,
LINK_SUPERVISION_REQ,
LINK_SUPERVISION_RESP,
}PAL_PROTOCOL_IDENTIFIERS;
#define HCI_CMD_HDR_SZ 3
#define HCI_EVENT_HDR_SIZE 2
#define MAX_EVT_PKT_SZ 255
#define AMP_ASSOC_MAX_FRAG_SZ 248
#define AMP_MAX_GUARANTEED_BW 20000
#define DEFAULT_CONN_ACCPT_TO 5000
#define DEFAULT_LL_ACCPT_TO 5000
#define DEFAULT_LSTO 10000
#define PACKET_BASED_FLOW_CONTROL_MODE 0x00
#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01
#define SERVICE_TYPE_BEST_EFFORT 0x01
#define SERVICE_TYPE_GUARANTEED 0x02
#define MAC_ADDR_LEN 6
#define LINK_KEY_LEN 32
typedef enum {
ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
ACL_DATA_PB_COMPLETE_PDU = 0x03,
} ACL_DATA_PB_FLAGS;
#define ACL_DATA_PB_FLAGS_SHIFT 12
typedef enum {
ACL_DATA_BC_POINT_TO_POINT = 0x00,
} ACL_DATA_BC_FLAGS;
#define ACL_DATA_BC_FLAGS_SHIFT 14
/* Command pkt */
typedef struct hci_cmd_pkt_t {
u16 opcode;
u8 param_length;
u8 params[255];
} POSTPACK HCI_CMD_PKT;
#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */
/* Data pkt */
typedef struct hci_acl_data_pkt_t {
u16 hdl_and_flags;
u16 data_len;
u8 data[Max80211_PAL_PDU_Size];
} POSTPACK HCI_ACL_DATA_PKT;
/* Event pkt */
typedef struct hci_event_pkt_t {
u8 event_code;
u8 param_len;
u8 params[256];
} POSTPACK HCI_EVENT_PKT;
/*============== HCI Command definitions ======================= */
typedef struct hci_cmd_phy_link_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
u8 link_key_len;
u8 link_key_type;
u8 link_key[LINK_KEY_LEN];
} POSTPACK HCI_CMD_PHY_LINK;
typedef struct hci_cmd_write_rem_amp_assoc_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
u16 len_so_far;
u16 amp_assoc_remaining_len;
u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
typedef struct hci_cmd_opcode_hdl_t {
u16 opcode;
u8 param_length;
u16 hdl;
} POSTPACK HCI_CMD_READ_LINK_QUAL,
HCI_CMD_FLUSH,
HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
typedef struct hci_cmd_read_local_amp_assoc_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
u16 len_so_far;
u16 max_rem_amp_assoc_len;
} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
typedef struct hci_cmd_set_event_mask_t {
u16 opcode;
u8 param_length;
u64 mask;
}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
typedef struct hci_cmd_enhanced_flush_t{
u16 opcode;
u8 param_length;
u16 hdl;
u8 type;
} POSTPACK HCI_CMD_ENHANCED_FLUSH;
typedef struct hci_cmd_write_timeout_t {
u16 opcode;
u8 param_length;
u16 timeout;
} POSTPACK HCI_CMD_WRITE_TIMEOUT;
typedef struct hci_cmd_write_link_supervision_timeout_t {
u16 opcode;
u8 param_length;
u16 hdl;
u16 timeout;
} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
typedef struct hci_cmd_write_flow_control_t {
u16 opcode;
u8 param_length;
u8 mode;
} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL;
typedef struct location_data_cfg_t {
u8 reg_domain_aware;
u8 reg_domain[3];
u8 reg_options;
} POSTPACK LOCATION_DATA_CFG;
typedef struct hci_cmd_write_location_data_t {
u16 opcode;
u8 param_length;
LOCATION_DATA_CFG cfg;
} POSTPACK HCI_CMD_WRITE_LOCATION_DATA;
typedef struct flow_spec_t {
u8 id;
u8 service_type;
u16 max_sdu;
u32 sdu_inter_arrival_time;
u32 access_latency;
u32 flush_timeout;
} POSTPACK FLOW_SPEC;
typedef struct hci_cmd_create_logical_link_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
FLOW_SPEC tx_flow_spec;
FLOW_SPEC rx_flow_spec;
} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
typedef struct hci_cmd_flow_spec_modify_t {
u16 opcode;
u8 param_length;
u16 hdl;
FLOW_SPEC tx_flow_spec;
FLOW_SPEC rx_flow_spec;
} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
typedef struct hci_cmd_logical_link_cancel_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
u8 tx_flow_spec_id;
} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
typedef struct hci_cmd_disconnect_logical_link_t {
u16 opcode;
u8 param_length;
u16 logical_link_hdl;
} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
typedef struct hci_cmd_disconnect_phy_link_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
typedef struct hci_cmd_srm_t {
u16 opcode;
u8 param_length;
u8 phy_link_hdl;
u8 mode;
} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
/*============== HCI Command definitions end ======================= */
/*============== HCI Event definitions ============================= */
/* Command complete event */
typedef struct hci_event_cmd_complete_t {
u8 event_code;
u8 param_len;
u8 num_hci_cmd_pkts;
u16 opcode;
u8 params[255];
} POSTPACK HCI_EVENT_CMD_COMPLETE;
/* Command status event */
typedef struct hci_event_cmd_status_t {
u8 event_code;
u8 param_len;
u8 status;
u8 num_hci_cmd_pkts;
u16 opcode;
} POSTPACK HCI_EVENT_CMD_STATUS;
/* Hardware Error event */
typedef struct hci_event_hw_err_t {
u8 event_code;
u8 param_len;
u8 hw_err_code;
} POSTPACK HCI_EVENT_HW_ERR;
/* Flush occurred event */
/* Qos Violation event */
typedef struct hci_event_handle_t {
u8 event_code;
u8 param_len;
u16 handle;
} POSTPACK HCI_EVENT_FLUSH_OCCRD,
HCI_EVENT_QOS_VIOLATION;
/* Loopback command event */
typedef struct hci_loopback_cmd_t {
u8 event_code;
u8 param_len;
u8 params[252];
} POSTPACK HCI_EVENT_LOOPBACK_CMD;
/* Data buffer overflow event */
typedef struct hci_data_buf_overflow_t {
u8 event_code;
u8 param_len;
u8 link_type;
} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW;
/* Enhanced Flush complete event */
typedef struct hci_enhanced_flush_complt_t{
u8 event_code;
u8 param_len;
u16 hdl;
} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT;
/* Channel select event */
typedef struct hci_event_chan_select_t {
u8 event_code;
u8 param_len;
u8 phy_link_hdl;
} POSTPACK HCI_EVENT_CHAN_SELECT;
/* Physical Link Complete event */
typedef struct hci_event_phy_link_complete_event_t {
u8 event_code;
u8 param_len;
u8 status;
u8 phy_link_hdl;
} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
/* Logical Link complete event */
typedef struct hci_event_logical_link_complete_event_t {
u8 event_code;
u8 param_len;
u8 status;
u16 logical_link_hdl;
u8 phy_hdl;
u8 tx_flow_id;
} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
/* Disconnect Logical Link complete event */
typedef struct hci_event_disconnect_logical_link_event_t {
u8 event_code;
u8 param_len;
u8 status;
u16 logical_link_hdl;
u8 reason;
} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
/* Disconnect Physical Link complete event */
typedef struct hci_event_disconnect_phy_link_complete_t {
u8 event_code;
u8 param_len;
u8 status;
u8 phy_link_hdl;
u8 reason;
} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
typedef struct hci_event_physical_link_loss_early_warning_t{
u8 event_code;
u8 param_len;
u8 phy_hdl;
u8 reason;
} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
typedef struct hci_event_physical_link_recovery_t{
u8 event_code;
u8 param_len;
u8 phy_hdl;
} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
/* Flow spec modify complete event */
/* Flush event */
typedef struct hci_event_status_handle_t {
u8 event_code;
u8 param_len;
u8 status;
u16 handle;
} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
HCI_EVENT_FLUSH;
/* Num of completed data blocks event */
typedef struct hci_event_num_of_compl_data_blks_t {
u8 event_code;
u8 param_len;
u16 num_data_blks;
u8 num_handles;
u8 params[255];
} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
/* Short range mode change complete event */
typedef struct hci_srm_cmpl_t {
u8 event_code;
u8 param_len;
u8 status;
u8 phy_link;
u8 state;
} POSTPACK HCI_EVENT_SRM_COMPL;
typedef struct hci_event_amp_status_change_t{
u8 event_code;
u8 param_len;
u8 status;
u8 amp_status;
} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
/*============== Event definitions end =========================== */
typedef struct local_amp_info_resp_t {
u8 status;
u8 amp_status;
u32 total_bw; /* kbps */
u32 max_guranteed_bw; /* kbps */
u32 min_latency;
u32 max_pdu_size;
u8 amp_type;
u16 pal_capabilities;
u16 amp_assoc_len;
u32 max_flush_timeout; /* in ms */
u32 be_flush_timeout; /* in ms */
} POSTPACK LOCAL_AMP_INFO;
typedef struct amp_assoc_cmd_resp_t{
u8 status;
u8 phy_hdl;
u16 amp_assoc_len;
u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
}POSTPACK AMP_ASSOC_CMD_RESP;
enum PAL_HCI_CMD_STATUS {
PAL_HCI_CMD_PROCESSED,
PAL_HCI_CMD_IGNORED
};
/*============= HCI Error Codes =======================*/
#define HCI_SUCCESS 0x00
#define HCI_ERR_UNKNOW_CMD 0x01
#define HCI_ERR_UNKNOWN_CONN_ID 0x02
#define HCI_ERR_HW_FAILURE 0x03
#define HCI_ERR_PAGE_TIMEOUT 0x04
#define HCI_ERR_AUTH_FAILURE 0x05
#define HCI_ERR_KEY_MISSING 0x06
#define HCI_ERR_MEM_CAP_EXECED 0x07
#define HCI_ERR_CON_TIMEOUT 0x08
#define HCI_ERR_CON_LIMIT_EXECED 0x09
#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B
#define HCI_ERR_COMMAND_DISALLOWED 0x0C
#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D
#define HCI_ERR_CONN_REJ_BY_SEC 0x0E
#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F
#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10
#define HCI_ERR_UNSUPPORT_FEATURE 0x11
#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12
#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13
#define HCI_ERR_CON_TERM_BY_HOST 0x16
#define HCI_ERR_UNSPECIFIED_ERROR 0x1F
#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25
#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27
#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C
#define HCI_ERR_QOS_REJECTED 0x2D
#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39
/*============= HCI Error Codes End =======================*/
/* Following are event return parameters.. part of HCI events
*/
typedef struct timeout_read_t {
u8 status;
u16 timeout;
}POSTPACK TIMEOUT_INFO;
typedef struct link_supervision_timeout_read_t {
u8 status;
u16 hdl;
u16 timeout;
}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
typedef struct status_hdl_t {
u8 status;
u16 hdl;
}POSTPACK INFO_STATUS_HDL;
typedef struct write_remote_amp_assoc_t{
u8 status;
u8 hdl;
}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
typedef struct read_loc_info_t {
u8 status;
LOCATION_DATA_CFG loc;
}POSTPACK READ_LOC_INFO;
typedef struct read_flow_ctrl_mode_t {
u8 status;
u8 mode;
}POSTPACK READ_FLWCTRL_INFO;
typedef struct read_data_blk_size_t {
u8 status;
u16 max_acl_data_pkt_len;
u16 data_block_len;
u16 total_num_data_blks;
}POSTPACK READ_DATA_BLK_SIZE_INFO;
/* Read Link quality info */
typedef struct link_qual_t {
u8 status;
u16 hdl;
u8 link_qual;
} POSTPACK READ_LINK_QUAL_INFO,
READ_RSSI_INFO;
typedef struct ll_cancel_resp_t {
u8 status;
u8 phy_link_hdl;
u8 tx_flow_spec_id;
} POSTPACK LL_CANCEL_RESP;
typedef struct read_local_ver_info_t {
u8 status;
u8 hci_version;
u16 hci_revision;
u8 pal_version;
u16 manf_name;
u16 pal_sub_ver;
} POSTPACK READ_LOCAL_VER_INFO;
#endif /* __A_HCI_H__ */

8
drivers/staging/ath6kl/include/common/bmi_msg.h
View File

@ -22,10 +22,6 @@
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
@ -234,8 +230,4 @@ PREPACK struct bmi_target_info {
* Note: Not supported on all versions of ROM firmware.
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __BMI_MSG_H__ */

86
drivers/staging/ath6kl/include/common/btcoexGpio.h
View File

@ -1,86 +0,0 @@
// Copyright (c) 2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
#ifndef BTCOEX_GPIO_H_
#define BTCOEX_GPIO_H_
#ifdef FPGA
#define GPIO_A (15)
#define GPIO_B (16)
#define GPIO_C (17)
#define GPIO_D (18)
#define GPIO_E (19)
#define GPIO_F (21)
#define GPIO_G (21)
#else
#define GPIO_A (0)
#define GPIO_B (5)
#define GPIO_C (6)
#define GPIO_D (7)
#define GPIO_E (7)
#define GPIO_F (7)
#define GPIO_G (7)
#endif
#define GPIO_DEBUG_WORD_1 (1<<GPIO_A)
#define GPIO_DEBUG_WORD_2 (1<<GPIO_B)
#define GPIO_DEBUG_WORD_3 ((1<<GPIO_B) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_4 (1<<GPIO_C)
#define GPIO_DEBUG_WORD_5 ((1<<GPIO_C) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_6 ((1<<GPIO_C) | (1<<GPIO_B))
#define GPIO_DEBUG_WORD_7 ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_8 (1<<GPIO_D)
#define GPIO_DEBUG_WORD_9 ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
#define GPIO_DEBUG_WORD_10 ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
#define GPIO_DEBUG_WORD_11 ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
#define GPIO_DEBUG_WORD_12 ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
#define GPIO_DEBUG_WORD_13 ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
#define GPIO_DEBUG_WORD_14 ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
#define GPIO_DEBUG_WORD_15 ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
#define GPIO_DEBUG_WORD_16 (1<<GPIO_E)
#define GPIO_DEBUG_WORD_17 ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
#define GPIO_DEBUG_WORD_18 ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
#define GPIO_DEBUG_WORD_19 ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
#define GPIO_DEBUG_WORD_20 ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
#define GPIO_DEBUG_WORD_21 ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
#define GPIO_DEBUG_WORD_22 ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
#define GPIO_DEBUG_WORD_23 ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
extern void btcoexDbgPulseWord(u32 gpioPinMask);
extern void btcoexDbgPulse(u32 pin);
#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask))
#define BTCOEX_DBG_PULSE(pin) (btcoexDbgPulse(pin))
#else
#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
#define BTCOEX_DBG_PULSE(pin)
#endif
#endif

8
drivers/staging/ath6kl/include/common/dbglog.h
View File

@ -24,10 +24,6 @@
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -127,8 +123,4 @@ PREPACK struct dbglog_config_s {
}
#endif
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* _DBGLOG_H_ */

63
drivers/staging/ath6kl/include/common/dset_internal.h
View File

@ -1,63 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="dset_internal.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSET_INTERNAL_H__
#define __DSET_INTERNAL_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Internal dset definitions, common for DataSet layer.
*/
#define DSET_TYPE_STANDARD 0
#define DSET_TYPE_BPATCHED 1
#define DSET_TYPE_COMPRESSED 2
/* Dataset descriptor */
typedef PREPACK struct dset_descriptor_s {
struct dset_descriptor_s *next; /* List link. NULL only at the last
descriptor */
u16 id; /* Dset ID */
u16 size; /* Dset size. */
void *DataPtr; /* Pointer to raw data for standard
DataSet or pointer to original
dset_descriptor for patched
DataSet */
u32 data_type; /* DSET_TYPE_*, above */
void *AuxPtr; /* Additional data that might
needed for data_type. For
example, pointer to patch
Dataset descriptor for BPatch. */
} POSTPACK dset_descriptor_t;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSET_INTERNAL_H__ */

134
drivers/staging/ath6kl/include/common/dsetid.h
View File

@ -1,134 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="dsetid.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSETID_H__
#define __DSETID_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* Well-known DataSet IDs */
#define DSETID_UNUSED 0x00000000
#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
#define DSETID_REGDB 0x00000002 /* Regulatory Database */
#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
/*
* Get DSETID for various reference clock speeds.
* For each speed there are three DataSets that correspond
* to the three columns of bank6 data (addr, 11a, 11b/g).
* This macro returns the dsetid of the first of those
* three DataSets.
*/
#define ANALOG_CONTROL_DATA_DSETID(refclk) \
(DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
/*
* There are TWO STARTUP_PATCH DataSets.
* DSETID_STARTUP_PATCH is historical, and was applied before BMI on
* earlier systems. On AR6002, it is applied after BMI, just like
* DSETID_STARTUP_PATCH2.
*/
#define DSETID_STARTUP_PATCH 0x00000026
#define DSETID_GPIO_CONFIG_PATCH 0x00000027
#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
#define DSETID_STARTUP_PATCH2 0x00000029
#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
#define DSETID_INI_DATA 0x00000100
/* Reserved for WHAL INI Tables: 0x100..0x11f */
#define DSETID_INI_DATA_END 0x0000011f
#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
end of a memory-based
DataSet Index */
#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
/*
* PATCH DataSet format:
* A list of patches, terminated by a patch with
* address=PATCH_END.
*
* This allows for patches to be stored in flash.
*/
PREPACK struct patch_s {
u32 *address;
u32 data;
} POSTPACK ;
/*
* Skip some patches. Can be used to erase a single patch in a
* patch DataSet without having to re-write the DataSet. May
* also be used to embed information for use by subsequent
* patch code. The "data" in a PATCH_SKIP tells how many
* bytes of length "patch_s" to skip.
*/
#define PATCH_SKIP ((u32 *)0x00000000)
/*
* Execute code at the address specified by "data".
* The address of the patch structure is passed as
* the one parameter.
*/
#define PATCH_CODE_ABS ((u32 *)0x00000001)
/*
* Same as PATCH_CODE_ABS, but treat "data" as an
* offset from the start of the patch word.
*/
#define PATCH_CODE_REL ((u32 *)0x00000002)
/* Mark the end of this patch DataSet. */
#define PATCH_END ((u32 *)0xffffffff)
/*
* A DataSet which contains a Binary Patch to some other DataSet
* uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
* Such a BPatch DataSet consists of BPatch metadata followed by
* the bdiff bytes. BPatch metadata consists of a single 32-bit
* word that contains the size of the BPatched final image.
*
* To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
* to create "diffs":
* bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
* Then add BPatch metadata to the start of "diffs".
*
* NB: There are some implementation-induced restrictions
* on which DataSets can be BPatched.
*/
#define DSETID_BPATCH_FLAG 0x80000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSETID_H__ */

9
drivers/staging/ath6kl/include/common/epping_test.h
View File

@ -25,10 +25,6 @@
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(struct htc_frame_hdr) + 3) & (~0x3)) - sizeof(struct htc_frame_hdr))
@ -112,9 +108,4 @@ typedef PREPACK struct {
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /*EPPING_TEST_H_*/

8
drivers/staging/ath6kl/include/common/gmboxif.h
View File

@ -23,10 +23,6 @@
#ifndef __GMBOXIF_H__
#define __GMBOXIF_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* GMBOX interface definitions */
#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
@ -70,9 +66,5 @@ typedef PREPACK struct {
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __GMBOXIF_H__ */

45
drivers/staging/ath6kl/include/common/gpio.h
View File

@ -1,45 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#define AR6001_GPIO_PIN_COUNT 18
#define AR6002_GPIO_PIN_COUNT 18
#define AR6003_GPIO_PIN_COUNT 28
/*
* Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
* NB: These match hardware order, so that addresses can
* easily be computed.
*/
#define GPIO_ID_OUT 0x00000000
#define GPIO_ID_OUT_W1TS 0x00000001
#define GPIO_ID_OUT_W1TC 0x00000002
#define GPIO_ID_ENABLE 0x00000003
#define GPIO_ID_ENABLE_W1TS 0x00000004
#define GPIO_ID_ENABLE_W1TC 0x00000005
#define GPIO_ID_IN 0x00000006
#define GPIO_ID_STATUS 0x00000007
#define GPIO_ID_STATUS_W1TS 0x00000008
#define GPIO_ID_STATUS_W1TC 0x00000009
#define GPIO_ID_PIN0 0x0000000a
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
#define GPIO_ID_NONE 0xffffffff

9
drivers/staging/ath6kl/include/common/gpio_reg.h Normal file
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@ -0,0 +1,9 @@
#ifndef _GPIO_REG_REG_H_
#define _GPIO_REG_REG_H_
#define GPIO_PIN10_ADDRESS 0x00000050
#define GPIO_PIN11_ADDRESS 0x00000054
#define GPIO_PIN12_ADDRESS 0x00000058
#define GPIO_PIN13_ADDRESS 0x0000005c
#endif /* _GPIO_REG_H_ */

9
drivers/staging/ath6kl/include/common/htc.h
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@ -24,10 +24,6 @@
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
@ -227,10 +223,5 @@ typedef PREPACK struct {
u8 LookAhead[4]; /* 4 byte lookahead */
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

82
drivers/staging/ath6kl/include/common/ini_dset.h
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@ -1,82 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#ifndef _INI_DSET_H_
#define _INI_DSET_H_
/*
* Each of these represents a WHAL INI table, which consists
* of an "address column" followed by 1 or more "value columns".
*
* Software uses the base WHAL_INI_DATA_ID+column to access a
* DataSet that holds a particular column of data.
*/
typedef enum {
#if defined(AR6002_REV4) || defined(AR6003)
/* Add these definitions for compatibility */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */
WHAL_INI_DATA_ID_COMMON =6, /* 7 */
WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */
#ifdef FPGA
WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */
WHAL_INI_DATA_ID_ADDAC =25, /* 26 */
#else
WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
#endif /* FPGA */
#else
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
WHAL_INI_DATA_ID_COMMON =4, /* 5 */
WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */
#endif
WHAL_INI_DATA_ID_MAX =31
} WHAL_INI_DATA_ID;
typedef PREPACK struct {
u16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
u16 offset;
u32 newValue;
} POSTPACK INI_DSET_REG_OVERRIDE;
#endif

29
drivers/staging/ath6kl/include/common/regDb.h
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@ -1,29 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DB_H__
#define __REG_DB_H__
#include "./regulatory/reg_dbschema.h"
#include "./regulatory/reg_dbvalues.h"
#endif /* __REG_DB_H__ */

59
drivers/staging/ath6kl/include/common/regdump.h
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@ -1,59 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="regdump.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REGDUMP_H__
#define __REGDUMP_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6001)
#include "AR6001/AR6001_regdump.h"
#endif
#if defined(AR6002)
#include "AR6002/AR6002_regdump.h"
#endif
#if !defined(__ASSEMBLER__)
/*
* Target CPU state at the time of failure is reflected
* in a register dump, which the Host can fetch through
* the diagnostic window.
*/
PREPACK struct register_dump_s {
u32 target_id; /* Target ID */
u32 assline; /* Line number (if assertion failure) */
u32 pc; /* Program Counter at time of exception */
u32 badvaddr; /* Virtual address causing exception */
CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
/* Could copy top of stack here, too.... */
} POSTPACK;
#endif /* __ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __REGDUMP_H__ */

237
drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h
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@ -1,237 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBSCHEMA_H__
#define __REG_DBSCHEMA_H__
/*
* This file describes the regulatory DB schema, which is common between the
* 'generator' and 'parser'. The 'generator' runs on a host(typically a x86
* Linux) and spits outs two binary files, which follow the DB file
* format(described below). The resultant output "regulatoryData_AG.bin"
* is binary file which has information regarding A and G regulatory
* information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory
* information. This binary file is parsed in the target for extracting
* regulatory information.
*
* The DB values used to populate the regulatory DB are defined in
* reg_dbvalues.h
*
*/
/* Binary data file - Representation of Regulatory DB*/
#define REG_DATA_FILE_AG "./regulatoryData_AG.bin"
#define REG_DATA_FILE_G "./regulatoryData_G.bin"
/* Table tags used to encode different tables in the database */
enum data_tags_t{
REG_DMN_PAIR_MAPPING_TAG = 0,
REG_COUNTRY_CODE_TO_ENUM_RD_TAG,
REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG,
REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG,
REG_DOMAIN_TAG,
MAX_DB_TABLE_TAGS
};
/*
****************************************************************************
* Regulatory DB file format :
* 4-bytes : "RGDB" (Magic Key)
* 4-bytes : version (Default is 5379(my extn))
* 4-bytes : length of file
* dbType(4)
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* ...
* ...
****************************************************************************
*
*/
/*
* Length of the file would be filled in when the file is created and
* it would include the header size.
*/
#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */
#define REG_DB_VER 7802 /* Between 0-9999 */
/* REG_DB_VER history in reverse chronological order:
* 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09
* 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes)
* 1178: '11N' = 11 + ASCII code of N(78)
* 5379: initial version, no 11N support
*/
#define MAGIC_KEY_OFFSET 0
#define VERSION_OFFSET 4
#define FILE_SZ_OFFSET 8
#define DB_TYPE_OFFSET 12
#define MAGIC_KEY_SZ 4
#define VERSION_SZ 4
#define FILE_SZ_SZ 4
#define DB_TYPE_SZ 4
#define DB_TAG_SZ 4
#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET)
#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET)
#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET))
#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET)
#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_)
#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) )
/* A Table can be search based on key as a parameter or accessed directly
* by giving its index in to the table.
*/
enum searchType {
KEY_BASED_TABLE_SEARCH = 1,
INDEX_BASED_TABLE_ACCESS
};
/* Data is organised as different tables. There is a Master table, which
* holds information regarding all the tables. It does not have any
* knowledge about the attributes of the table it is holding
* but has external view of the same(for ex, how many entries, record size,
* how to search the table, total table size and reference to the data
* instance of table).
*/
typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */
u8 numOfEntries;
char entrySize; /* Entry size per table row */
char searchType; /* Index based access or key based */
char reserved[3]; /* for alignment */
u16 tableSize; /* Size of this table */
char *dataPtr; /* Ptr to the actual Table */
} POSTPACK dbMasterTable; /* Master table - table of tables */
/* used to get the number of rows in a table */
#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0]))
/*
* Used to set the RegDomain bitmask which chooses which frequency
* band specs are used.
*/
#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */
#define BMZERO {0,0} /* BMLEN zeros */
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
{((((_fa >= 0) && (_fa < 32)) ? (((u32) 1) << _fa) : 0) | \
(((_fb >= 0) && (_fb < 32)) ? (((u32) 1) << _fb) : 0) | \
(((_fc >= 0) && (_fc < 32)) ? (((u32) 1) << _fc) : 0) | \
(((_fd >= 0) && (_fd < 32)) ? (((u32) 1) << _fd) : 0) | \
(((_fe >= 0) && (_fe < 32)) ? (((u32) 1) << _fe) : 0) | \
(((_ff >= 0) && (_ff < 32)) ? (((u32) 1) << _ff) : 0) | \
(((_fg >= 0) && (_fg < 32)) ? (((u32) 1) << _fg) : 0) | \
(((_fh >= 0) && (_fh < 32)) ? (((u32) 1) << _fh) : 0)), \
((((_fa > 31) && (_fa < 64)) ? (((u32) 1) << (_fa - 32)) : 0) | \
(((_fb > 31) && (_fb < 64)) ? (((u32) 1) << (_fb - 32)) : 0) | \
(((_fc > 31) && (_fc < 64)) ? (((u32) 1) << (_fc - 32)) : 0) | \
(((_fd > 31) && (_fd < 64)) ? (((u32) 1) << (_fd - 32)) : 0) | \
(((_fe > 31) && (_fe < 64)) ? (((u32) 1) << (_fe - 32)) : 0) | \
(((_ff > 31) && (_ff < 64)) ? (((u32) 1) << (_ff - 32)) : 0) | \
(((_fg > 31) && (_fg < 64)) ? (((u32) 1) << (_fg - 32)) : 0) | \
(((_fh > 31) && (_fh < 64)) ? (((u32) 1) << (_fh - 32)) : 0))}
/*
* THE following table is the mapping of regdomain pairs specified by
* a regdomain value to the individual unitary reg domains
*/
typedef PREPACK struct reg_dmn_pair_mapping {
u16 regDmnEnum; /* 16 bit reg domain pair */
u16 regDmn5GHz; /* 5GHz reg domain */
u16 regDmn2GHz; /* 2GHz reg domain */
u8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */
u8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */
u32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
flags. This value is used as a mask on the unitary flags*/
} POSTPACK REG_DMN_PAIR_MAPPING;
#define OFDM_YES (1 << 0)
#define OFDM_NO (0 << 0)
#define MCS_HT20_YES (1 << 1)
#define MCS_HT20_NO (0 << 1)
#define MCS_HT40_A_YES (1 << 2)
#define MCS_HT40_A_NO (0 << 2)
#define MCS_HT40_G_YES (1 << 3)
#define MCS_HT40_G_NO (0 << 3)
typedef PREPACK struct {
u16 countryCode;
u16 regDmnEnum;
char isoName[3];
char allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */
} POSTPACK COUNTRY_CODE_TO_ENUM_RD;
/* lower 16 bits of ht40ChanMask */
#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */
#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */
#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */
#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */
#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */
#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */
#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */
#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */
/* upper 16 bits of ht40ChanMask */
#define FREQ_HALF_RATE 0x10000
#define FREQ_QUARTER_RATE 0x20000
typedef PREPACK struct RegDmnFreqBand {
u16 lowChannel; /* Low channel center in MHz */
u16 highChannel; /* High Channel center in MHz */
u8 power; /* Max power (dBm) for channel range */
u8 channelSep; /* Channel separation within the band */
u8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */
u8 mode; /* Mode of operation */
u32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
u32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
upper 16 bits: what rate (half/quarter) the channel is */
} POSTPACK REG_DMN_FREQ_BAND;
typedef PREPACK struct regDomain {
u16 regDmnEnum; /* value from EnumRd table */
u8 rdCTL;
u8 maxAntGain;
u8 dfsMask; /* DFS bitmask for 5Ghz tables */
u8 flags; /* Requirement flags (AdHoc disallow etc) */
u16 reserved; /* for alignment */
u32 pscan; /* Bitmask for passive scan */
u32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
u32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
} POSTPACK REG_DOMAIN;
#endif /* __REG_DBSCHEMA_H__ */

504
drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h
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@ -1,504 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBVALUE_H__
#define __REG_DBVALUE_H__
/*
* Numbering from ISO 3166
*/
enum CountryCode {
CTRY_ALBANIA = 8, /* Albania */
CTRY_ALGERIA = 12, /* Algeria */
CTRY_ARGENTINA = 32, /* Argentina */
CTRY_ARMENIA = 51, /* Armenia */
CTRY_ARUBA = 533, /* Aruba */
CTRY_AUSTRALIA = 36, /* Australia (for STA) */
CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */
CTRY_AUSTRIA = 40, /* Austria */
CTRY_AZERBAIJAN = 31, /* Azerbaijan */
CTRY_BAHRAIN = 48, /* Bahrain */
CTRY_BANGLADESH = 50, /* Bangladesh */
CTRY_BARBADOS = 52, /* Barbados */
CTRY_BELARUS = 112, /* Belarus */
CTRY_BELGIUM = 56, /* Belgium */
CTRY_BELIZE = 84, /* Belize */
CTRY_BOLIVIA = 68, /* Bolivia */
CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */
CTRY_BRAZIL = 76, /* Brazil */
CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
CTRY_BULGARIA = 100, /* Bulgaria */
CTRY_CAMBODIA = 116, /* Cambodia */
CTRY_CANADA = 124, /* Canada (for STA) */
CTRY_CANADA_AP = 5001, /* Canada (for AP) */
CTRY_CHILE = 152, /* Chile */
CTRY_CHINA = 156, /* People's Republic of China */
CTRY_COLOMBIA = 170, /* Colombia */
CTRY_COSTA_RICA = 188, /* Costa Rica */
CTRY_CROATIA = 191, /* Croatia */
CTRY_CYPRUS = 196,
CTRY_CZECH = 203, /* Czech Republic */
CTRY_DENMARK = 208, /* Denmark */
CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
CTRY_ECUADOR = 218, /* Ecuador */
CTRY_EGYPT = 818, /* Egypt */
CTRY_EL_SALVADOR = 222, /* El Salvador */
CTRY_ESTONIA = 233, /* Estonia */
CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
CTRY_FINLAND = 246, /* Finland */
CTRY_FRANCE = 250, /* France */
CTRY_FRANCE2 = 255, /* France2 */
CTRY_GEORGIA = 268, /* Georgia */
CTRY_GERMANY = 276, /* Germany */
CTRY_GREECE = 300, /* Greece */
CTRY_GREENLAND = 304, /* Greenland */
CTRY_GRENADA = 308, /* Grenada */
CTRY_GUAM = 316, /* Guam */
CTRY_GUATEMALA = 320, /* Guatemala */
CTRY_HAITI = 332, /* Haiti */
CTRY_HONDURAS = 340, /* Honduras */
CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
CTRY_HUNGARY = 348, /* Hungary */
CTRY_ICELAND = 352, /* Iceland */
CTRY_INDIA = 356, /* India */
CTRY_INDONESIA = 360, /* Indonesia */
CTRY_IRAN = 364, /* Iran */
CTRY_IRAQ = 368, /* Iraq */
CTRY_IRELAND = 372, /* Ireland */
CTRY_ISRAEL = 376, /* Israel */
CTRY_ITALY = 380, /* Italy */
CTRY_JAMAICA = 388, /* Jamaica */
CTRY_JAPAN = 392, /* Japan */
CTRY_JAPAN1 = 393, /* Japan (JP1) */
CTRY_JAPAN2 = 394, /* Japan (JP0) */
CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
CTRY_JAPAN4 = 396, /* Japan (JE1) */
CTRY_JAPAN5 = 397, /* Japan (JE2) */
CTRY_JAPAN6 = 399, /* Japan (JP6) */
CTRY_JORDAN = 400, /* Jordan */
CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
CTRY_KENYA = 404, /* Kenya */
CTRY_KOREA_NORTH = 408, /* North Korea */
CTRY_KOREA_ROC = 410, /* South Korea (for STA) */
CTRY_KOREA_ROC2 = 411, /* South Korea */
CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */
CTRY_KUWAIT = 414, /* Kuwait */
CTRY_LATVIA = 428, /* Latvia */
CTRY_LEBANON = 422, /* Lebanon */
CTRY_LIBYA = 434, /* Libya */
CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
CTRY_LITHUANIA = 440, /* Lithuania */
CTRY_LUXEMBOURG = 442, /* Luxembourg */
CTRY_MACAU = 446, /* Macau */
CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */
CTRY_MALAYSIA = 458, /* Malaysia */
CTRY_MALTA = 470, /* Malta */
CTRY_MEXICO = 484, /* Mexico */
CTRY_MONACO = 492, /* Principality of Monaco */
CTRY_MOROCCO = 504, /* Morocco */
CTRY_NEPAL = 524, /* Nepal */
CTRY_NETHERLANDS = 528, /* Netherlands */
CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */
CTRY_NEW_ZEALAND = 554, /* New Zealand */
CTRY_NICARAGUA = 558, /* Nicaragua */
CTRY_NORWAY = 578, /* Norway */
CTRY_OMAN = 512, /* Oman */
CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
CTRY_PANAMA = 591, /* Panama */
CTRY_PARAGUAY = 600, /* Paraguay */
CTRY_PERU = 604, /* Peru */
CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
CTRY_POLAND = 616, /* Poland */
CTRY_PORTUGAL = 620, /* Portugal */
CTRY_PUERTO_RICO = 630, /* Puerto Rico */
CTRY_QATAR = 634, /* Qatar */
CTRY_ROMANIA = 642, /* Romania */
CTRY_RUSSIA = 643, /* Russia */
CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
CTRY_MONTENEGRO = 891, /* Montenegro */
CTRY_SINGAPORE = 702, /* Singapore */
CTRY_SLOVAKIA = 703, /* Slovak Republic */
CTRY_SLOVENIA = 705, /* Slovenia */
CTRY_SOUTH_AFRICA = 710, /* South Africa */
CTRY_SPAIN = 724, /* Spain */
CTRY_SRILANKA = 144, /* Sri Lanka */
CTRY_SWEDEN = 752, /* Sweden */
CTRY_SWITZERLAND = 756, /* Switzerland */
CTRY_SYRIA = 760, /* Syria */
CTRY_TAIWAN = 158, /* Taiwan */
CTRY_THAILAND = 764, /* Thailand */
CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
CTRY_TUNISIA = 788, /* Tunisia */
CTRY_TURKEY = 792, /* Turkey */
CTRY_UAE = 784, /* U.A.E. */
CTRY_UKRAINE = 804, /* Ukraine */
CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
CTRY_UNITED_STATES = 840, /* United States (for STA) */
CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */
CTRY_UNITED_STATES_PS = 842, /* United States - public safety */
CTRY_URUGUAY = 858, /* Uruguay */
CTRY_UZBEKISTAN = 860, /* Uzbekistan */
CTRY_VENEZUELA = 862, /* Venezuela */
CTRY_VIET_NAM = 704, /* Viet Nam */
CTRY_YEMEN = 887, /* Yemen */
CTRY_ZIMBABWE = 716 /* Zimbabwe */
};
#define CTRY_DEBUG 0
#define CTRY_DEFAULT 0x1ff
/*
* The following regulatory domain definitions are
* found in the EEPROM. Each regulatory domain
* can operate in either a 5GHz or 2.4GHz wireless mode or
* both 5GHz and 2.4GHz wireless modes.
* In general, the value holds no special
* meaning and is used to decode into either specific
* 2.4GHz or 5GHz wireless mode for that particular
* regulatory domain.
*
* Enumerated Regulatory Domain Information 8 bit values indicate that
* the regdomain is really a pair of unitary regdomains. 12 bit values
* are the real unitary regdomains and are the only ones which have the
* frequency bitmasks and flags set.
*/
enum EnumRd {
NO_ENUMRD = 0x00,
NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */
NULL1_ETSIB = 0x07, /* Israel */
NULL1_ETSIC = 0x08,
FCC1_FCCA = 0x10, /* USA */
FCC1_WORLD = 0x11, /* Hong Kong */
FCC2_FCCA = 0x20, /* Canada */
FCC2_WORLD = 0x21, /* Australia & HK */
FCC2_ETSIC = 0x22,
FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */
FCC5_FCCA = 0x13, /* US with no DFS */
FCC5_WORLD = 0x16, /* US with no DFS */
FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */
FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */
ETSI1_WORLD = 0x37,
ETSI2_WORLD = 0x35, /* Hungary & others */
ETSI3_WORLD = 0x36, /* France & others */
ETSI4_WORLD = 0x30,
ETSI4_ETSIC = 0x38,
ETSI5_WORLD = 0x39,
ETSI6_WORLD = 0x34, /* Bulgaria */
ETSI_RESERVED = 0x33, /* Reserved (Do not used) */
FRANCE_RES = 0x31, /* Legacy France for OEM */
APL6_WORLD = 0x5B, /* Singapore */
APL4_WORLD = 0x42, /* Singapore */
APL3_FCCA = 0x50,
APL_RESERVED = 0x44, /* Reserved (Do not used) */
APL2_WORLD = 0x45, /* Korea */
APL2_APLC = 0x46,
APL3_WORLD = 0x47,
APL2_APLD = 0x49, /* Korea with 2.3G channels */
APL2_FCCA = 0x4D, /* Specific Mobile Customer */
APL1_WORLD = 0x52, /* Latin America */
APL1_FCCA = 0x53,
APL1_ETSIC = 0x55,
APL2_ETSIC = 0x56, /* Venezuela */
APL5_WORLD = 0x58, /* Chile */
APL7_FCCA = 0x5C,
APL8_WORLD = 0x5D,
APL9_WORLD = 0x5E,
APL10_WORLD = 0x5F, /* Korea 5GHz for STA */
MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */
MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */
MKK5_MKKC = 0x88,
MKK11_MKKA = 0xD4,
MKK11_FCCA = 0xD5,
MKK11_MKKC = 0xD7,
/*
* World mode SKUs
*/
WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */
WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */
WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */
WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */
WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */
WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */
WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */
WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */
EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */
WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */
/*
* Regulator domains ending in a number (e.g. APL1,
* MK1, ETSI4, etc) apply to 5GHz channel and power
* information. Regulator domains ending in a letter
* (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
* power information.
*/
APL1 = 0x0150, /* LAT & Asia */
APL2 = 0x0250, /* LAT & Asia */
APL3 = 0x0350, /* Taiwan */
APL4 = 0x0450, /* Jordan */
APL5 = 0x0550, /* Chile */
APL6 = 0x0650, /* Singapore */
APL7 = 0x0750, /* Taiwan */
APL8 = 0x0850, /* Malaysia */
APL9 = 0x0950, /* Korea */
APL10 = 0x1050, /* Korea 5GHz */
ETSI1 = 0x0130, /* Europe & others */
ETSI2 = 0x0230, /* Europe & others */
ETSI3 = 0x0330, /* Europe & others */
ETSI4 = 0x0430, /* Europe & others */
ETSI5 = 0x0530, /* Europe & others */
ETSI6 = 0x0630, /* Europe & others */
ETSIB = 0x0B30, /* Israel */
ETSIC = 0x0C30, /* Latin America */
FCC1 = 0x0110, /* US & others */
FCC2 = 0x0120, /* Canada, Australia & New Zealand */
FCC3 = 0x0160, /* US w/new middle band & DFS */
FCC4 = 0x0165,
FCC5 = 0x0180,
FCC6 = 0x0610,
FCCA = 0x0A10,
APLD = 0x0D50, /* South Korea */
MKK1 = 0x0140, /* Japan */
MKK2 = 0x0240, /* Japan Extended */
MKK3 = 0x0340, /* Japan new 5GHz */
MKK4 = 0x0440, /* Japan new 5GHz */
MKK5 = 0x0540, /* Japan new 5GHz */
MKK6 = 0x0640, /* Japan new 5GHz */
MKK7 = 0x0740, /* Japan new 5GHz */
MKK8 = 0x0840, /* Japan new 5GHz */
MKK9 = 0x0940, /* Japan new 5GHz */
MKK10 = 0x1040, /* Japan new 5GHz */
MKK11 = 0x1140, /* Japan new 5GHz */
MKK12 = 0x1240, /* Japan new 5GHz */
MKKA = 0x0A40, /* Japan */
MKKC = 0x0A50,
NULL1 = 0x0198,
WORLD = 0x0199,
DEBUG_REG_DMN = 0x01ff,
UNINIT_REG_DMN = 0x0fff,
};
enum { /* conformance test limits */
FCC = 0x10,
MKK = 0x40,
ETSI = 0x30,
NO_CTL = 0xff,
CTL_11B = 1,
CTL_11G = 2
};
/*
* The following are flags for different requirements per reg domain.
* These requirements are either inhereted from the reg domain pair or
* from the unitary reg domain if the reg domain pair flags value is
* 0
*/
enum {
NO_REQ = 0x00,
DISALLOW_ADHOC_11A = 0x01,
ADHOC_PER_11D = 0x02,
ADHOC_NO_11A = 0x04,
DISALLOW_ADHOC_11G = 0x08
};
/*
* The following describe the bit masks for different passive scan
* capability/requirements per regdomain.
*/
#define NO_PSCAN 0x00000000
#define PSCAN_FCC 0x00000001
#define PSCAN_ETSI 0x00000002
#define PSCAN_MKK 0x00000004
#define PSCAN_ETSIB 0x00000008
#define PSCAN_ETSIC 0x00000010
#define PSCAN_WWR 0x00000020
#define PSCAN_DEFER 0xFFFFFFFF
/* Bit masks for DFS per regdomain */
enum {
NO_DFS = 0x00,
DFS_FCC3 = 0x01,
DFS_ETSI = 0x02,
DFS_MKK = 0x04
};
#define DEF_REGDMN FCC1_FCCA
/*
* The following table is the master list for all different freqeuncy
* bands with the complete matrix of all possible flags and settings
* for each band if it is used in ANY reg domain.
*
* The table of frequency bands is indexed by a bitmask. The ordering
* must be consistent with the enum below. When adding a new
* frequency band, be sure to match the location in the enum with the
* comments
*/
/*
* These frequency values are as per channel tags and regulatory domain
* info. Please update them as database is updated.
*/
#define A_FREQ_MIN 4920
#define A_FREQ_MAX 5825
#define A_CHAN0_FREQ 5000
#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5)
#define BG_FREQ_MIN 2412
#define BG_FREQ_MAX 2484
#define BG_CHAN0_FREQ 2407
#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5)
#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */
#define A_20MHZ_BAND_FREQ_MAX 5000
/*
* 5GHz 11A channel tags
*/
enum {
F1_4920_4980,
F1_5040_5080,
F1_5120_5240,
F1_5180_5240,
F2_5180_5240,
F3_5180_5240,
F4_5180_5240,
F5_5180_5240,
F6_5180_5240,
F7_5180_5240,
F1_5260_5280,
F1_5260_5320,
F2_5260_5320,
F3_5260_5320,
F4_5260_5320,
F5_5260_5320,
F6_5260_5320,
F1_5260_5700,
F1_5280_5320,
F1_5500_5620,
F1_5500_5700,
F2_5500_5700,
F3_5500_5700,
F4_5500_5700,
F5_5500_5700,
F6_5500_5700,
F7_5500_5700,
F1_5745_5805,
F2_5745_5805,
F1_5745_5825,
F2_5745_5825,
F3_5745_5825,
F4_5745_5825,
F5_5745_5825,
F6_5745_5825,
W1_4920_4980,
W1_5040_5080,
W1_5170_5230,
W1_5180_5240,
W1_5260_5320,
W1_5745_5825,
W1_5500_5700,
};
/* 2.4 GHz table - for 11b and 11g info */
enum {
BG1_2312_2372,
BG2_2312_2372,
BG1_2412_2472,
BG2_2412_2472,
BG3_2412_2472,
BG4_2412_2472,
BG1_2412_2462,
BG2_2412_2462,
BG1_2432_2442,
BG1_2457_2472,
BG1_2467_2472,
BG1_2484_2484, /* No G */
BG2_2484_2484, /* No G */
BG1_2512_2732,
WBG1_2312_2372,
WBG1_2412_2412,
WBG1_2417_2432,
WBG1_2437_2442,
WBG1_2447_2457,
WBG1_2462_2462,
WBG1_2467_2467,
WBG2_2467_2467,
WBG1_2472_2472,
WBG2_2472_2472,
WBG1_2484_2484, /* No G */
WBG2_2484_2484, /* No G */
};
#endif /* __REG_DBVALUE_H__ */

234
drivers/staging/ath6kl/include/common/targaddrs.h
View File

@ -22,10 +22,6 @@
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6002)
#include "AR6002/addrs.h"
#endif
@ -91,15 +87,7 @@ PREPACK struct host_interest_s {
/* Pointer to debug logging header */
u32 hi_dbglog_hdr; /* 0x08 */
/* Indicates whether or not flash is present on Target.
* NB: flash_is_present indicator is here not just
* because it might be of interest to the Host; but
* also because it's set early on by Target's startup
* asm code and we need it to have a special RAM address
* so that it doesn't get reinitialized with the rest
* of data.
*/
u32 hi_flash_is_present; /* 0x0c */
u32 hi_unused1; /* 0x0c */
/*
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
@ -113,7 +101,7 @@ PREPACK struct host_interest_s {
*/
u32 hi_serial_enable; /* 0x14 */
/* Start address of Flash DataSet index, if any */
/* Start address of DataSet index, if any */
u32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
@ -171,35 +159,179 @@ PREPACK struct host_interest_s {
u32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [0]: 1 = enable, 0 = disable
* [1]: 0 = UART FC active low, 1 = UART FC active high
* 0xa9 - [7:0]: wakeup timeout in ms
* 0xaa, 0xab - [15:0]: idle timeout in ms
*/
/* Pointer to extended board Data */
u32 hi_board_ext_data; /* 0xac */
u32 hi_board_ext_data_initialized; /* 0xb0 */
/*
* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board data */
u32 hi_board_ext_data; /* 0xac */
u32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
u32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
u32 hi_reset_flag_valid; /* 0xb8 */
u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/*
* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
u32 hi_acs_flags; /* 0xc0 */
u32 hi_console_flags; /* 0xc4 */
u32 hi_nvram_state; /* 0xc8 */
u32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
u32 hi_sw_version_override; /* 0xd0 */
u32 hi_abi_version_override; /* 0xd4 */
/*
* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004
*/
u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
u32 hi_test_apps_related ; /* 0xdc */
/* location of test script */
u32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
u32 hi_cal_data; /* 0xe4 */
/* Number of packet log buffers */
u32 hi_pktlog_num_buffers; /* 0xe8 */
} POSTPACK;
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */
#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
/* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_MAC_ADDR_METHOD 0x08
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
/* Disable LowFreq Timer Stabilization */
#define HI_OPTION_NO_LFT_STBL 0x10000000
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
/* Do regulatory scan during init beforesending WMI ready event to host */
#define HI_OPTION_INIT_REG_SCAN 0x40000000
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory
map */
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
/* Fw Mode Mask */
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0x3
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
#define HI_OPTION_NUM_DEV_SHIFT 0x9
/* firmware bridging */
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
|------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
#define HI_OPTION_FW_SUBMODE_BITS 0x2
#define HI_OPTION_FW_SUBMODE_MASK 0x3
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_reset_flag */
/* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01
/* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is
valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define ON_RESET_PRESERVE_BOOT_INFO() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
/* CONSOLE FLAGS
*
* Bit Range Meaning
* --------- --------------------------------
* 2..0 UART ID (0 = Default)
* 3 Baud Select (0 = 9600, 1 = 115200)
* 30..4 Reserved
* 31 Enable Console
*
*/
#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
#define HI_CONSOLE_FLAGS_UART_SHIFT 0
#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
/*
* Intended for use by Host software, this macro returns the Target RAM
@ -212,34 +344,52 @@ PREPACK struct host_interest_s {
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
((u32)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
((HOST_INTEREST->hi_pktlog_num_buffers))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
#define HOST_INTEREST_DFS_IS_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
/* override REV2 ROM's app start address */
#define AR6002_REV2_APP_START_OVERRIDE 0x911A00
#define AR6003_REV1_APP_START_OVERRIDE 0x944c00
#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800
#define AR6003_REV2_APP_START_OVERRIDE 0x945000
#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800
#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
#define AR6003_REV2_APP_START_OVERRIDE 0x944C00
#define AR6003_REV2_APP_LOAD_ADDRESS 0x543180
#define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500
#define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884
#define AR6003_REV2_RAM_RESERVE_SIZE 6912
#define AR6003_REV3_APP_START_OVERRIDE 0x945d00
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
#define AR6003_REV3_RAM_RESERVE_SIZE 512
#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
/* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __TARGADDRS_H__ */

33
drivers/staging/ath6kl/include/common/wlan_dset.h
View File

@ -1,33 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __WLAN_DSET_H__
#define __WLAN_DSET_H__
typedef PREPACK struct wow_config_dset {
u8 valid_dset;
u8 gpio_enable;
u16 gpio_pin;
} POSTPACK WOW_CONFIG_DSET;
#endif

133
drivers/staging/ath6kl/include/common/wmi.h
View File

@ -34,10 +34,6 @@
#ifndef _WMI_H_
#define _WMI_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#include "wmix.h"
#include "wlan_defs.h"
@ -118,7 +114,7 @@ typedef enum {
typedef enum {
WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
WMI_DATA_HDR_DATA_TYPE_802_11,
WMI_DATA_HDR_DATA_TYPE_ACL,
WMI_DATA_HDR_DATA_TYPE_ACL, /* used to be used for the PAL */
} WMI_DATA_HDR_DATA_TYPE;
#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3
@ -159,6 +155,16 @@ typedef enum {
#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK)
#define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT))
/* Macros for operating on WMI_DATA_HDR (info3) field */
#define WMI_DATA_HDR_DEVID_MASK 0xF
#define WMI_DATA_HDR_DEVID_SHIFT 0
#define GET_DEVID(_v) ((_v) & WMI_DATA_HDR_DEVID_MASK)
#define WMI_DATA_HDR_GET_DEVID(h) \
(((h)->info3 >> WMI_DATA_HDR_DEVID_SHIFT) & WMI_DATA_HDR_DEVID_MASK)
#define WMI_DATA_HDR_SET_DEVID(h, _v) \
((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_DEVID_MASK << WMI_DATA_HDR_DEVID_SHIFT)) | (GET_DEVID(_v) << WMI_DATA_HDR_DEVID_SHIFT))
typedef PREPACK struct {
s8 rssi;
u8 info; /* usage of 'info' field(8-bit):
@ -175,7 +181,7 @@ typedef PREPACK struct {
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
u16 reserved;
u16 info3;
} POSTPACK WMI_DATA_HDR;
/*
@ -259,6 +265,17 @@ typedef PREPACK struct {
#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF)
/* Macros for operating on WMI_CMD_HDR (info1) field */
#define WMI_CMD_HDR_DEVID_MASK 0xF
#define WMI_CMD_HDR_DEVID_SHIFT 0
#define GET_CMD_DEVID(_v) ((_v) & WMI_CMD_HDR_DEVID_MASK)
#define WMI_CMD_HDR_GET_DEVID(h) \
(((h)->info1 >> WMI_CMD_HDR_DEVID_SHIFT) & WMI_CMD_HDR_DEVID_MASK)
#define WMI_CMD_HDR_SET_DEVID(h, _v) \
((h)->info1 = ((h)->info1 & \
~(WMI_CMD_HDR_DEVID_MASK << WMI_CMD_HDR_DEVID_SHIFT)) | \
(GET_CMD_DEVID(_v) << WMI_CMD_HDR_DEVID_SHIFT))
/*
* Control Path
@ -433,13 +450,47 @@ typedef enum {
WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID,
WMI_GET_BTCOEX_STATS_CMDID,
WMI_GET_BTCOEX_CONFIG_CMDID,
WMI_GET_PMK_CMDID,
WMI_SET_PASSPHRASE_CMDID,
WMI_ENABLE_WAC_CMDID,
WMI_WAC_SCAN_REPLY_CMDID,
WMI_WAC_CTRL_REQ_CMDID,
WMI_SET_DIV_PARAMS_CMDID,
WMI_SET_EXCESS_TX_RETRY_THRES_CMDID,
WMI_SET_DFS_ENABLE_CMDID, /* F034 */
WMI_SET_DFS_MINRSSITHRESH_CMDID,
WMI_SET_DFS_MAXPULSEDUR_CMDID,
WMI_DFS_RADAR_DETECTED_CMDID,
/* P2P CMDS */
WMI_P2P_SET_CONFIG_CMDID, /* F038 */
WMI_WPS_SET_CONFIG_CMDID,
WMI_SET_REQ_DEV_ATTR_CMDID,
WMI_P2P_FIND_CMDID,
WMI_P2P_STOP_FIND_CMDID,
WMI_P2P_GO_NEG_START_CMDID,
WMI_P2P_LISTEN_CMDID,
WMI_CONFIG_TX_MAC_RULES_CMDID, /* F040 */
WMI_SET_PROMISCUOUS_MODE_CMDID,
WMI_RX_FRAME_FILTER_CMDID,
WMI_SET_CHANNEL_CMDID,
/* WAC commands */
WMI_ENABLE_WAC_CMDID,
WMI_WAC_SCAN_REPLY_CMDID,
WMI_WAC_CTRL_REQ_CMDID,
WMI_SET_DIV_PARAMS_CMDID,
WMI_GET_PMK_CMDID,
WMI_SET_PASSPHRASE_CMDID,
WMI_SEND_ASSOC_RES_CMDID,
WMI_SET_ASSOC_REQ_RELAY_CMDID,
WMI_GET_RFKILL_MODE_CMDID,
/* ACS command, consists of sub-commands */
WMI_ACS_CTRL_CMDID,
/* Ultra low power store / recall commands */
WMI_STORERECALL_CONFIGURE_CMDID,
WMI_STORERECALL_RECALL_CMDID,
WMI_STORERECALL_HOST_READY_CMDID,
WMI_FORCE_TARGET_ASSERT_CMDID,
WMI_SET_EXCESS_TX_RETRY_THRES_CMDID,
} WMI_COMMAND_ID;
/*
@ -470,6 +521,11 @@ typedef enum {
LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */
} DOT11_AUTH_MODE;
enum {
AUTH_IDLE,
AUTH_OPEN_IN_PROGRESS,
};
typedef enum {
NONE_AUTH = 0x01,
WPA_AUTH = 0x02,
@ -560,7 +616,7 @@ typedef PREPACK struct {
* WMI_SET_EXCESS_TX_RETRY_THRES_CMDID
*/
typedef PREPACK struct {
A_UINT32 threshold;
u32 threshold;
} POSTPACK WMI_SET_EXCESS_TX_RETRY_THRES_CMD;
/*
@ -1969,12 +2025,47 @@ typedef enum {
#endif
WMI_REPORT_BTCOEX_STATS_EVENTID,
WMI_REPORT_BTCOEX_CONFIG_EVENTID,
WMI_ACM_REJECT_EVENTID,
WMI_THIN_RESERVED_START_EVENTID = 0x8000,
/* Events in this range are reserved for thinmode
* See wmi_thin.h for actual definitions */
WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
WMI_GET_PMK_EVENTID,
/* DFS Events */
WMI_DFS_HOST_ATTACH_EVENTID,
WMI_DFS_HOST_INIT_EVENTID,
WMI_DFS_RESET_DELAYLINES_EVENTID,
WMI_DFS_RESET_RADARQ_EVENTID,
WMI_DFS_RESET_AR_EVENTID,
WMI_DFS_RESET_ARQ_EVENTID,
WMI_DFS_SET_DUR_MULTIPLIER_EVENTID,
WMI_DFS_SET_BANGRADAR_EVENTID,
WMI_DFS_SET_DEBUGLEVEL_EVENTID,
WMI_DFS_PHYERR_EVENTID,
/* CCX Evants */
WMI_CCX_RM_STATUS_EVENTID,
/* P2P Events */
WMI_P2P_GO_NEG_RESULT_EVENTID,
WMI_WAC_SCAN_DONE_EVENTID,
WMI_WAC_REPORT_BSS_EVENTID,
WMI_WAC_START_WPS_EVENTID,
WMI_WAC_CTRL_REQ_REPLY_EVENTID,
/* RFKILL Events */
WMI_RFKILL_STATE_CHANGE_EVENTID,
WMI_RFKILL_GET_MODE_CMD_EVENTID,
WMI_THIN_RESERVED_START_EVENTID = 0x8000,
/*
* Events in this range are reserved for thinmode
* See wmi_thin.h for actual definitions
*/
WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
WMI_SET_CHANNEL_EVENTID,
WMI_ASSOC_REQ_EVENTID,
/* generic ACS event */
WMI_ACS_EVENTID,
WMI_REPORT_WMM_PARAMS_EVENTID
} WMI_EVENT_ID;
@ -3122,10 +3213,6 @@ typedef PREPACK struct {
* End of AP mode definitions
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#ifdef __cplusplus
}
#endif

347
drivers/staging/ath6kl/include/common/wmi_thin.h
View File

@ -1,347 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="wmi_thin.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
/*
* This file contains the definitions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all the
* commands and events. Commands are messages from the host to the WM.
* Events and Replies are messages from the WM to the host.
*
* Ownership of correctness in regards to WMI commands
* belongs to the host driver and the WM is not required to validate
* parameters for value, proper range, or any other checking.
*
*/
#ifndef _WMI_THIN_H_
#define _WMI_THIN_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START
WMI_THIN_SET_MIB_CMDID,
WMI_THIN_GET_MIB_CMDID,
WMI_THIN_JOIN_CMDID,
/* add new CMDID's here */
WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
} WMI_THIN_COMMAND_ID;
typedef enum{
TEMPLATE_FRM_FIRST = 0,
TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
TEMPLATE_FRM_BEACON,
TEMPLATE_FRM_PROBE_RESP,
TEMPLATE_FRM_NULL,
TEMPLATE_FRM_QOS_NULL,
TEMPLATE_FRM_PSPOLL,
TEMPLATE_FRM_MAX
}WMI_TEMPLATE_FRM_TYPE;
/* TEMPLATE_FRM_LEN... represent the maximum allowable
* data lengths (bytes) for each frame type */
#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
#define TEMPLATE_FRM_LEN_BEACON (256)
#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
#define TEMPLATE_FRM_LEN_NULL (32)
#define TEMPLATE_FRM_LEN_QOS_NULL (32)
#define TEMPLATE_FRM_LEN_PSPOLL (32)
#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
/* MAC Header Build Rules */
/* These values allow the host to configure the
* target code that is responsible for constructing
* the MAC header. In cases where the MAC header
* is provided by the host framework, the target
* has a diminished responsibility over what fields
* it must write. This will vary from framework to framework.
* Symbian requires different behavior from MAC80211 which
* requires different behavior from MS Native Wifi. */
#define WMI_WRT_VER_TYPE 0x00000001
#define WMI_WRT_DURATION 0x00000002
#define WMI_WRT_DIRECTION 0x00000004
#define WMI_WRT_POWER 0x00000008
#define WMI_WRT_WEP 0x00000010
#define WMI_WRT_MORE 0x00000020
#define WMI_WRT_BSSID 0x00000040
#define WMI_WRT_QOS 0x00000080
#define WMI_WRT_SEQNO 0x00000100
#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */
#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for
* TX Complete messages the will come from the Target. these messages are
* disabled by default but can be enabled using this structure and the
* WMI_THIN_CONFIG_CMDID. */
typedef PREPACK struct {
u8 version; /* the versioned type of messages to use or 0 to disable */
u8 countThreshold; /* msg count threshold triggering a tx complete message */
u16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */
} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames
* that have decryption errors. The default behavior is to discard the frame
* without notification. Alternately, the MAC Header is forwarded to the host
* with the failed status. */
typedef PREPACK struct {
u8 enable; /* 1 == send decrypt errors to the host, 0 == don't */
u8 reserved[3]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
* frames that require partial MAC header construction. These rules
* are used by the target to indicate which fields need to be written. */
typedef PREPACK struct {
u32 rules; /* combination of WMI_WRT_... values */
} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
* frames as to which frames should get forwarded to the host and which
* should get processed internally. */
typedef PREPACK struct {
u32 rules; /* combination of WMI_FILT_... values */
} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
* WMI_THIN_CONFIG_... structures. The actual combination is indicated
* by the value of cfgField. Each bit in this field corresponds to
* one of the above structures. */
typedef PREPACK struct {
#define WMI_THIN_CFG_TXCOMP 0x00000001
#define WMI_THIN_CFG_DECRYPT 0x00000002
#define WMI_THIN_CFG_MAC_RULES 0x00000004
#define WMI_THIN_CFG_FILTER_RULES 0x00000008
u32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
u16 length; /* length in bytes of appended sub-commands */
u8 reserved[2]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_CMD;
/* MIB Access Identifiers tailored for Symbian. */
enum {
MIB_ID_STA_MAC = 1, // [READONLY]
MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED]
MIB_ID_SLOT_TIME, // [READ/WRITE]
MIB_ID_RTS_THRESHOLD, // [READ/WRITE]
MIB_ID_CTS_TO_SELF, // [READ/WRITE]
MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY]
MIB_ID_RXFRAME_FILTER, // [READ/WRITE]
MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY]
MIB_ID_BEACON_FILTER, // [READ/WRITE]
MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY]
MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY]
MIB_ID_HT_CAP, // [NOT IMPLEMENTED]
MIB_ID_HT_OP, // [NOT IMPLEMENTED]
MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED]
MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED]
MIB_ID_PREAMBLE, // [READ/WRITE]
/*MIB_ID_GROUP_ADDR_TABLE,*/
/*MIB_ID_WEP_DEFAULT_KEY_ID */
/*MIB_ID_TX_POWER */
/*MIB_ID_ARP_IP_TABLE */
/*MIB_ID_SLEEP_MODE */
/*MIB_ID_WAKE_INTERVAL*/
/*MIB_ID_STAT_TABLE*/
/*MIB_ID_IBSS_PWR_SAVE*/
/*MIB_ID_COUNTERS_TABLE*/
/*MIB_ID_ETHERTYPE_FILTER*/
/*MIB_ID_BC_UDP_FILTER*/
};
typedef PREPACK struct {
u8 addr[ATH_MAC_LEN];
} POSTPACK WMI_THIN_MIB_STA_MAC;
typedef PREPACK struct {
u32 time; // units == msec
} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
typedef PREPACK struct {
u8 enable; //1 = on, 0 = off
} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
typedef PREPACK struct {
u32 time; // units == usec
} POSTPACK WMI_THIN_MIB_SLOT_TIME;
typedef PREPACK struct {
u16 length; //units == bytes
} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
typedef PREPACK struct {
u8 type; // type of frame
u8 rate; // tx rate to be used (one of WMI_BIT_RATE)
u16 length; // num bytes following this structure as the template data
} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
typedef PREPACK struct {
#define FRAME_FILTER_PROMISCUOUS 0x00000001
#define FRAME_FILTER_BSSID 0x00000002
u32 filterMask;
} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
#define IE_FILTER_TREATMENT_CHANGE 1
#define IE_FILTER_TREATMENT_APPEAR 2
typedef PREPACK struct {
u8 ie;
u8 treatment;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
typedef PREPACK struct {
u8 ie;
u8 treatment;
u8 oui[3];
u8 type;
u16 version;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
typedef PREPACK struct {
u16 numElements;
u8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
u8 reserved;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER;
typedef PREPACK struct {
u32 count; /* num beacons between deliveries */
u8 enable;
u8 reserved[3];
} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
typedef PREPACK struct {
u32 count; /* num consec lost beacons after which send event */
} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
typedef PREPACK struct {
u8 rssi; /* the low threshold which can trigger an event warning */
u8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
u8 count; /* the sample count of consecutive frames necessary to trigger an event. */
u8 reserved[1]; /* padding */
} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
typedef PREPACK struct {
u32 cap;
u32 rxRateField;
u32 beamForming;
u8 addr[ATH_MAC_LEN];
u8 enable;
u8 stbc;
u8 maxAMPDU;
u8 msduSpacing;
u8 mcsFeedback;
u8 antennaSelCap;
} POSTPACK WMI_THIN_MIB_HT_CAP;
typedef PREPACK struct {
u32 infoField;
u32 basicRateField;
u8 protection;
u8 secondChanneloffset;
u8 channelWidth;
u8 reserved;
} POSTPACK WMI_THIN_MIB_HT_OP;
typedef PREPACK struct {
#define SECOND_BEACON_PRIMARY 1
#define SECOND_BEACON_EITHER 2
#define SECOND_BEACON_SECONDARY 3
u8 cfg;
u8 reserved[3]; /* padding */
} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
typedef PREPACK struct {
u8 txTIDField;
u8 rxTIDField;
u8 reserved[2]; /* padding */
} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
typedef PREPACK struct {
u8 enableLong; // 1 == long preamble, 0 == short preamble
u8 reserved[3];
} POSTPACK WMI_THIN_MIB_PREAMBLE;
typedef PREPACK struct {
u16 length; /* the length in bytes of the appended MIB data */
u8 mibID; /* the ID of the MIB element being set */
u8 reserved; /* align padding */
} POSTPACK WMI_THIN_SET_MIB_CMD;
typedef PREPACK struct {
u8 mibID; /* the ID of the MIB element being set */
u8 reserved[3]; /* align padding */
} POSTPACK WMI_THIN_GET_MIB_CMD;
typedef PREPACK struct {
u32 basicRateMask; /* bit mask of basic rates */
u32 beaconIntval; /* TUs */
u16 atimWindow; /* TUs */
u16 channel; /* frequency in Mhz */
u8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
u8 ssidLength; /* 0 - 32 */
u8 probe; /* != 0 : issue probe req at start */
u8 reserved; /* alignment */
u8 ssid[WMI_MAX_SSID_LEN];
u8 bssid[ATH_MAC_LEN];
} POSTPACK WMI_THIN_JOIN_CMD;
typedef PREPACK struct {
u16 dtim; /* dtim interval in num beacons */
u16 aid; /* 80211 AID from Assoc resp */
} POSTPACK WMI_THIN_POST_ASSOC_CMD;
typedef enum {
WMI_THIN_EVENTID_RESERVED_START = 0x8000,
WMI_THIN_GET_MIB_EVENTID,
WMI_THIN_JOIN_EVENTID,
/* Add new THIN EVENTID's here */
WMI_THIN_EVENTID_RESERVED_END = 0x8fff
} WMI_THIN_EVENT_ID;
/* Possible values for WMI_THIN_JOIN_EVENT.result */
typedef enum {
WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
}WMI_THIN_JOIN_RESULT;
typedef PREPACK struct {
u8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
u8 reserved[3]; /* alignment */
} POSTPACK WMI_THIN_JOIN_EVENT;
#ifdef __cplusplus
}
#endif
#endif /* _WMI_THIN_H_ */

8
drivers/staging/ath6kl/include/common/wmix.h
View File

@ -40,10 +40,6 @@
extern "C" {
#endif
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#include "dbglog.h"
/*
@ -148,7 +144,6 @@ typedef PREPACK struct {
* All masks are 18-bit masks with bit N operating on GPIO pin N.
*/
#include "gpio.h"
/*
* Set GPIO pin output state.
@ -268,9 +263,6 @@ typedef PREPACK struct {
u32 count;
} POSTPACK WMIX_PROF_COUNT_EVENT;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#ifdef __cplusplus
}

4
drivers/staging/ath6kl/include/common_drv.h
View File

@ -81,10 +81,6 @@ int ar6000_set_htc_params(struct hif_device *hifDevice,
u32 MboxIsrYieldValue,
u8 HtcControlBuffers);
int ar6000_prepare_target(struct hif_device *hifDevice,
u32 TargetType,
u32 TargetVersion);
int ar6000_set_hci_bridge_flags(struct hif_device *hifDevice,
u32 TargetType,
u32 Flags);

59
drivers/staging/ath6kl/include/gpio_api.h
View File

@ -1,59 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="gpio_api.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Host-side General Purpose I/O API.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _GPIO_API_H_
#define _GPIO_API_H_
/*
* Send a command to the Target in order to change output on GPIO pins.
*/
int wmi_gpio_output_set(struct wmi_t *wmip,
u32 set_mask,
u32 clear_mask,
u32 enable_mask,
u32 disable_mask);
/*
* Send a command to the Target requesting input state of GPIO pins.
*/
int wmi_gpio_input_get(struct wmi_t *wmip);
/*
* Send a command to the Target to change the value of a GPIO register.
*/
int wmi_gpio_register_set(struct wmi_t *wmip,
u32 gpioreg_id,
u32 value);
/*
* Send a command to the Target to fetch the value of a GPIO register.
*/
int wmi_gpio_register_get(struct wmi_t *wmip, u32 gpioreg_id);
/*
* Send a command to the Target, acknowledging some GPIO interrupts.
*/
int wmi_gpio_intr_ack(struct wmi_t *wmip, u32 ack_mask);
#endif /* _GPIO_API_H_ */

3
drivers/staging/ath6kl/include/hif.h
View File

@ -32,7 +32,6 @@ extern "C" {
/* Header files */
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "dl_list.h"
@ -148,7 +147,7 @@ typedef enum {
*
* HIF_DEVICE_GET_MBOX_BLOCK_SIZE
* input : none
* output : array of 4 A_UINT32s
* output : array of 4 u32s
* notes: block size is returned for each mailbox (4)
*
* HIF_DEVICE_GET_MBOX_ADDR

244
drivers/staging/ath6kl/include/target_reg_table.h
View File

@ -1,244 +0,0 @@
//------------------------------------------------------------------------------
// <copyright file="target_reg_table.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Target register table macros and structure definitions
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef TARGET_REG_TABLE_H_
#define TARGET_REG_TABLE_H_
#include "targaddrs.h"
/*** WARNING : Add to the end of the TABLE! do not change the order ****/
typedef struct targetdef_s {
u32 d_RTC_BASE_ADDRESS;
u32 d_SYSTEM_SLEEP_OFFSET;
u32 d_SYSTEM_SLEEP_DISABLE_LSB;
u32 d_SYSTEM_SLEEP_DISABLE_MASK;
u32 d_CLOCK_CONTROL_OFFSET;
u32 d_CLOCK_CONTROL_SI0_CLK_MASK;
u32 d_RESET_CONTROL_OFFSET;
u32 d_RESET_CONTROL_SI0_RST_MASK;
u32 d_GPIO_BASE_ADDRESS;
u32 d_GPIO_PIN0_OFFSET;
u32 d_GPIO_PIN1_OFFSET;
u32 d_GPIO_PIN0_CONFIG_MASK;
u32 d_GPIO_PIN1_CONFIG_MASK;
u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
u32 d_SI_CONFIG_I2C_LSB;
u32 d_SI_CONFIG_I2C_MASK;
u32 d_SI_CONFIG_POS_SAMPLE_LSB;
u32 d_SI_CONFIG_POS_SAMPLE_MASK;
u32 d_SI_CONFIG_INACTIVE_CLK_LSB;
u32 d_SI_CONFIG_INACTIVE_CLK_MASK;
u32 d_SI_CONFIG_INACTIVE_DATA_LSB;
u32 d_SI_CONFIG_INACTIVE_DATA_MASK;
u32 d_SI_CONFIG_DIVIDER_LSB;
u32 d_SI_CONFIG_DIVIDER_MASK;
u32 d_SI_BASE_ADDRESS;
u32 d_SI_CONFIG_OFFSET;
u32 d_SI_TX_DATA0_OFFSET;
u32 d_SI_TX_DATA1_OFFSET;
u32 d_SI_RX_DATA0_OFFSET;
u32 d_SI_RX_DATA1_OFFSET;
u32 d_SI_CS_OFFSET;
u32 d_SI_CS_DONE_ERR_MASK;
u32 d_SI_CS_DONE_INT_MASK;
u32 d_SI_CS_START_LSB;
u32 d_SI_CS_START_MASK;
u32 d_SI_CS_RX_CNT_LSB;
u32 d_SI_CS_RX_CNT_MASK;
u32 d_SI_CS_TX_CNT_LSB;
u32 d_SI_CS_TX_CNT_MASK;
u32 d_BOARD_DATA_SZ;
u32 d_BOARD_EXT_DATA_SZ;
} TARGET_REGISTER_TABLE;
#define BOARD_DATA_SZ_MAX 2048
#if defined(MY_TARGET_DEF) /* { */
#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
static struct targetdef_s my_target_def = {
RTC_BASE_ADDRESS,
SYSTEM_SLEEP_OFFSET,
SYSTEM_SLEEP_DISABLE_LSB,
SYSTEM_SLEEP_DISABLE_MASK,
CLOCK_CONTROL_OFFSET,
CLOCK_CONTROL_SI0_CLK_MASK,
RESET_CONTROL_OFFSET,
RESET_CONTROL_SI0_RST_MASK,
GPIO_BASE_ADDRESS,
GPIO_PIN0_OFFSET,
GPIO_PIN0_CONFIG_MASK,
GPIO_PIN1_OFFSET,
GPIO_PIN1_CONFIG_MASK,
SI_CONFIG_BIDIR_OD_DATA_LSB,
SI_CONFIG_BIDIR_OD_DATA_MASK,
SI_CONFIG_I2C_LSB,
SI_CONFIG_I2C_MASK,
SI_CONFIG_POS_SAMPLE_LSB,
SI_CONFIG_POS_SAMPLE_MASK,
SI_CONFIG_INACTIVE_CLK_LSB,
SI_CONFIG_INACTIVE_CLK_MASK,
SI_CONFIG_INACTIVE_DATA_LSB,
SI_CONFIG_INACTIVE_DATA_MASK,
SI_CONFIG_DIVIDER_LSB,
SI_CONFIG_DIVIDER_MASK,
SI_BASE_ADDRESS,
SI_CONFIG_OFFSET,
SI_TX_DATA0_OFFSET,
SI_TX_DATA1_OFFSET,
SI_RX_DATA0_OFFSET,
SI_RX_DATA1_OFFSET,
SI_CS_OFFSET,
SI_CS_DONE_ERR_MASK,
SI_CS_DONE_INT_MASK,
SI_CS_START_LSB,
SI_CS_START_MASK,
SI_CS_RX_CNT_LSB,
SI_CS_RX_CNT_MASK,
SI_CS_TX_CNT_LSB,
SI_CS_TX_CNT_MASK,
MY_TARGET_BOARD_DATA_SZ,
MY_TARGET_BOARD_EXT_DATA_SZ,
};
#else
static struct targetdef_s my_target_def = {
.d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
.d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
.d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
.d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
.d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
.d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
.d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
.d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
.d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
.d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
.d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
.d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
.d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
.d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
.d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
.d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
.d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
.d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
.d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
.d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
.d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
.d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
.d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
.d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
.d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
.d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
.d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
.d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
.d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
.d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
.d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
.d_SI_CS_OFFSET = SI_CS_OFFSET,
.d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
.d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
.d_SI_CS_START_LSB = SI_CS_START_LSB,
.d_SI_CS_START_MASK = SI_CS_START_MASK,
.d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
.d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
.d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
.d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
.d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
.d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
};
#endif
#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
#error "BOARD_DATA_SZ_MAX is too small"
#endif
struct targetdef_s *MY_TARGET_DEF = &my_target_def;
#else /* } { */
#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
/* SET macros */
#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#endif /* } */
#endif /*TARGET_REG_TABLE_H_*/

23
drivers/staging/ath6kl/miscdrv/ar3kconfig.c
View File

@ -24,7 +24,6 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"
@ -78,7 +77,7 @@ static int SendHCICommand(struct ar3k_config_info *pConfig,
} while (false);
if (pPacket != NULL) {
A_FREE(pPacket);
kfree(pPacket);
}
return status;
@ -116,7 +115,7 @@ static int RecvHCIEvent(struct ar3k_config_info *pConfig,
} while (false);
if (pRecvPacket != NULL) {
A_FREE(pRecvPacket);
kfree(pRecvPacket);
}
return status;
@ -203,7 +202,7 @@ int SendHCICommandWaitCommandComplete(struct ar3k_config_info *pConfig,
} while (false);
if (pBuffer != NULL) {
A_FREE(pBuffer);
kfree(pBuffer);
}
return status;
@ -268,7 +267,7 @@ static int AR3KConfigureHCIBaud(struct ar3k_config_info *pConfig)
} while (false);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
return status;
@ -304,7 +303,7 @@ static int AR3KExitMinBoot(struct ar3k_config_info *pConfig)
}
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
return status;
@ -328,7 +327,7 @@ static int AR3KConfigureSendHCIReset(struct ar3k_config_info *pConfig)
}
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
return status;
@ -382,7 +381,7 @@ static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Config Failed! \n"));
@ -397,7 +396,7 @@ static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Config Failed! \n"));
@ -412,7 +411,7 @@ static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Enable Failed! \n"));
@ -427,7 +426,7 @@ static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Enable Failed! \n"));
@ -442,7 +441,7 @@ static int AR3KEnableTLPM(struct ar3k_config_info *pConfig)
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
A_FREE(pBufferToFree);
kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Sleep Enable Failed! \n"));

22
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
View File

@ -222,7 +222,7 @@ int PSSendOps(void *arg)
A_RELEASE_FIRMWARE(firmware);
/* Parse the PS buffer to a global variable */
status = AthDoParsePS(buffer,len);
A_FREE(buffer);
kfree(buffer);
} else {
A_RELEASE_FIRMWARE(firmware);
}
@ -256,7 +256,7 @@ int PSSendOps(void *arg)
A_RELEASE_FIRMWARE(firmware);
/* parse and store the Patch file contents to a global variables */
status = AthDoParsePatch(buffer,len);
A_FREE(buffer);
kfree(buffer);
} else {
A_RELEASE_FIRMWARE(firmware);
}
@ -283,7 +283,7 @@ int PSSendOps(void *arg)
&bufferToFree) == 0) {
if(ReadPSEvent(event) == 0) { /* Exit if the status is success */
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
#ifndef HCI_TRANSPORT_SDIO
@ -295,7 +295,7 @@ int PSSendOps(void *arg)
goto complete;
}
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
} else {
status = 0;
@ -312,13 +312,13 @@ int PSSendOps(void *arg)
&bufferToFree) == 0) {
if(ReadPSEvent(event) != 0) { /* Exit if the status is success */
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
status = 1;
goto complete;
}
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
} else {
status = 0;
@ -376,10 +376,10 @@ int PSSendOps(void *arg)
AthFreeCommandList(&HciCmdList,numCmds);
}
if(path) {
A_FREE(path);
kfree(path);
}
if(config_path) {
A_FREE(config_path);
kfree(config_path);
}
return status;
}
@ -511,7 +511,7 @@ int write_bdaddr(struct ar3k_config_info *pConfig,u8 *bdaddr,int type)
}
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
return result;
@ -527,7 +527,7 @@ int ReadVersionInfo(struct ar3k_config_info *pConfig)
}
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
return result;
}
@ -564,7 +564,7 @@ int getDeviceType(struct ar3k_config_info *pConfig, u32 *code)
}
if(bufferToFree != NULL) {
A_FREE(bufferToFree);
kfree(bufferToFree);
}
return result;
}

28
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
View File

@ -362,7 +362,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -401,7 +401,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -422,7 +422,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -433,7 +433,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
if (ByteCount > LINE_SIZE_MAX/2)
{
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -449,7 +449,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -510,7 +510,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
//Sleep (3000);
@ -524,7 +524,7 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
default:
{
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
@ -541,13 +541,13 @@ int AthParseFilesUnified(u8 *srcbuffer,u32 srclen, int FileFormat)
{
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return A_ERROR;
}
if(Buffer != NULL) {
A_FREE(Buffer);
kfree(Buffer);
}
return 0;
@ -609,7 +609,7 @@ int AthDoParsePatch(u8 *patchbuffer, u32 patchlen)
/* Handle case when the number of patch buffer is more than the 20K */
if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
for(i = 0; i < Patch_Count; i++) {
A_FREE(RamPatch[i].Data);
kfree(RamPatch[i].Data);
}
return A_ERROR;
}
@ -812,13 +812,13 @@ int AthCreateCommandList(struct ps_cmd_packet **HciPacketList, u32 *numPackets)
for(count = 0; count < Patch_Count; count++) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
A_FREE(RamPatch[Patch_Count].Data);
kfree(RamPatch[Patch_Count].Data);
}
for(count = 0; count < Tag_Count; count++) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
A_FREE(PsTagEntry[count].TagData);
kfree(PsTagEntry[count].TagData);
}
/*
@ -962,8 +962,8 @@ int AthFreeCommandList(struct ps_cmd_packet **HciPacketList, u32 numPackets)
return A_ERROR;
}
for(i = 0; i < numPackets;i++) {
A_FREE((*HciPacketList)[i].Hcipacket);
kfree((*HciPacketList)[i].Hcipacket);
}
A_FREE(*HciPacketList);
kfree(*HciPacketList);
return 0;
}

6
drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
View File

@ -33,7 +33,6 @@
#include "athdefs.h"
#ifdef HCI_TRANSPORT_SDIO
#include "a_config.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"
@ -60,11 +59,6 @@
#ifndef A_MALLOC
#define A_MALLOC(size) kmalloc((size),GFP_KERNEL)
#endif /* A_MALLOC */
#ifndef A_FREE
#define A_FREE(addr) kfree((addr))
#endif /* A_MALLOC */
#endif /* HCI_TRANSPORT_UART */
/* String manipulation APIs */

126
drivers/staging/ath6kl/miscdrv/common_drv.c
View File

@ -23,15 +23,12 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "AR6002/hw2.0/hw/apb_map.h"
#include "AR6002/hw2.0/hw/si_reg.h"
#include "AR6002/hw2.0/hw/gpio_reg.h"
#include "AR6002/hw2.0/hw/rtc_reg.h"
#include "AR6002/hw2.0/hw/vmc_reg.h"
#include "AR6002/hw2.0/hw/mbox_reg.h"
#include "hw/mbox_host_reg.h"
#include "gpio_reg.h"
#include "hw/rtc_reg.h"
#include "hw/mbox_reg.h"
#include "hw/apb_map.h"
#include "a_osapi.h"
#include "targaddrs.h"
@ -683,119 +680,6 @@ int ar6000_set_htc_params(struct hif_device *hifDevice,
return status;
}
static int prepare_ar6002(struct hif_device *hifDevice, u32 TargetVersion)
{
int status = 0;
/* placeholder */
return status;
}
static int prepare_ar6003(struct hif_device *hifDevice, u32 TargetVersion)
{
int status = 0;
/* placeholder */
return status;
}
/* this function assumes the caller has already initialized the BMI APIs */
int ar6000_prepare_target(struct hif_device *hifDevice,
u32 TargetType,
u32 TargetVersion)
{
if (TargetType == TARGET_TYPE_AR6002) {
/* do any preparations for AR6002 devices */
return prepare_ar6002(hifDevice,TargetVersion);
} else if (TargetType == TARGET_TYPE_AR6003) {
return prepare_ar6003(hifDevice,TargetVersion);
}
return 0;
}
#if defined(CONFIG_AR6002_REV1_FORCE_HOST)
/*
* Call this function just before the call to BMIInit
* in order to force* AR6002 rev 1.x firmware to detect a Host.
* THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
* TBDXXX: Remove this function when REV 1.x is desupported.
*/
int
ar6002_REV1_reset_force_host (struct hif_device *hifDevice)
{
s32 i;
struct forceROM_s {
u32 addr;
u32 data;
};
struct forceROM_s *ForceROM;
s32 szForceROM;
int status = 0;
u32 address;
u32 data;
/* Force AR6002 REV1.x to recognize Host presence.
*
* Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
* so that this workaround functions with AR6002.war1.sh. We
* could fold that entire workaround into this one, but it's not
* worth the effort at this point. This workaround cannot be
* merged into the other workaround because this must be done
* before BMI.
*/
static struct forceROM_s ForceROM_NEW[] = {
{0x52df80, 0x20f31c07},
{0x52df84, 0x92374420},
{0x52df88, 0x1d120c03},
{0x52df8c, 0xff8216f0},
{0x52df90, 0xf01d120c},
{0x52df94, 0x81004136},
{0x52df98, 0xbc9100bd},
{0x52df9c, 0x00bba100},
{0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
{0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
{0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
{0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
{0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
{0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
};
address = 0x004ed4b0; /* REV1 target software ID is stored here */
status = ar6000_ReadRegDiag(hifDevice, &address, &data);
if (status || (data != AR6002_VERSION_REV1)) {
return A_ERROR; /* Not AR6002 REV1 */
}
ForceROM = ForceROM_NEW;
szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
for (i = 0; i < szForceROM; i++)
{
if (ar6000_WriteRegDiag(hifDevice,
&ForceROM[i].addr,
&ForceROM[i].data) != 0)
{
ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
return A_ERROR;
}
}
A_MDELAY(1000);
return 0;
}
#endif /* CONFIG_AR6002_REV1_FORCE_HOST */
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription)
{
char stream[60];

1
drivers/staging/ath6kl/miscdrv/credit_dist.c
View File

@ -23,7 +23,6 @@
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"

388
drivers/staging/ath6kl/os/linux/ar6000_android.c
View File

@ -1,388 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Communications Inc.
// All rights reserved.
//
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#include "ar6000_drv.h"
#include "htc.h"
#include <linux/vmalloc.h>
#include <linux/fs.h>
#ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h>
#endif
bool enable_mmc_host_detect_change = false;
static void ar6000_enable_mmchost_detect_change(int enable);
char fwpath[256] = "/system/wifi";
int wowledon;
unsigned int enablelogcat;
extern int bmienable;
extern struct net_device *ar6000_devices[];
extern char ifname[];
const char def_ifname[] = "wlan0";
module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
module_param(enablelogcat, uint, 0644);
module_param(wowledon, int, 0644);
#ifdef CONFIG_HAS_EARLYSUSPEND
static int screen_is_off;
static struct early_suspend ar6k_early_suspend;
#endif
static int (*ar6000_avail_ev_p)(void *, void *);
#if defined(CONFIG_ANDROID_LOGGER) && (!defined(CONFIG_MMC_MSM))
int logger_write(const enum logidx index,
const unsigned char prio,
const char __kernel * const tag,
const char __kernel * const fmt,
...)
{
int ret = 0;
va_list vargs;
struct file *filp = (struct file *)-ENOENT;
mm_segment_t oldfs;
struct iovec vec[3];
int tag_bytes = strlen(tag) + 1, msg_bytes;
char *msg;
va_start(vargs, fmt);
msg = kvasprintf(GFP_ATOMIC, fmt, vargs);
va_end(vargs);
if (!msg)
return -ENOMEM;
if (in_interrupt()) {
/* we have no choice since aio_write may be blocked */
printk(KERN_ALERT "%s", msg);
goto out_free_message;
}
msg_bytes = strlen(msg) + 1;
if (msg_bytes <= 1) /* empty message? */
goto out_free_message; /* don't bother, then */
if ((msg_bytes + tag_bytes + 1) > 2048) {
ret = -E2BIG;
goto out_free_message;
}
vec[0].iov_base = (unsigned char *) &prio;
vec[0].iov_len = 1;
vec[1].iov_base = (void *) tag;
vec[1].iov_len = strlen(tag) + 1;
vec[2].iov_base = (void *) msg;
vec[2].iov_len = strlen(msg) + 1;
oldfs = get_fs();
set_fs(KERNEL_DS);
do {
filp = filp_open("/dev/log/main", O_WRONLY, S_IRUSR);
if (IS_ERR(filp) || !filp->f_op) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: filp_open /dev/log/main error\n", __FUNCTION__));
ret = -ENOENT;
break;
}
if (filp->f_op->aio_write) {
int nr_segs = sizeof(vec) / sizeof(vec[0]);
int len = vec[0].iov_len + vec[1].iov_len + vec[2].iov_len;
struct kiocb kiocb;
init_sync_kiocb(&kiocb, filp);
kiocb.ki_pos = 0;
kiocb.ki_left = len;
kiocb.ki_nbytes = len;
ret = filp->f_op->aio_write(&kiocb, vec, nr_segs, kiocb.ki_pos);
}
} while (0);
if (!IS_ERR(filp)) {
filp_close(filp, NULL);
}
set_fs(oldfs);
out_free_message:
kfree(msg);
return ret;
}
#endif
int android_logger_lv(void *module, int mask)
{
switch (mask) {
case ATH_DEBUG_ERR:
return 6;
case ATH_DEBUG_INFO:
return 4;
case ATH_DEBUG_WARN:
return 5;
case ATH_DEBUG_TRC:
return 3;
default:
#ifdef DEBUG
if (!module) {
return 3;
} else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(driver)) {
return (mask <=ATH_DEBUG_MAKE_MODULE_MASK(3)) ? 3 : 2;
} else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(htc)) {
return 2;
} else {
return 3;
}
#else
return 3; /* DEBUG */
#endif
}
}
static int android_readwrite_file(const char *filename, char *rbuf, const char *wbuf, size_t length)
{
int ret = 0;
struct file *filp = (struct file *)-ENOENT;
mm_segment_t oldfs;
oldfs = get_fs();
set_fs(KERNEL_DS);
do {
int mode = (wbuf) ? O_RDWR : O_RDONLY;
filp = filp_open(filename, mode, S_IRUSR);
if (IS_ERR(filp) || !filp->f_op) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: file %s filp_open error\n", __FUNCTION__, filename));
ret = -ENOENT;
break;
}
if (length==0) {
/* Read the length of the file only */
struct inode *inode;
inode = GET_INODE_FROM_FILEP(filp);
if (!inode) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Get inode from %s failed\n", __FUNCTION__, filename));
ret = -ENOENT;
break;
}
ret = i_size_read(inode->i_mapping->host);
break;
}
if (wbuf) {
if ( (ret=filp->f_op->write(filp, wbuf, length, &filp->f_pos)) < 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Write %u bytes to file %s error %d\n", __FUNCTION__,
length, filename, ret));
break;
}
} else {
if ( (ret=filp->f_op->read(filp, rbuf, length, &filp->f_pos)) < 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Read %u bytes from file %s error %d\n", __FUNCTION__,
length, filename, ret));
break;
}
}
} while (0);
if (!IS_ERR(filp)) {
filp_close(filp, NULL);
}
set_fs(oldfs);
return ret;
}
int android_request_firmware(const struct firmware **firmware_p, const char *name,
struct device *device)
{
int ret = 0;
struct firmware *firmware;
char filename[256];
const char *raw_filename = name;
*firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
if (!firmware)
return -ENOMEM;
sprintf(filename, "%s/%s", fwpath, raw_filename);
do {
size_t length, bufsize, bmisize;
if ( (ret=android_readwrite_file(filename, NULL, NULL, 0)) < 0) {
break;
} else {
length = ret;
}
bufsize = ALIGN(length, PAGE_SIZE);
bmisize = A_ROUND_UP(length, 4);
bufsize = max(bmisize, bufsize);
firmware->data = vmalloc(bufsize);
firmware->size = length;
if (!firmware->data) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: Cannot allocate buffer for firmware\n", __FUNCTION__));
ret = -ENOMEM;
break;
}
if ( (ret=android_readwrite_file(filename, (char*)firmware->data, NULL, length)) != length) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: file read error, ret %d request %d\n", __FUNCTION__, ret, length));
ret = -1;
break;
}
} while (0);
if (ret<0) {
if (firmware) {
if (firmware->data)
vfree(firmware->data);
kfree(firmware);
}
*firmware_p = NULL;
} else {
ret = 0;
}
return ret;
}
void android_release_firmware(const struct firmware *firmware)
{
if (firmware) {
if (firmware->data)
vfree(firmware->data);
kfree(firmware);
}
}
static int ar6000_android_avail_ev(void *context, void *hif_handle)
{
int ret;
ar6000_enable_mmchost_detect_change(0);
ret = ar6000_avail_ev_p(context, hif_handle);
return ret;
}
/* Useful for qualcom platform to detect our wlan card for mmc stack */
static void ar6000_enable_mmchost_detect_change(int enable)
{
#ifdef CONFIG_MMC_MSM
#define MMC_MSM_DEV "msm_sdcc.1"
char buf[3];
int length;
if (!enable_mmc_host_detect_change) {
return;
}
length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0);
if (android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/detect_change",
NULL, buf, length) < 0) {
/* fall back to polling */
android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/polling", NULL, buf, length);
}
#endif
}
#ifdef CONFIG_HAS_EARLYSUSPEND
static void android_early_suspend(struct early_suspend *h)
{
screen_is_off = 1;
}
static void android_late_resume(struct early_suspend *h)
{
screen_is_off = 0;
}
#endif
void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks)
{
bmienable = 1;
if (ifname[0] == '\0')
strcpy(ifname, def_ifname);
#ifdef CONFIG_HAS_EARLYSUSPEND
ar6k_early_suspend.suspend = android_early_suspend;
ar6k_early_suspend.resume = android_late_resume;
ar6k_early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN;
register_early_suspend(&ar6k_early_suspend);
#endif
ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler;
osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev;
ar6000_enable_mmchost_detect_change(1);
}
void android_module_exit(void)
{
#ifdef CONFIG_HAS_EARLYSUSPEND
unregister_early_suspend(&ar6k_early_suspend);
#endif
ar6000_enable_mmchost_detect_change(1);
}
#ifdef CONFIG_PM
void android_ar6k_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isEvent)
{
if (
#ifdef CONFIG_HAS_EARLYSUSPEND
screen_is_off &&
#endif
skb && ar->arConnected) {
bool needWake = false;
if (isEvent) {
if (A_NETBUF_LEN(skb) >= sizeof(u16)) {
u16 cmd = *(const u16 *)A_NETBUF_DATA(skb);
switch (cmd) {
case WMI_CONNECT_EVENTID:
case WMI_DISCONNECT_EVENTID:
needWake = true;
break;
default:
/* dont wake lock the system for other event */
break;
}
}
} else if (A_NETBUF_LEN(skb) >= sizeof(ATH_MAC_HDR)) {
ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
if (!IEEE80211_IS_MULTICAST(datap->dstMac)) {
switch (A_BE2CPU16(datap->typeOrLen)) {
case 0x0800: /* IP */
case 0x888e: /* EAPOL */
case 0x88c7: /* RSN_PREAUTH */
case 0x88b4: /* WAPI */
needWake = true;
break;
case 0x0806: /* ARP is not important to hold wake lock */
default:
break;
}
}
}
if (needWake) {
/* keep host wake up if there is any event and packate coming in*/
if (wowledon) {
char buf[32];
int len = sprintf(buf, "on");
android_readwrite_file("/sys/power/state", NULL, buf, len);
len = sprintf(buf, "%d", 127);
android_readwrite_file("/sys/class/leds/lcd-backlight/brightness",
NULL, buf,len);
}
}
}
}
#endif /* CONFIG_PM */

793
drivers/staging/ath6kl/os/linux/ar6000_drv.c
View File

File diff suppressed because it is too large Load Diff

77
drivers/staging/ath6kl/os/linux/ar6000_pm.c
View File

@ -36,9 +36,6 @@
extern unsigned int wmitimeout;
extern wait_queue_head_t arEvent;
#ifdef ANDROID_ENV
extern void android_ar6k_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isEvent);
#endif
#undef ATH_MODULE_NAME
#define ATH_MODULE_NAME pm
#define ATH_DEBUG_PM ATH_DEBUG_MAKE_MODULE_MASK(0)
@ -283,10 +280,6 @@ void ar6000_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isE
/* Wow resume from irq interrupt */
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: WoW resume from irq thread status %d\n", __func__, ar->arWlanPowerState));
ar6000_wow_resume(ar);
} else {
#ifdef ANDROID_ENV
android_ar6k_check_wow_status(ar, skb, isEvent);
#endif
}
}
@ -309,37 +302,6 @@ int ar6000_power_change_ev(void *context, u32 config)
return status;
}
static int ar6000_pm_probe(struct platform_device *pdev)
{
plat_setup_power(1,1);
return 0;
}
static int ar6000_pm_remove(struct platform_device *pdev)
{
plat_setup_power(0,1);
return 0;
}
static int ar6000_pm_suspend(struct platform_device *pdev, pm_message_t state)
{
return 0;
}
static int ar6000_pm_resume(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver ar6000_pm_device = {
.probe = ar6000_pm_probe,
.remove = ar6000_pm_remove,
.suspend = ar6000_pm_suspend,
.resume = ar6000_pm_resume,
.driver = {
.name = "wlan_ar6000_pm",
},
};
#endif /* CONFIG_PM */
int
@ -359,8 +321,6 @@ ar6000_setup_cut_power_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
break;
}
plat_setup_power(1,0);
/* Change the state to ON */
ar->arWlanPowerState = WLAN_POWER_STATE_ON;
@ -373,17 +333,6 @@ ar6000_setup_cut_power_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
if (status == A_PENDING) {
#ifdef ANDROID_ENV
/* Wait for WMI ready event */
u32 timeleft = wait_event_interruptible_timeout(arEvent,
(ar->arWmiReady == true), wmitimeout * HZ);
if (!timeleft || signal_pending(current)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : Failed to get wmi ready \n"));
status = A_ERROR;
break;
}
#endif
status = 0;
} else if (status == 0) {
ar6000_restart_endpoint(ar->arNetDev);
status = 0;
@ -403,8 +352,6 @@ ar6000_setup_cut_power_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
&config,
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
plat_setup_power(0,0);
ar->arWlanPowerState = WLAN_POWER_STATE_CUT_PWR;
}
} while (0);
@ -642,8 +589,6 @@ ar6000_update_wlan_pwr_state(struct ar6_softc *ar, AR6000_WLAN_STATE state, bool
}
if (pSleepEvent) {
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("SENT WLAN Sleep Event %d\n", wmiSleepEvent.sleepState));
ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (u8 *)pSleepEvent,
sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
}
}
up(&ar->arSem);
@ -679,25 +624,3 @@ ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
status = ar6000_update_wlan_pwr_state(ar, state, false);
return status;
}
void ar6000_pm_init()
{
A_REGISTER_MODULE_DEBUG_INFO(pm);
#ifdef CONFIG_PM
/*
* Register ar6000_pm_device into system.
* We should also add platform_device into the first item of array
* of devices[] in file arch/xxx/mach-xxx/board-xxxx.c
*/
if (platform_driver_register(&ar6000_pm_device)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000: fail to register the power control driver.\n"));
}
#endif /* CONFIG_PM */
}
void ar6000_pm_exit()
{
#ifdef CONFIG_PM
platform_driver_unregister(&ar6000_pm_device);
#endif /* CONFIG_PM */
}

479
drivers/staging/ath6kl/os/linux/ar6k_pal.c
View File

@ -1,479 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Communications Inc.
// All rights reserved.
//
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#include "ar6000_drv.h"
#ifdef AR6K_ENABLE_HCI_PAL
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#include <ar6k_pal.h>
extern unsigned int setupbtdev;
#define bt_check_bit(val, bit) (val & bit)
#define bt_set_bit(val, bit) (val |= bit)
#define bt_clear_bit(val, bit) (val &= ~bit)
/* export ATH_AR6K_DEBUG_HCI_PAL=yes in host/localmake.linux.inc
* to enable debug information */
#ifdef HCIPAL_DEBUG
#define PRIN_LOG(format, args...) printk(KERN_ALERT "%s:%d - %s Msg:" format "\n",__FUNCTION__, __LINE__, __FILE__, ## args)
#else
#define PRIN_LOG(format, args...)
#endif
/**********************************
* HCI PAL private info structure
*********************************/
typedef struct ar6k_hci_pal_info_s{
unsigned long ulFlags;
#define HCI_NORMAL_MODE (1)
#define HCI_REGISTERED (1<<1)
struct hci_dev *hdev; /* BT Stack HCI dev */
struct ar6_softc *ar;
}ar6k_hci_pal_info_t;
/*** BT Stack Entrypoints *******/
/***************************************
* bt_open - open a handle to the device
***************************************/
static int bt_open(struct hci_dev *hdev)
{
PRIN_LOG("HCI PAL: bt_open - enter - x\n");
set_bit(HCI_RUNNING, &hdev->flags);
set_bit(HCI_UP, &hdev->flags);
set_bit(HCI_INIT, &hdev->flags);
return 0;
}
/***************************************
* bt_close - close handle to the device
***************************************/
static int bt_close(struct hci_dev *hdev)
{
PRIN_LOG("HCI PAL: bt_close - enter\n");
clear_bit(HCI_RUNNING, &hdev->flags);
return 0;
}
/*****************************
* bt_ioctl - ioctl processing
*****************************/
static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
{
PRIN_LOG("HCI PAL: bt_ioctl - enter\n");
return -ENOIOCTLCMD;
}
/**************************************
* bt_flush - flush outstanding packets
**************************************/
static int bt_flush(struct hci_dev *hdev)
{
PRIN_LOG("HCI PAL: bt_flush - enter\n");
return 0;
}
/***************
* bt_destruct
***************/
static void bt_destruct(struct hci_dev *hdev)
{
PRIN_LOG("HCI PAL: bt_destruct - enter\n");
/* nothing to do here */
}
/****************************************************
* Invoked from bluetooth stack via hdev->send()
* to send the packet out via ar6k to PAL firmware.
*
* For HCI command packet wmi_send_hci_cmd() is invoked.
* wmi_send_hci_cmd adds WMI_CMD_HDR and sends the packet
* to PAL firmware.
*
* For HCI ACL data packet wmi_data_hdr_add is invoked
* to add WMI_DATA_HDR to the packet. ar6000_acl_data_tx
* is then invoked to send the packet to PAL firmware.
******************************************************/
static int btpal_send_frame(struct sk_buff *skb)
{
struct hci_dev *hdev = (struct hci_dev *)skb->dev;
HCI_TRANSPORT_PACKET_TYPE type;
ar6k_hci_pal_info_t *pHciPalInfo;
int status = 0;
struct sk_buff *txSkb = NULL;
struct ar6_softc *ar;
if (!hdev) {
PRIN_LOG("HCI PAL: btpal_send_frame - no device\n");
return -ENODEV;
}
if (!test_bit(HCI_RUNNING, &hdev->flags)) {
PRIN_LOG("HCI PAL: btpal_send_frame - not open\n");
return -EBUSY;
}
pHciPalInfo = (ar6k_hci_pal_info_t *)hdev->driver_data;
A_ASSERT(pHciPalInfo != NULL);
ar = pHciPalInfo->ar;
PRIN_LOG("+btpal_send_frame type: %d \n",bt_cb(skb)->pkt_type);
type = HCI_COMMAND_TYPE;
switch (bt_cb(skb)->pkt_type) {
case HCI_COMMAND_PKT:
type = HCI_COMMAND_TYPE;
hdev->stat.cmd_tx++;
break;
case HCI_ACLDATA_PKT:
type = HCI_ACL_TYPE;
hdev->stat.acl_tx++;
break;
case HCI_SCODATA_PKT:
/* we don't support SCO over the pal */
kfree_skb(skb);
return 0;
default:
A_ASSERT(false);
kfree_skb(skb);
return 0;
}
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
A_PRINTF(">>> Send HCI %s packet len: %d\n",
(type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
skb->len);
if (type == HCI_COMMAND_TYPE) {
PRIN_LOG(" HCI Command: OGF:0x%X OCF:0x%X \r\n",
HCI_GET_OP_CODE(skb-data) >> 10, HCI_GET_OP_CODE(skb-data) & 0x3FF);
}
AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
}
do {
if(type == HCI_COMMAND_TYPE)
{
PRIN_LOG("HCI command");
if (ar->arWmiReady == false)
{
PRIN_LOG("WMI not ready ");
break;
}
if (wmi_send_hci_cmd(ar->arWmi, skb->data, skb->len) != 0)
{
PRIN_LOG("send hci cmd error");
break;
}
}
else if(type == HCI_ACL_TYPE)
{
void *osbuf;
PRIN_LOG("ACL data");
if (ar->arWmiReady == false)
{
PRIN_LOG("WMI not ready");
break;
}
/* need to add WMI header so allocate a skb with more space */
txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ +
sizeof(WMI_DATA_HDR) + skb->len,
GFP_ATOMIC);
if (txSkb == NULL) {
status = A_NO_MEMORY;
PRIN_LOG("No memory");
break;
}
bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
txSkb->dev = (void *)pHciPalInfo->hdev;
skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ + sizeof(WMI_DATA_HDR));
memcpy(txSkb->data, skb->data, skb->len);
skb_put(txSkb,skb->len);
/* Add WMI packet type */
osbuf = (void *)txSkb;
if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != 0) {
PRIN_LOG("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n");
} else {
/* Send data buffer over HTC */
PRIN_LOG("acl data tx");
ar6000_acl_data_tx(osbuf, ar->arNetDev);
}
txSkb = NULL;
}
} while (false);
if (txSkb != NULL) {
PRIN_LOG("Free skb");
kfree_skb(txSkb);
}
kfree_skb(skb);
return 0;
}
/***********************************************
* Unregister HCI device and free HCI device info
***********************************************/
static void bt_cleanup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
{
int err;
if (bt_check_bit(pHciPalInfo->ulFlags, HCI_REGISTERED)) {
bt_clear_bit(pHciPalInfo->ulFlags, HCI_REGISTERED);
clear_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags);
clear_bit(HCI_UP, &pHciPalInfo->hdev->flags);
clear_bit(HCI_INIT, &pHciPalInfo->hdev->flags);
A_ASSERT(pHciPalInfo->hdev != NULL);
/* unregister */
PRIN_LOG("Unregister PAL device");
if ((err = hci_unregister_dev(pHciPalInfo->hdev)) < 0) {
PRIN_LOG("HCI PAL: failed to unregister with bluetooth %d\n",err);
}
}
kfree(pHciPalInfo->hdev);
pHciPalInfo->hdev = NULL;
}
/*********************************************************
* Allocate HCI device and store in PAL private info structure.
*********************************************************/
static int bt_setup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
{
int status = 0;
struct hci_dev *pHciDev = NULL;
if (!setupbtdev) {
return 0;
}
do {
/* allocate a BT HCI struct for this device */
pHciDev = hci_alloc_dev();
if (NULL == pHciDev) {
PRIN_LOG("HCI PAL driver - failed to allocate BT HCI struct \n");
status = A_NO_MEMORY;
break;
}
/* save the device, we'll register this later */
pHciPalInfo->hdev = pHciDev;
SET_HCI_BUS_TYPE(pHciDev, HCI_VIRTUAL, HCI_80211);
pHciDev->driver_data = pHciPalInfo;
pHciDev->open = bt_open;
pHciDev->close = bt_close;
pHciDev->send = btpal_send_frame;
pHciDev->ioctl = bt_ioctl;
pHciDev->flush = bt_flush;
pHciDev->destruct = bt_destruct;
pHciDev->owner = THIS_MODULE;
/* driver is running in normal BT mode */
PRIN_LOG("Normal mode enabled");
bt_set_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE);
} while (false);
if (status) {
bt_cleanup_hci_pal(pHciPalInfo);
}
return status;
}
/**********************************************
* Cleanup HCI device and free HCI PAL private info
*********************************************/
void ar6k_cleanup_hci_pal(void *ar_p)
{
struct ar6_softc *ar = (struct ar6_softc *)ar_p;
ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)ar->hcipal_info;
if (pHciPalInfo != NULL) {
bt_cleanup_hci_pal(pHciPalInfo);
A_FREE(pHciPalInfo);
ar->hcipal_info = NULL;
}
}
/****************************
* Register HCI device
****************************/
static bool ar6k_pal_transport_ready(void *pHciPal)
{
ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
PRIN_LOG("HCI device transport ready");
if(pHciPalInfo == NULL)
return false;
if (hci_register_dev(pHciPalInfo->hdev) < 0) {
PRIN_LOG("Can't register HCI device");
hci_free_dev(pHciPalInfo->hdev);
return false;
}
PRIN_LOG("HCI device registered");
pHciPalInfo->ulFlags |= HCI_REGISTERED;
return true;
}
/**************************************************
* Called from ar6k driver when command or ACL data
* packet is received. Pass the packet to bluetooth
* stack via hci_recv_frame.
**************************************************/
bool ar6k_pal_recv_pkt(void *pHciPal, void *osbuf)
{
struct sk_buff *skb = (struct sk_buff *)osbuf;
ar6k_hci_pal_info_t *pHciPalInfo;
bool success = false;
u8 btType = 0;
pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
do {
/* if normal mode is not enabled pass on to the stack
* by returning failure */
if(!(pHciPalInfo->ulFlags & HCI_NORMAL_MODE))
{
PRIN_LOG("Normal mode not enabled");
break;
}
if (!test_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags)) {
PRIN_LOG("HCI PAL: HCI - not running\n");
break;
}
if(*((short *)A_NETBUF_DATA(skb)) == WMI_ACL_DATA_EVENTID)
btType = HCI_ACLDATA_PKT;
else
btType = HCI_EVENT_PKT;
/* pull 4 bytes which contains WMI packet type */
A_NETBUF_PULL(skb, sizeof(int));
bt_cb(skb)->pkt_type = btType;
skb->dev = (void *)pHciPalInfo->hdev;
/* pass the received event packet up the stack */
if (hci_recv_frame(skb) != 0) {
PRIN_LOG("HCI PAL: hci_recv_frame failed \n");
break;
} else {
PRIN_LOG("HCI PAL: Indicated RCV of type:%d, Length:%d \n",HCI_EVENT_PKT, skb->len);
}
PRIN_LOG("hci recv success");
success = true;
}while(false);
return success;
}
/**********************************************************
* HCI PAL init function called from ar6k when it is loaded..
* Allocates PAL private info, stores the same in ar6k private info.
* Registers a HCI device.
* Registers packet receive callback function with ar6k
**********************************************************/
int ar6k_setup_hci_pal(void *ar_p)
{
int status = 0;
ar6k_hci_pal_info_t *pHciPalInfo;
ar6k_pal_config_t ar6k_pal_config;
struct ar6_softc *ar = (struct ar6_softc *)ar_p;
do {
pHciPalInfo = (ar6k_hci_pal_info_t *)A_MALLOC(sizeof(ar6k_hci_pal_info_t));
if (NULL == pHciPalInfo) {
status = A_NO_MEMORY;
break;
}
A_MEMZERO(pHciPalInfo, sizeof(ar6k_hci_pal_info_t));
ar->hcipal_info = pHciPalInfo;
pHciPalInfo->ar = ar;
status = bt_setup_hci_pal(pHciPalInfo);
if (status) {
break;
}
if(bt_check_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE))
PRIN_LOG("HCI PAL: running in normal mode... \n");
else
PRIN_LOG("HCI PAL: running in test mode... \n");
ar6k_pal_config.fpar6k_pal_recv_pkt = ar6k_pal_recv_pkt;
register_pal_cb(&ar6k_pal_config);
ar6k_pal_transport_ready(ar->hcipal_info);
} while (false);
if (status) {
ar6k_cleanup_hci_pal(ar);
}
return status;
}
#else /* AR6K_ENABLE_HCI_PAL */
int ar6k_setup_hci_pal(void *ar_p)
{
return 0;
}
void ar6k_cleanup_hci_pal(void *ar_p)
{
}
#endif /* AR6K_ENABLE_HCI_PAL */
#ifdef EXPORT_HCI_PAL_INTERFACE
/*****************************************************
* Register init and callback function with ar6k
* when PAL driver is a separate kernel module.
****************************************************/
int ar6k_register_hci_pal(struct hci_transport_callbacks *hciTransCallbacks);
static int __init pal_init_module(void)
{
struct hci_transport_callbacks hciTransCallbacks;
hciTransCallbacks.setupTransport = ar6k_setup_hci_pal;
hciTransCallbacks.cleanupTransport = ar6k_cleanup_hci_pal;
if(ar6k_register_hci_pal(&hciTransCallbacks) != 0)
return -ENODEV;
return 0;
}
static void __exit pal_cleanup_module(void)
{
}
module_init(pal_init_module);
module_exit(pal_cleanup_module);
MODULE_LICENSE("Dual BSD/GPL");
#endif

346
drivers/staging/ath6kl/os/linux/cfg80211.c
View File

@ -172,6 +172,12 @@ ar6k_set_auth_type(struct ar6_softc *ar, enum nl80211_auth_type auth_type)
case NL80211_AUTHTYPE_NETWORK_EAP:
ar->arDot11AuthMode = LEAP_AUTH;
break;
case NL80211_AUTHTYPE_AUTOMATIC:
ar->arDot11AuthMode = OPEN_AUTH;
ar->arAutoAuthStage = AUTH_OPEN_IN_PROGRESS;
break;
default:
ar->arDot11AuthMode = OPEN_AUTH;
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@ -460,6 +466,8 @@ ar6k_cfg80211_connect_event(struct ar6_softc *ar, u16 channel,
assocReqLen -= assocReqIeOffset;
assocRespLen -= assocRespIeOffset;
ar->arAutoAuthStage = AUTH_IDLE;
if((ADHOC_NETWORK & networkType)) {
if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@ -487,75 +495,84 @@ ar6k_cfg80211_connect_event(struct ar6_softc *ar, u16 channel,
((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS),
((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS));
if(!bss) {
if (ADHOC_NETWORK & networkType) {
/*
* Earlier we were updating the cfg about bss by making a beacon frame
* only if the entry for bss is not there. This can have some issue if
* ROAM event is generated and a heavy traffic is ongoing. The ROAM
* event is handled through a work queue and by the time it really gets
* handled, BSS would have been aged out. So it is better to update the
* cfg about BSS irrespective of its entry being present right now or
* not.
*/
if (ADHOC_NETWORK & networkType) {
/* construct 802.11 mgmt beacon */
if(ptr_ie_buf) {
*ptr_ie_buf++ = WLAN_EID_SSID;
*ptr_ie_buf++ = ar->arSsidLen;
memcpy(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
ptr_ie_buf +=ar->arSsidLen;
*ptr_ie_buf++ = WLAN_EID_SSID;
*ptr_ie_buf++ = ar->arSsidLen;
memcpy(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
ptr_ie_buf +=ar->arSsidLen;
*ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
*ptr_ie_buf++ = 2; /* length */
*ptr_ie_buf++ = 0; /* ATIM window */
*ptr_ie_buf++ = 0; /* ATIM window */
*ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
*ptr_ie_buf++ = 2; /* length */
*ptr_ie_buf++ = 0; /* ATIM window */
*ptr_ie_buf++ = 0; /* ATIM window */
/* TODO: update ibss params and include supported rates,
* DS param set, extened support rates, wmm. */
/* TODO: update ibss params and include supported rates,
* DS param set, extened support rates, wmm. */
ie_buf_len = ptr_ie_buf - ie_buf;
ie_buf_len = ptr_ie_buf - ie_buf;
}
capability |= IEEE80211_CAPINFO_IBSS;
if(WEP_CRYPT == ar->arPairwiseCrypto) {
capability |= IEEE80211_CAPINFO_PRIVACY;
capability |= IEEE80211_CAPINFO_PRIVACY;
}
memcpy(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN);
ptr_ie_buf = ie_buf;
} else {
} else {
capability = *(u16 *)(&assocInfo[beaconIeLen]);
memcpy(source_mac, bssid, ATH_MAC_LEN);
ptr_ie_buf = assocReqIe;
ie_buf_len = assocReqLen;
}
}
size = offsetof(struct ieee80211_mgmt, u)
+ sizeof(mgmt->u.beacon)
+ ie_buf_len;
size = offsetof(struct ieee80211_mgmt, u)
+ sizeof(mgmt->u.beacon)
+ ie_buf_len;
ieeemgmtbuf = A_MALLOC_NOWAIT(size);
if(!ieeemgmtbuf) {
ieeemgmtbuf = A_MALLOC_NOWAIT(size);
if(!ieeemgmtbuf) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: ieeeMgmtbuf alloc error\n", __func__));
cfg80211_put_bss(bss);
return;
}
A_MEMZERO(ieeemgmtbuf, size);
mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
memcpy(mgmt->da, bcast_mac, ATH_MAC_LEN);
memcpy(mgmt->sa, source_mac, ATH_MAC_LEN);
memcpy(mgmt->bssid, bssid, ATH_MAC_LEN);
mgmt->u.beacon.beacon_int = beaconInterval;
mgmt->u.beacon.capab_info = capability;
memcpy(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
("%s: inform bss with bssid %pM channel %d beaconInterval %d "
"capability 0x%x\n", __func__, mgmt->bssid,
ibss_channel->hw_value, beaconInterval, capability));
bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
ibss_channel, mgmt,
le16_to_cpu(size),
signal, GFP_KERNEL);
A_FREE(ieeemgmtbuf);
cfg80211_put_bss(bss);
}
A_MEMZERO(ieeemgmtbuf, size);
mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
memcpy(mgmt->da, bcast_mac, ATH_MAC_LEN);
memcpy(mgmt->sa, source_mac, ATH_MAC_LEN);
memcpy(mgmt->bssid, bssid, ATH_MAC_LEN);
mgmt->u.beacon.beacon_int = beaconInterval;
mgmt->u.beacon.capab_info = capability;
memcpy(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
("%s: inform bss with bssid %pM channel %d beaconInterval %d "
"capability 0x%x\n", __func__, mgmt->bssid,
ibss_channel->hw_value, beaconInterval, capability));
bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
ibss_channel, mgmt,
le16_to_cpu(size),
signal, GFP_KERNEL);
kfree(ieeemgmtbuf);
cfg80211_put_bss(bss);
if((ADHOC_NETWORK & networkType)) {
cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
return;
@ -625,8 +642,14 @@ ar6k_cfg80211_disconnect_event(struct ar6_softc *ar, u8 reason,
u8 *assocInfo, u16 protocolReasonStatus)
{
u16 status;
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason));
if (ar->scan_request) {
cfg80211_scan_done(ar->scan_request, true);
ar->scan_request = NULL;
}
if((ADHOC_NETWORK & ar->arNetworkType)) {
if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@ -651,23 +674,70 @@ ar6k_cfg80211_disconnect_event(struct ar6_softc *ar, u8 reason,
/* connect cmd failed */
wmi_disconnect_cmd(ar->arWmi);
} else if (reason == DISCONNECT_CMD) {
/* connection loss due to disconnect cmd or low rssi */
ar->arConnectPending = false;
if (ar->smeState == SME_CONNECTING) {
cfg80211_connect_result(ar->arNetDev, bssid,
NULL, 0,
NULL, 0,
WLAN_STATUS_UNSPECIFIED_FAILURE,
GFP_KERNEL);
} else {
cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL);
}
ar->smeState = SME_DISCONNECTED;
}
if (ar->arAutoAuthStage) {
/*
* If the current auth algorithm is open try shared
* and make autoAuthStage idle. We do not make it
* leap for now being.
*/
if (ar->arDot11AuthMode == OPEN_AUTH) {
struct ar_key *key = NULL;
key = &ar->keys[ar->arDefTxKeyIndex];
if (down_interruptible(&ar->arSem)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
return;
}
ar->arDot11AuthMode = SHARED_AUTH;
ar->arAutoAuthStage = AUTH_IDLE;
wmi_addKey_cmd(ar->arWmi, ar->arDefTxKeyIndex,
ar->arPairwiseCrypto,
GROUP_USAGE | TX_USAGE,
key->key_len,
NULL,
key->key, KEY_OP_INIT_VAL, NULL,
NO_SYNC_WMIFLAG);
status = wmi_connect_cmd(ar->arWmi,
ar->arNetworkType,
ar->arDot11AuthMode,
ar->arAuthMode,
ar->arPairwiseCrypto,
ar->arPairwiseCryptoLen,
ar->arGroupCrypto,
ar->arGroupCryptoLen,
ar->arSsidLen,
ar->arSsid,
ar->arReqBssid,
ar->arChannelHint,
ar->arConnectCtrlFlags);
up(&ar->arSem);
} else if (ar->arDot11AuthMode == SHARED_AUTH) {
/* should not reach here */
}
} else {
ar->arConnectPending = false;
if (ar->smeState == SME_CONNECTING) {
cfg80211_connect_result(ar->arNetDev, bssid,
NULL, 0,
NULL, 0,
WLAN_STATUS_UNSPECIFIED_FAILURE,
GFP_KERNEL);
} else {
cfg80211_disconnected(ar->arNetDev,
reason,
NULL, 0,
GFP_KERNEL);
}
ar->smeState = SME_DISCONNECTED;
}
}
} else {
if (reason != DISCONNECT_CMD) {
wmi_disconnect_cmd(ar->arWmi);
}
if (reason != DISCONNECT_CMD)
wmi_disconnect_cmd(ar->arWmi);
}
}
@ -729,7 +799,7 @@ ar6k_cfg80211_scan_node(void *arg, bss_t *ni)
le16_to_cpu(size),
signal, GFP_KERNEL);
A_FREE (ieeemgmtbuf);
kfree (ieeemgmtbuf);
}
static int
@ -1205,10 +1275,10 @@ ar6k_cfg80211_set_power_mgmt(struct wiphy *wiphy,
if(pmgmt) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__));
pwrMode.powerMode = MAX_PERF_POWER;
pwrMode.powerMode = REC_POWER;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__));
pwrMode.powerMode = REC_POWER;
pwrMode.powerMode = MAX_PERF_POWER;
}
if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != 0) {
@ -1391,6 +1461,151 @@ u32 cipher_suites[] = {
WLAN_CIPHER_SUITE_CCMP,
};
bool is_rate_legacy(s32 rate)
{
static const s32 legacy[] = { 1000, 2000, 5500, 11000,
6000, 9000, 12000, 18000, 24000,
36000, 48000, 54000 };
u8 i;
for (i = 0; i < ARRAY_SIZE(legacy); i++) {
if (rate == legacy[i])
return true;
}
return false;
}
bool is_rate_ht20(s32 rate, u8 *mcs, bool *sgi)
{
static const s32 ht20[] = { 6500, 13000, 19500, 26000, 39000,
52000, 58500, 65000, 72200 };
u8 i;
for (i = 0; i < ARRAY_SIZE(ht20); i++) {
if (rate == ht20[i]) {
if (i == ARRAY_SIZE(ht20) - 1)
/* last rate uses sgi */
*sgi = true;
else
*sgi = false;
*mcs = i;
return true;
}
}
return false;
}
bool is_rate_ht40(s32 rate, u8 *mcs, bool *sgi)
{
static const s32 ht40[] = { 13500, 27000, 40500, 54000,
81000, 108000, 121500, 135000,
150000 };
u8 i;
for (i = 0; i < ARRAY_SIZE(ht40); i++) {
if (rate == ht40[i]) {
if (i == ARRAY_SIZE(ht40) - 1)
/* last rate uses sgi */
*sgi = true;
else
*sgi = false;
*mcs = i;
return true;
}
}
return false;
}
static int ar6k_get_station(struct wiphy *wiphy, struct net_device *dev,
u8 *mac, struct station_info *sinfo)
{
struct ar6_softc *ar = ar6k_priv(dev);
long left;
bool sgi;
s32 rate;
int ret;
u8 mcs;
if (memcmp(mac, ar->arBssid, ETH_ALEN) != 0)
return -ENOENT;
if (down_interruptible(&ar->arSem))
return -EBUSY;
ar->statsUpdatePending = true;
ret = wmi_get_stats_cmd(ar->arWmi);
if (ret != 0) {
up(&ar->arSem);
return -EIO;
}
left = wait_event_interruptible_timeout(arEvent,
ar->statsUpdatePending == false,
wmitimeout * HZ);
up(&ar->arSem);
if (left == 0)
return -ETIMEDOUT;
else if (left < 0)
return left;
if (ar->arTargetStats.rx_bytes) {
sinfo->rx_bytes = ar->arTargetStats.rx_bytes;
sinfo->filled |= STATION_INFO_RX_BYTES;
sinfo->rx_packets = ar->arTargetStats.rx_packets;
sinfo->filled |= STATION_INFO_RX_PACKETS;
}
if (ar->arTargetStats.tx_bytes) {
sinfo->tx_bytes = ar->arTargetStats.tx_bytes;
sinfo->filled |= STATION_INFO_TX_BYTES;
sinfo->tx_packets = ar->arTargetStats.tx_packets;
sinfo->filled |= STATION_INFO_TX_PACKETS;
}
sinfo->signal = ar->arTargetStats.cs_rssi;
sinfo->filled |= STATION_INFO_SIGNAL;
rate = ar->arTargetStats.tx_unicast_rate;
if (is_rate_legacy(rate)) {
sinfo->txrate.legacy = rate / 100;
} else if (is_rate_ht20(rate, &mcs, &sgi)) {
if (sgi) {
sinfo->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
sinfo->txrate.mcs = mcs - 1;
} else {
sinfo->txrate.mcs = mcs;
}
sinfo->txrate.flags |= RATE_INFO_FLAGS_MCS;
} else if (is_rate_ht40(rate, &mcs, &sgi)) {
if (sgi) {
sinfo->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
sinfo->txrate.mcs = mcs - 1;
} else {
sinfo->txrate.mcs = mcs;
}
sinfo->txrate.flags |= RATE_INFO_FLAGS_40_MHZ_WIDTH;
sinfo->txrate.flags |= RATE_INFO_FLAGS_MCS;
} else {
WARN(1, "invalid rate: %d", rate);
return 0;
}
sinfo->filled |= STATION_INFO_TX_BITRATE;
return 0;
}
static struct
cfg80211_ops ar6k_cfg80211_ops = {
.change_virtual_intf = ar6k_cfg80211_change_iface,
@ -1411,6 +1626,7 @@ cfg80211_ops ar6k_cfg80211_ops = {
.set_power_mgmt = ar6k_cfg80211_set_power_mgmt,
.join_ibss = ar6k_cfg80211_join_ibss,
.leave_ibss = ar6k_cfg80211_leave_ibss,
.get_station = ar6k_get_station,
};
struct wireless_dev *

574
drivers/staging/ath6kl/os/linux/eeprom.c
View File

@ -1,574 +0,0 @@
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Communications Inc.
// All rights reserved.
//
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#include "ar6000_drv.h"
#include "htc.h"
#include <linux/fs.h>
#include "AR6002/hw2.0/hw/gpio_reg.h"
#include "AR6002/hw2.0/hw/si_reg.h"
//
// defines
//
#define MAX_FILENAME 1023
#define EEPROM_WAIT_LIMIT 16
#define HOST_INTEREST_ITEM_ADDRESS(item) \
(AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
#define EEPROM_SZ 768
/* soft mac */
#define ATH_MAC_LEN 6
#define ATH_SOFT_MAC_TMP_BUF_LEN 64
unsigned char mac_addr[ATH_MAC_LEN];
unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
char *p_mac = NULL;
/* soft mac */
//
// static variables
//
static u8 eeprom_data[EEPROM_SZ];
static u32 sys_sleep_reg;
static struct hif_device *p_bmi_device;
//
// Functions
//
/* soft mac */
static int
wmic_ether_aton(const char *orig, u8 *eth)
{
const char *bufp;
int i;
i = 0;
for(bufp = orig; *bufp != '\0'; ++bufp) {
unsigned int val;
int h, l;
h = hex_to_bin(*bufp++);
if (h < 0) {
printk("%s: MAC value is invalid\n", __FUNCTION__);
break;
}
l = hex_to_bin(*bufp++);
if (l < 0) {
printk("%s: MAC value is invalid\n", __FUNCTION__);
break;
}
val = (h << 4) | l;
eth[i] = (unsigned char) (val & 0377);
if(++i == ATH_MAC_LEN) {
/* That's it. Any trailing junk? */
if (*bufp != '\0') {
return 0;
}
return 1;
}
if (*bufp != ':')
break;
}
return 0;
}
static void
update_mac(unsigned char *eeprom, int size, unsigned char *macaddr)
{
int i;
u16 *ptr = (u16 *)(eeprom+4);
u16 checksum = 0;
memcpy(eeprom+10,macaddr,6);
*ptr = 0;
ptr = (u16 *)eeprom;
for (i=0; i<size; i+=2) {
checksum ^= *ptr++;
}
checksum = ~checksum;
ptr = (u16 *)(eeprom+4);
*ptr = checksum;
return;
}
/* soft mac */
/* Read a Target register and return its value. */
inline void
BMI_read_reg(u32 address, u32 *pvalue)
{
BMIReadSOCRegister(p_bmi_device, address, pvalue);
}
/* Write a value to a Target register. */
inline void
BMI_write_reg(u32 address, u32 value)
{
BMIWriteSOCRegister(p_bmi_device, address, value);
}
/* Read Target memory word and return its value. */
inline void
BMI_read_mem(u32 address, u32 *pvalue)
{
BMIReadMemory(p_bmi_device, address, (u8*)(pvalue), 4);
}
/* Write a word to a Target memory. */
inline void
BMI_write_mem(u32 address, u8 *p_data, u32 sz)
{
BMIWriteMemory(p_bmi_device, address, (u8*)(p_data), sz);
}
/*
* Enable and configure the Target's Serial Interface
* so we can access the EEPROM.
*/
static void
enable_SI(struct hif_device *p_device)
{
u32 regval;
printk("%s\n", __FUNCTION__);
p_bmi_device = p_device;
BMI_read_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
BMI_read_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, &regval);
regval &= ~RESET_CONTROL_SI0_RST_MASK;
BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, &regval);
regval &= ~GPIO_PIN0_CONFIG_MASK;
BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, &regval);
regval &= ~GPIO_PIN1_CONFIG_MASK;
BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
/* SI_CONFIG = 0x500a6; */
regval = SI_CONFIG_BIDIR_OD_DATA_SET(1) |
SI_CONFIG_I2C_SET(1) |
SI_CONFIG_POS_SAMPLE_SET(1) |
SI_CONFIG_INACTIVE_CLK_SET(1) |
SI_CONFIG_INACTIVE_DATA_SET(1) |
SI_CONFIG_DIVIDER_SET(6);
BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
}
static void
disable_SI(void)
{
u32 regval;
printk("%s\n", __FUNCTION__);
BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
regval |= CLOCK_CONTROL_SI0_CLK_MASK;
BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
}
/*
* Tell the Target to start an 8-byte read from EEPROM,
* putting the results in Target RX_DATA registers.
*/
static void
request_8byte_read(int offset)
{
u32 regval;
// printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
/* SI_TX_DATA0 = read from offset */
regval =(0xa1<<16)|
((offset & 0xff)<<8) |
(0xa0 | ((offset & 0xff00)>>7));
BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
regval = SI_CS_START_SET(1) |
SI_CS_RX_CNT_SET(8) |
SI_CS_TX_CNT_SET(3);
BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
}
/*
* Tell the Target to start a 4-byte write to EEPROM,
* writing values from Target TX_DATA registers.
*/
static void
request_4byte_write(int offset, u32 data)
{
u32 regval;
printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
/* SI_TX_DATA0 = write data to offset */
regval = ((data & 0xffff) <<16) |
((offset & 0xff)<<8) |
(0xa0 | ((offset & 0xff00)>>7));
BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
regval = data >> 16;
BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
regval = SI_CS_START_SET(1) |
SI_CS_RX_CNT_SET(0) |
SI_CS_TX_CNT_SET(6);
BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
}
/*
* Check whether or not an EEPROM request that was started
* earlier has completed yet.
*/
static bool
request_in_progress(void)
{
u32 regval;
/* Wait for DONE_INT in SI_CS */
BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
if (regval & SI_CS_DONE_ERR_MASK) {
printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
}
return (!(regval & SI_CS_DONE_INT_MASK));
}
/*
* try to detect the type of EEPROM,16bit address or 8bit address
*/
static void eeprom_type_detect(void)
{
u32 regval;
u8 i = 0;
request_8byte_read(0x100);
/* Wait for DONE_INT in SI_CS */
do{
BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
if (regval & SI_CS_DONE_ERR_MASK) {
printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);
break;
}
if (i++ == EEPROM_WAIT_LIMIT) {
printk("%s: EEPROM not responding\n", __FUNCTION__);
}
} while(!(regval & SI_CS_DONE_INT_MASK));
}
/*
* Extract the results of a completed EEPROM Read request
* and return them to the caller.
*/
inline void
read_8byte_results(u32 *data)
{
/* Read SI_RX_DATA0 and SI_RX_DATA1 */
BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
}
/*
* Wait for a previously started command to complete.
* Timeout if the command is takes "too long".
*/
static void
wait_for_eeprom_completion(void)
{
int i=0;
while (request_in_progress()) {
if (i++ == EEPROM_WAIT_LIMIT) {
printk("%s: EEPROM not responding\n", __FUNCTION__);
}
}
}
/*
* High-level function which starts an 8-byte read,
* waits for it to complete, and returns the result.
*/
static void
fetch_8bytes(int offset, u32 *data)
{
request_8byte_read(offset);
wait_for_eeprom_completion();
read_8byte_results(data);
/* Clear any pending intr */
BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
}
/*
* High-level function which starts a 4-byte write,
* and waits for it to complete.
*/
inline void
commit_4bytes(int offset, u32 data)
{
request_4byte_write(offset, data);
wait_for_eeprom_completion();
}
/* ATHENV */
#ifdef ANDROID_ENV
void eeprom_ar6000_transfer(struct hif_device *device, char *fake_file, char *p_mac)
{
u32 first_word;
u32 board_data_addr;
int i;
printk("%s: Enter\n", __FUNCTION__);
enable_SI(device);
eeprom_type_detect();
if (fake_file) {
/*
* Transfer from file to Target RAM.
* Fetch source data from file.
*/
mm_segment_t oldfs;
struct file *filp;
struct inode *inode = NULL;
int length;
/* open file */
oldfs = get_fs();
set_fs(KERNEL_DS);
filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
if (IS_ERR(filp)) {
printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
set_fs(oldfs);
return;
}
if (!filp->f_op) {
printk("%s: File Operation Method Error\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
inode = GET_INODE_FROM_FILEP(filep);
if (!inode) {
printk("%s: Get inode from filp failed\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
/* file's size */
length = i_size_read(inode->i_mapping->host);
printk("%s: length=%d\n", __FUNCTION__, length);
if (length != EEPROM_SZ) {
printk("%s: The file's size is not as expected\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
/* read data */
if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
printk("%s: file read error\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
/* read data out successfully */
filp_close(filp, NULL);
set_fs(oldfs);
} else {
/*
* Read from EEPROM to file OR transfer from EEPROM to Target RAM.
* Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
*/
fetch_8bytes(0, (u32 *)(&eeprom_data[0]));
/* Check the first word of EEPROM for validity */
first_word = *((u32 *)eeprom_data);
if ((first_word == 0) || (first_word == 0xffffffff)) {
printk("Did not find EEPROM with valid Board Data.\n");
}
for (i=8; i<EEPROM_SZ; i+=8) {
fetch_8bytes(i, (u32 *)(&eeprom_data[i]));
}
}
/* soft mac */
if (p_mac) {
mm_segment_t oldfs;
struct file *filp;
struct inode *inode = NULL;
int length;
/* open file */
oldfs = get_fs();
set_fs(KERNEL_DS);
filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
printk("%s try to open file %s\n", __FUNCTION__, p_mac);
if (IS_ERR(filp)) {
printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
set_fs(oldfs);
return;
}
if (!filp->f_op) {
printk("%s: File Operation Method Error\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
inode = GET_INODE_FROM_FILEP(filep);
if (!inode) {
printk("%s: Get inode from filp failed\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
/* file's size */
length = i_size_read(inode->i_mapping->host);
printk("%s: length=%d\n", __FUNCTION__, length);
if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
/* read data */
if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
printk("%s: file read error\n", __FUNCTION__);
filp_close(filp, NULL);
set_fs(oldfs);
return;
}
#if 0
/* the data we just read */
printk("%s: mac address from the file:\n", __FUNCTION__);
for (i = 0; i < length; i++)
printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
printk("\n");
#endif
/* read data out successfully */
filp_close(filp, NULL);
set_fs(oldfs);
/* convert mac address */
if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
printk("%s: convert mac value fail\n", __FUNCTION__);
return;
}
#if 0
/* the converted mac address */
printk("%s: the converted mac value\n", __FUNCTION__);
for (i = 0; i < ATH_MAC_LEN; i++)
printk("[0x%x],", mac_addr[i]);
printk("\n");
#endif
}
/* soft mac */
/* Determine where in Target RAM to write Board Data */
BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
if (board_data_addr == 0) {
printk("hi_board_data is zero\n");
}
/* soft mac */
#if 1
/* Update MAC address in RAM */
if (p_mac) {
update_mac(eeprom_data, EEPROM_SZ, mac_addr);
}
#endif
#if 0
/* mac address in eeprom array */
printk("%s: mac values in eeprom array\n", __FUNCTION__);
for (i = 10; i < 10 + 6; i++)
printk("[0x%x],", eeprom_data[i]);
printk("\n");
#endif
/* soft mac */
/* Write EEPROM data to Target RAM */
BMI_write_mem(board_data_addr, ((u8 *)eeprom_data), EEPROM_SZ);
/* Record the fact that Board Data IS initialized */
{
u32 one = 1;
BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
(u8 *)&one, sizeof(u32));
}
disable_SI();
}
#endif
/* ATHENV */

1
drivers/staging/ath6kl/os/linux/export_hci_transport.c
View File

@ -23,7 +23,6 @@
//==============================================================================
#include <a_config.h>
#include <athdefs.h>
#include "a_types.h"
#include "a_osapi.h"
#include "htc_api.h"
#include "a_drv.h"

Some files were not shown because too many files have changed in this diff Show More