mirror of https://gitee.com/openkylin/linux.git
PCI: Add Loongson PCI Controller support
This controller can be found on Loongson-2K SoC, Loongson-3 systems with RS780E/LS7A PCH. The RS780E part of code was previously located at arch/mips/pci/ops-loongson3.c and now it can use generic PCI driver implementation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
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The Hyper-V PCI Interface is a helper driver allows other drivers to
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have a common interface with the Hyper-V PCI frontend driver.
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config PCI_LOONGSON
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bool "LOONGSON PCI Controller"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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depends on OF
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depends on PCI_QUIRKS
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default MACH_LOONGSON64
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help
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Say Y here if you want to enable PCI controller support on
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Loongson systems.
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source "drivers/pci/controller/dwc/Kconfig"
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source "drivers/pci/controller/mobiveil/Kconfig"
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source "drivers/pci/controller/cadence/Kconfig"
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@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
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obj-$(CONFIG_VMD) += vmd.o
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obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
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obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
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# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
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obj-y += dwc/
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obj-y += mobiveil/
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@ -0,0 +1,247 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Loongson PCI Host Controller Driver
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*
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* Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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*/
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#include <linux/of_device.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include "../pci.h"
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/* Device IDs */
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#define DEV_PCIE_PORT_0 0x7a09
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#define DEV_PCIE_PORT_1 0x7a19
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#define DEV_PCIE_PORT_2 0x7a29
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#define DEV_LS2K_APB 0x7a02
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#define DEV_LS7A_CONF 0x7a10
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#define DEV_LS7A_LPC 0x7a0c
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#define FLAG_CFG0 BIT(0)
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#define FLAG_CFG1 BIT(1)
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#define FLAG_DEV_FIX BIT(2)
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struct loongson_pci {
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void __iomem *cfg0_base;
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void __iomem *cfg1_base;
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struct platform_device *pdev;
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u32 flags;
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};
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/* Fixup wrong class code in PCIe bridges */
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static void bridge_class_quirk(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_0, bridge_class_quirk);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_1, bridge_class_quirk);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_2, bridge_class_quirk);
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static void system_bus_quirk(struct pci_dev *pdev)
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{
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/*
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* The address space consumed by these devices is outside the
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* resources of the host bridge.
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*/
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pdev->mmio_always_on = 1;
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pdev->non_compliant_bars = 1;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS2K_APB, system_bus_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_CONF, system_bus_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_LPC, system_bus_quirk);
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static void loongson_mrrs_quirk(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->bus;
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struct pci_dev *bridge;
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static const struct pci_device_id bridge_devids[] = {
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
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{ 0, },
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};
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/* look for the matching bridge */
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while (!pci_is_root_bus(bus)) {
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bridge = bus->self;
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bus = bus->parent;
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/*
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* Some Loongson PCIe ports have a h/w limitation of
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* 256 bytes maximum read request size. They can't handle
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* anything larger than this. So force this limit on
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* any devices attached under these ports.
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*/
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if (pci_match_id(bridge_devids, bridge)) {
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if (pcie_get_readrq(dev) > 256) {
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pci_info(dev, "limiting MRRS to 256\n");
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pcie_set_readrq(dev, 256);
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}
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break;
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}
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}
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
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static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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if (bus != 0)
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addroff |= BIT(28); /* Type 1 Access */
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addroff |= (where & 0xff) | ((where & 0xf00) << 16);
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addroff |= (bus << 16) | (devfn << 8);
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return priv->cfg1_base + addroff;
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}
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static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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if (bus != 0)
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addroff |= BIT(24); /* Type 1 Access */
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addroff |= (bus << 16) | (devfn << 8) | where;
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return priv->cfg0_base + addroff;
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}
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static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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unsigned char busnum = bus->number;
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struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
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struct loongson_pci *priv = pci_host_bridge_priv(bridge);
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/*
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* Do not read more than one device on the bus other than
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* the host bus. For our hardware the root bus is always bus 0.
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*/
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if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
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PCI_SLOT(devfn) > 0)
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return NULL;
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/* CFG0 can only access standard space */
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if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
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return cfg0_map(priv, busnum, devfn, where);
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/* CFG1 can access extended space */
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if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
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return cfg1_map(priv, busnum, devfn, where);
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return NULL;
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}
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static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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u8 val;
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irq = of_irq_parse_and_map_pci(dev, slot, pin);
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if (irq > 0)
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return irq;
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/* Care i8259 legacy systems */
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
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/* i8259 only have 15 IRQs */
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if (val > 15)
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return 0;
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return val;
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}
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/* H/w only accept 32-bit PCI operations */
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static struct pci_ops loongson_pci_ops = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static const struct of_device_id loongson_pci_of_match[] = {
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{ .compatible = "loongson,ls2k-pci",
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.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
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{ .compatible = "loongson,ls7a-pci",
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.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
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{ .compatible = "loongson,rs780e-pci",
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.data = (void *)(FLAG_CFG0), },
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{}
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};
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static int loongson_pci_probe(struct platform_device *pdev)
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{
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struct loongson_pci *priv;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct pci_host_bridge *bridge;
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struct resource *regs;
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int err;
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if (!node)
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return -ENODEV;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
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if (!bridge)
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return -ENODEV;
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priv = pci_host_bridge_priv(bridge);
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priv->pdev = pdev;
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priv->flags = (unsigned long)of_device_get_match_data(dev);
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs) {
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dev_err(dev, "missing mem resources for cfg0\n");
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return -EINVAL;
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}
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priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg0_base))
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return PTR_ERR(priv->cfg0_base);
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/* CFG1 is optional */
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if (priv->flags & FLAG_CFG1) {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!regs)
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dev_info(dev, "missing mem resource for cfg1\n");
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else {
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priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg1_base))
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priv->cfg1_base = NULL;
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}
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}
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err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
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&bridge->dma_ranges, NULL);
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if (err) {
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dev_err(dev, "failed to get bridge resources\n");
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return err;
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}
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bridge->dev.parent = dev;
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bridge->sysdata = priv;
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bridge->ops = &loongson_pci_ops;
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bridge->map_irq = loongson_map_irq;
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err = pci_host_probe(bridge);
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if (err)
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return err;
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return 0;
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}
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static struct platform_driver loongson_pci_driver = {
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.driver = {
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.name = "loongson-pci",
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.of_match_table = loongson_pci_of_match,
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},
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.probe = loongson_pci_probe,
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};
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builtin_platform_driver(loongson_pci_driver);
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