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drm/amd/display: Fix fclk idle state 

[Why]
The earlier change 'Fix 6x4K displays' led to fclk value
idling at higher DPM level.

[How]
Apply the fix only to respective multi-display configuration.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li 2019-01-17 15:47:54 -05:00 committed by Alex Deucher
parent 6e11ea9de9
commit 1f66b7ea8c
1 changed files with 9 additions and 1 deletions
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10
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
View File

@ -591,7 +591,15 @@ static void dce11_pplib_apply_display_requirements(
dc, dc,
context->bw.dce.sclk_khz); context->bw.dce.sclk_khz);
pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz; /*
* As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
* This is not required for less than 5 displays,
* thus don't request decfclk in dc to avoid impact
* on power saving.
*
*/
pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?
pp_display_cfg->min_engine_clock_khz : 0;
pp_display_cfg->min_engine_clock_deep_sleep_khz pp_display_cfg->min_engine_clock_deep_sleep_khz
= context->bw.dce.sclk_deep_sleep_khz; = context->bw.dce.sclk_deep_sleep_khz;